diff --git a/include/libopencm3/stm32/f3/rcc.h b/include/libopencm3/stm32/f3/rcc.h
index c1a9aec6..34fdb6b9 100644
--- a/include/libopencm3/stm32/f3/rcc.h
+++ b/include/libopencm3/stm32/f3/rcc.h
@@ -327,40 +327,22 @@
 #define RCC_AHBRSTR_FMCRST			(1 << 5)
 
 /* --- RCC_CFGR2 values ---------------------------------------------------- */
-/* ADC34PRES: ADC34 prescaler */
+/* ADCxxPRES: ADCxx prescaler */
 #define RCC_CFGR2_ADC34PRES_SHIFT		9
-#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_1	0x10
-#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_2	0x11
-#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_4	0x12
-#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_6	0x13
-#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_8	0x14
-#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_10	0x15
-#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_12	0x16
-#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_16	0x17
-#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_32	0x18
-#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_64	0x19
-#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_128	0x1A
-#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_256	0x1B
-/* OTHERS */
-/* #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV256	0x */
-
-/* ADC12PRES ADC prescaler */
-/* REVISAR DIRECCIONES */
 #define RCC_CFGR2_ADC12PRES_SHIFT		4
-#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_1	0x10
-#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_2	0x11
-#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_4	0x12
-#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_6	0x13
-#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_8	0x14
-#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_10	0x15
-#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_12	0x16
-#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_16	0x17
-#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_32	0x18
-#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_64	0x19
-#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_128	0x1A
-#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_256	0x1B
-/* OTHERS */
-/* #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV256	0x */
+#define RCC_CFGR2_ADCxPRES_MASK			0x1f
+#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_1	0x10
+#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_2	0x11
+#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_4	0x12
+#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_6	0x13
+#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_8	0x14
+#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_10	0x15
+#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_12	0x16
+#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_16	0x17
+#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_32	0x18
+#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_64	0x19
+#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_128	0x1A
+#define RCC_CFGR2_ADCxPRES_PLL_CLK_DIV_256	0x1B
 
 /* PREDIV[3:0] PREDIV division factor */
 /* REVISAR DIRECCIONES */
@@ -625,6 +607,7 @@ void rcc_set_i2c_clock_sysclk(uint32_t i2c);
 uint32_t rcc_get_i2c_clocks(void);
 void rcc_usb_prescale_1_5(void);
 void rcc_usb_prescale_1(void);
+void rcc_adc_prescale(uint32_t prescale1, uint32_t prescale2);
 
 END_DECLS
 
diff --git a/lib/stm32/f3/rcc.c b/lib/stm32/f3/rcc.c
index df957599..fca6c7b1 100644
--- a/lib/stm32/f3/rcc.c
+++ b/lib/stm32/f3/rcc.c
@@ -462,5 +462,15 @@ void rcc_usb_prescale_1(void)
 {
 	RCC_CFGR |= RCC_CFGR_USBPRES;
 }
+
+void rcc_adc_prescale(uint32_t prescale1, uint32_t prescale2)
+{
+	uint32_t clear_mask = (RCC_CFGR2_ADCxPRES_MASK << RCC_CFGR2_ADC12PRES_SHIFT) |
+		(RCC_CFGR2_ADCxPRES_MASK << RCC_CFGR2_ADC34PRES_SHIFT);
+	uint32_t set = (prescale1 << RCC_CFGR2_ADC12PRES_SHIFT) |
+		(prescale2 << RCC_CFGR2_ADC34PRES_SHIFT);
+	RCC_CFGR2 &= ~(clear_mask);
+	RCC_CFGR2 |= (set);
+}
 /**@}*/