stm32: adc-v2: pull up overrun and EOC flag methods
EOS vs EOSEQ is really a single/multi variant difference, so leave it out.
This commit is contained in:
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b2af9e632c
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5063ea0db7
@ -192,6 +192,12 @@ void adc_enable_dma(uint32_t adc);
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void adc_disable_dma(uint32_t adc);
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void adc_disable_dma(uint32_t adc);
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bool adc_eoc(uint32_t adc);
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bool adc_eoc(uint32_t adc);
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bool adc_eos(uint32_t adc);
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bool adc_eos(uint32_t adc);
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void adc_enable_eoc_interrupt(uint32_t adc);
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void adc_disable_eoc_interrupt(uint32_t adc);
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void adc_enable_overrun_interrupt(uint32_t adc);
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void adc_disable_overrun_interrupt(uint32_t adc);
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bool adc_get_overrun_flag(uint32_t adc);
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void adc_clear_overrun_flag(uint32_t adc);
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uint32_t adc_read_regular(uint32_t adc);
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uint32_t adc_read_regular(uint32_t adc);
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END_DECLS
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END_DECLS
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@ -174,15 +174,9 @@ void adc_enable_watchdog_interrupt(uint32_t adc);
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void adc_disable_watchdog_interrupt(uint32_t adc);
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void adc_disable_watchdog_interrupt(uint32_t adc);
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bool adc_get_watchdog_flag(uint32_t adc);
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bool adc_get_watchdog_flag(uint32_t adc);
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void adc_clear_watchdog_flag(uint32_t adc);
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void adc_clear_watchdog_flag(uint32_t adc);
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void adc_enable_overrun_interrupt(uint32_t adc);
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void adc_disable_overrun_interrupt(uint32_t adc);
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bool adc_get_overrun_flag(uint32_t adc);
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void adc_clear_overrun_flag(uint32_t adc);
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void adc_enable_eoc_sequence_interrupt(uint32_t adc);
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void adc_enable_eoc_sequence_interrupt(uint32_t adc);
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void adc_disable_eoc_sequence_interrupt(uint32_t adc);
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void adc_disable_eoc_sequence_interrupt(uint32_t adc);
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bool adc_get_eoc_sequence_flag(uint32_t adc);
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bool adc_get_eoc_sequence_flag(uint32_t adc);
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void adc_enable_eoc_interrupt(uint32_t adc);
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void adc_disable_eoc_interrupt(uint32_t adc);
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/* Basic configuration */
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/* Basic configuration */
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void adc_set_clk_source(uint32_t adc, uint32_t source);
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void adc_set_clk_source(uint32_t adc, uint32_t source);
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@ -595,8 +595,6 @@ void adc_enable_eos_interrupt_injected(uint32_t adc);
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void adc_disable_eos_interrupt_injected(uint32_t adc);
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void adc_disable_eos_interrupt_injected(uint32_t adc);
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void adc_enable_all_awd_interrupt(uint32_t adc);
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void adc_enable_all_awd_interrupt(uint32_t adc);
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void adc_disable_all_awd_interrupt(uint32_t adc);
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void adc_disable_all_awd_interrupt(uint32_t adc);
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void adc_enable_eoc_interrupt(uint32_t adc);
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void adc_disable_eoc_interrupt(uint32_t adc);
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void adc_enable_eos_interrupt(uint32_t adc);
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void adc_enable_eos_interrupt(uint32_t adc);
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void adc_disable_eos_interrupt(uint32_t adc);
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void adc_disable_eos_interrupt(uint32_t adc);
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void adc_start_conversion_regular(uint32_t adc);
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void adc_start_conversion_regular(uint32_t adc);
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@ -620,10 +618,6 @@ void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger,
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uint32_t polarity);
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uint32_t polarity);
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void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger,
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void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger,
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uint32_t polarity);
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uint32_t polarity);
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void adc_enable_overrun_interrupt(uint32_t adc);
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void adc_disable_overrun_interrupt(uint32_t adc);
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bool adc_get_overrun_flag(uint32_t adc);
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void adc_clear_overrun_flag(uint32_t adc);
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bool adc_awd(uint32_t adc);
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bool adc_awd(uint32_t adc);
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/*void adc_set_dma_continue(uint32_t adc);*/
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/*void adc_set_dma_continue(uint32_t adc);*/
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/*void adc_set_dma_terminate(uint32_t adc);*/
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/*void adc_set_dma_terminate(uint32_t adc);*/
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@ -216,6 +216,72 @@ void adc_disable_dma(uint32_t adc)
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ADC_CFGR1(adc) &= ~ADC_CFGR1_DMAEN;
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ADC_CFGR1(adc) &= ~ADC_CFGR1_DMAEN;
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}
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}
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/** @brief ADC Enable the Overrun Interrupt
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*
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* The overrun interrupt is generated when data is not read from a result
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* register before the next conversion is written. If DMA is enabled, all
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* transfers are terminated and any conversion sequence is aborted.
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_enable_overrun_interrupt(uint32_t adc)
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{
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ADC_IER(adc) |= ADC_IER_OVRIE;
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}
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/** @brief ADC Disable the Overrun Interrupt
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_disable_overrun_interrupt(uint32_t adc)
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{
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ADC_IER(adc) &= ~ADC_IER_OVRIE;
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}
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/** @brief ADC Read the Overrun Flag
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*
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* The overrun flag is set when data is not read from a result register before
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* the next conversion is written. If DMA is enabled, all transfers are
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* terminated and any conversion sequence is aborted.
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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bool adc_get_overrun_flag(uint32_t adc)
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{
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return ADC_ISR(adc) & ADC_ISR_OVR;
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}
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/** @brief ADC Clear Overrun Flags
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*
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* The overrun flag is cleared. Note that if an overrun occurs, DMA is
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* terminated.
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* The flag must be cleared and the DMA stream and ADC reinitialised to resume
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* conversions (see the reference manual).
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_clear_overrun_flag(uint32_t adc)
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{
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ADC_ISR(adc) = ADC_ISR_OVR;
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}
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/** @brief ADC Enable Regular End-Of-Conversion Interrupt
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_enable_eoc_interrupt(uint32_t adc)
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{
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ADC_IER(adc) |= ADC_IER_EOCIE;
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}
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/** @brief ADC Disable Regular End-Of-Conversion Interrupt
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_disable_eoc_interrupt(uint32_t adc)
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{
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ADC_IER(adc) &= ~ADC_IER_EOCIE;
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}
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/** @brief ADC Read from the Regular Conversion Result Register
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/** @brief ADC Read from the Regular Conversion Result Register
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*
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*
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@ -277,63 +277,6 @@ void adc_clear_watchdog_flag(uint32_t adc)
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ADC_ISR(adc) = ADC_ISR_AWD1;
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ADC_ISR(adc) = ADC_ISR_AWD1;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Enable the Overrun Interrupt
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*
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* The overrun interrupt is generated when data is not read from a result
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* register before the next conversion is written. If DMA is enabled, all
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* transfers are terminated and any conversion sequence is aborted.
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_enable_overrun_interrupt(uint32_t adc)
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{
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ADC_IER(adc) |= ADC_IER_OVRIE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Disable the Overrun Interrupt
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_disable_overrun_interrupt(uint32_t adc)
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{
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ADC_IER(adc) &= ~ADC_IER_OVRIE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Read the Overrun Flag
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*
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* The overrun flag is set when data is not read from a result register before
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* the next conversion is written. If DMA is enabled, all transfers are
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* terminated and any conversion sequence is aborted.
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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bool adc_get_overrun_flag(uint32_t adc)
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{
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return ADC_ISR(adc) & ADC_ISR_OVR;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Clear Overrun Flags
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*
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* The overrun flag is cleared. Note that if an overrun occurs, DMA is
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* terminated.
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* The flag must be cleared and the DMA stream and ADC reinitialised to resume
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* conversions (see the reference manual).
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_clear_overrun_flag(uint32_t adc)
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{
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ADC_ISR(adc) = ADC_ISR_OVR;
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}
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Enable Regular End-Of-Conversion Sequence Interrupt
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/** @brief ADC Enable Regular End-Of-Conversion Sequence Interrupt
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*
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*
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@ -367,27 +310,6 @@ bool adc_get_eoc_sequence_flag(uint32_t adc)
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return ADC_ISR(adc) & ADC_ISR_EOSEQ;
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return ADC_ISR(adc) & ADC_ISR_EOSEQ;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Enable Regular End-Of-Conversion Interrupt
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_enable_eoc_interrupt(uint32_t adc)
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{
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ADC_IER(adc) |= ADC_IER_EOCIE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Disable Regular End-Of-Conversion Interrupt
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*
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* @param[in] adc Unsigned int32. ADC base address (@ref adc_reg_base)
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*/
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void adc_disable_eoc_interrupt(uint32_t adc)
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{
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ADC_IER(adc) &= ~ADC_IER_EOCIE;
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}
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/**@}*/
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/**@}*/
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@ -405,30 +405,6 @@ void adc_disable_all_awd_interrupt(uint32_t adc)
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ADC_IER(adc) &= ~ADC_IER_AWD3IE;
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ADC_IER(adc) &= ~ADC_IER_AWD3IE;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Enable Regular End-Of-Conversion Interrupt
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*
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* @param[in] adc Unsigned int32. ADC block register address base @ref
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* adc_reg_base
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*/
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void adc_enable_eoc_interrupt(uint32_t adc)
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{
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ADC_IER(adc) |= ADC_IER_EOCIE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Disable Regular End-Of-Conversion Interrupt
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*
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* @param[in] adc Unsigned int32. ADC block register address base @ref
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* adc_reg_base
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*/
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void adc_disable_eoc_interrupt(uint32_t adc)
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{
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ADC_IER(adc) &= ~ADC_IER_EOCIE;
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}
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Enable Regular End-Of-Sequence Interrupt
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/** @brief ADC Enable Regular End-Of-Sequence Interrupt
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*
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*
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@ -869,70 +845,6 @@ void adc_disable_external_trigger_injected(uint32_t adc)
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ADC_JSQR(adc) &= ~ADC_JSQR_JEXTEN_MASK;
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ADC_JSQR(adc) &= ~ADC_JSQR_JEXTEN_MASK;
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}
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Enable the Overrun Interrupt
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*
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* The overrun interrupt is generated when data is not read from a result
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* register before the next conversion is written. If DMA is enabled, all
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* transfers are terminated and any conversion sequence is aborted.
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*
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* @param[in] adc Unsigned int32. ADC block register address base @ref
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* adc_reg_base
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*/
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void adc_enable_overrun_interrupt(uint32_t adc)
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{
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ADC_IER(adc) |= ADC_IER_OVRIE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Disable the Overrun Interrupt
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*
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* @param[in] adc Unsigned int32. ADC block register address base @ref
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* adc_reg_base
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*/
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void adc_disable_overrun_interrupt(uint32_t adc)
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{
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ADC_IER(adc) &= ~ADC_IER_OVRIE;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Read the Overrun Flag
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*
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* The overrun flag is set when data is not read from a result register before
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* the next conversion is written. If DMA is enabled, all transfers are
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* terminated and any conversion sequence is aborted.
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*
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* @param[in] adc Unsigned int32. ADC block register address base @ref
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* adc_reg_base
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* @returns Unsigned int32 conversion result.
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*/
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bool adc_get_overrun_flag(uint32_t adc)
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{
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return ADC_ISR(adc) & ADC_ISR_OVR;
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}
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Clear Overrun Flags
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*
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* The overrun flag is cleared. Note that if an overrun occurs, DMA is
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* terminated.
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* The flag must be cleared and the DMA stream and ADC reinitialised to resume
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* conversions (see the reference manual).
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*
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* @param[in] adc Unsigned int32. ADC block register address base
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* @ref adc_reg_base
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* @returns Unsigned int32 conversion result.
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*/
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void adc_clear_overrun_flag(uint32_t adc)
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{
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/* r_w1 bit */
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ADC_ISR(adc) |= ADC_ISR_OVR;
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}
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief ADC Set DMA to Continue
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/** @brief ADC Set DMA to Continue
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*
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*
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