diff --git a/include/libopencm3/efm32/common/acmp_common.h b/include/libopencm3/efm32/common/acmp_common.h new file mode 100644 index 00000000..1377e663 --- /dev/null +++ b/include/libopencm3/efm32/common/acmp_common.h @@ -0,0 +1,185 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2015 Kuldeep Singh Dhaka + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_EFM32_ACMP_H +#define LIBOPENCM3_EFM32_ACMP_H + +#include +#include + +#define ACMP_CTRL(base) ((base) + 0x000) +#define ACMP_INPUTSEL(base) ((base) + 0x004) +#define ACMP_STATUS(base) ((base) + 0x008) +#define ACMP_IEN(base) ((base) + 0x00C) +#define ACMP_IF(base) ((base) + 0x010) +#define ACMP_IFS(base) ((base) + 0x014) +#define ACMP_IFC(base) ((base) + 0x018) +#define ACMP_ROUTE(base) ((base) + 0x01C) + +/* ACMP_CTRL */ +#define ACMP_CTRL_FULLBIAS (1 << 31) +#define ACMP_CTRL_HALFBIAS (1 << 30) + +#define ACMP_CTRL_BIASPROG_SHIFT (24) +#define ACMP_CTRL_BIASPROG_MASK (0xF << ACMP_CTRL_BIASPROG_SHIFT) +#define ACMP_CTRL_BIASPROG(v) \ + (((v) << ACMP_CTRL_BIASPROG_SHIFT) & ACMP_CTRL_BIASPROG_MASK) + +#define ACMP_CTRL_IFALL (1 << 17) +#define ACMP_CTRL_IRISE (1 << 16) + +#define ACMP_CTRL_WARMTIME_SHIFT (8) +#define ACMP_CTRL_WARMTIME_MASK (0x7 << ACMP_CTRL_WARMTIME_SHIFT) +#define ACMP_CTRL_WARMTIME(v) \ + (((v) << ACMP_CTRL_WARMTIME_SHIFT) & ACMP_CTRL_WARMTIME_MASK) +#define ACMP_CTRL_WARMTIME_4CYCLES 0 +#define ACMP_CTRL_WARMTIME_8CYCLES 1 +#define ACMP_CTRL_WARMTIME_16CYCLES 2 +#define ACMP_CTRL_WARMTIME_32CYCLES 3 +#define ACMP_CTRL_WARMTIME_64CYCLES 4 +#define ACMP_CTRL_WARMTIME_128CYCLES 5 +#define ACMP_CTRL_WARMTIME_256CYCLES 6 +#define ACMP_CTRL_WARMTIME_512CYCLES 7 + +#define ACMP_CTRL_HYSTSEL_SHIFT (8) +#define ACMP_CTRL_HYSTSEL_MASK (0x7 << ACMP_CTRL_HYSTSEL_SHIFT) +#define ACMP_CTRL_HYSTSEL(v) \ + (((v) << ACMP_CTRL_HYSTSEL_SHIFT) & ACMP_CTRL_HYSTSEL_MASK) +#define ACMP_CTRL_HYSTSEL_HYSTx(x) ACMP_CTRL_HYSTSEL(x) +#define ACMP_CTRL_HYSTSEL_HYST0 0 +#define ACMP_CTRL_HYSTSEL_HYST1 1 +#define ACMP_CTRL_HYSTSEL_HYST2 2 +#define ACMP_CTRL_HYSTSEL_HYST3 3 +#define ACMP_CTRL_HYSTSEL_HYST4 4 +#define ACMP_CTRL_HYSTSEL_HYST5 5 +#define ACMP_CTRL_HYSTSEL_HYST6 6 +#define ACMP_CTRL_HYSTSEL_HYST7 7 + +#define ACMP_CTRL_GPIOINV (1 << 3) +#define ACMP_CTRL_INACTVAL (1 << 2) +#define ACMP_CTRL_MUXEN (1 << 1) +#define ACMP_CTRL_EN (1 << 0) + +/* ACMP_INPUTSEL */ +#define ACMP_INPUTSEL_CSRESSEL_SHIFT (28) +#define ACMP_INPUTSEL_CSRESSEL_MASK (0x3 << ACMP_INPUTSEL_CSRESSEL_SHIFT) +#define ACMP_INPUTSEL_CSRESSEL(v) \ + (((v) << ACMP_INPUTSEL_CSRESSEL_SHIFT) & ACMP_INPUTSEL_CSRESSEL_MASK) +#define ACMP_INPUTSEL_CSRESSEL_RESx(x) ACMP_INPUTSEL_CSRESSEL_RES(x) +#define ACMP_INPUTSEL_CSRESSEL_RES0 ACMP_INPUTSEL_CSRESSEL_RESx(0) +#define ACMP_INPUTSEL_CSRESSEL_RES1 ACMP_INPUTSEL_CSRESSEL_RESx(1) +#define ACMP_INPUTSEL_CSRESSEL_RES2 ACMP_INPUTSEL_CSRESSEL_RESx(2) +#define ACMP_INPUTSEL_CSRESSEL_RES3 ACMP_INPUTSEL_CSRESSEL_RESx(3) + +#define ACMP_INPUTSEL_CSRESEN (1 << 24) +#define ACMP_INPUTSEL_LPREF (1 << 16) + +#define ACMP_INPUTSEL_VDDLEVEL_SHIFT (8) +#define ACMP_INPUTSEL_VDDLEVEL_MASK (0x3F << ACMP_INPUTSEL_VDDLEVEL_SHIFT) +#define ACMP_INPUTSEL_VDDLEVEL(v) \ + (((v) << ACMP_INPUTSEL_VDDLEVEL_SHIFT) & ACMP_INPUTSEL_VDDLEVEL_MASK) + +#define ACMP_INPUTSEL_NEGSEL_SHIFT (8) +#define ACMP_INPUTSEL_NEGSEL_MASK (0x3F << ACMP_INPUTSEL_NEGSEL_SHIFT) +#define ACMP_INPUTSEL_NEGSEL(v) \ + (((v) << ACMP_INPUTSEL_NEGSEL_SHIFT) & ACMP_INPUTSEL_NEGSEL_MASK) +#define ACMP_INPUTSEL_NEGSEL_CHx(x) ACMP_INPUTSEL_NEGSEL(x) +#define ACMP_INPUTSEL_NEGSEL_CH0 0 +#define ACMP_INPUTSEL_NEGSEL_CH1 1 +#define ACMP_INPUTSEL_NEGSEL_CH2 2 +#define ACMP_INPUTSEL_NEGSEL_CH3 3 +#define ACMP_INPUTSEL_NEGSEL_CH4 4 +#define ACMP_INPUTSEL_NEGSEL_CH5 5 +#define ACMP_INPUTSEL_NEGSEL_CH6 6 +#define ACMP_INPUTSEL_NEGSEL_CH7 7 +#define ACMP_INPUTSEL_NEGSEL_1V25 8 +#define ACMP_INPUTSEL_NEGSEL_2V5 9 +#define ACMP_INPUTSEL_NEGSEL_VDD 10 +#define ACMP_INPUTSEL_NEGSEL_CAPSENSE 11 +#define ACMP_INPUTSEL_NEGSEL_DAC0CH0 12 +#define ACMP_INPUTSEL_NEGSEL_DAC0CH1 13 + +#define ACMP_INPUTSEL_POSSEL_SHIFT (0) +#define ACMP_INPUTSEL_POSSEL_MASK (0x7 << ACMP_INPUTSEL_POSSEL_SHIFT) +#define ACMP_INPUTSEL_POSSEL(v) \ + (((v) << ACMP_INPUTSEL_LPOSSELL_SHIFT) & ACMP_INPUTSEL_LPOSSELL_MASK) +#define ACMP_INPUTSEL_POSSEL_CHx(x) ACMP_INPUTSEL_POSSEL(x) +#define ACMP_INPUTSEL_POSSEL_CH0 0 +#define ACMP_INPUTSEL_POSSEL_CH1 1 +#define ACMP_INPUTSEL_POSSEL_CH2 2 +#define ACMP_INPUTSEL_POSSEL_CH3 3 +#define ACMP_INPUTSEL_POSSEL_CH4 4 +#define ACMP_INPUTSEL_POSSEL_CH5 5 +#define ACMP_INPUTSEL_POSSEL_CH6 6 +#define ACMP_INPUTSEL_POSSEL_CH7 7 + +/* ACMP_STATUS */ +#define ACMP_STATUS_ACMPOUT (1 << 1) +#define ACMP_STATUS_ACMPACT (1 << 0) + +/* ACMP_IEN */ +#define ACMP_IEN_WARMUP (1 << 1) +#define ACMP_IEN_EDGE (1 << 0) + +/* ACMP_IF */ +#define ACMP_IF_WARMUP (1 << 1) +#define ACMP_IF_EDGE (1 << 0) + +/* ACMP_IFS */ +#define ACMP_IFS_WARMUP (1 << 1) +#define ACMP_IFS_EDGE (1 << 0) + +/* ACMP_IFC */ +#define ACMP_IFC_WARMUP (1 << 1) +#define ACMP_IFC_EDGE (1 << 0) + +/* ACMP_ROUTE */ +#define ACMP_ROUTE_LOCATION_SHIFT (8) +#define ACMP_ROUTE_LOCATION_MASK (0x7 << ACMP_ROUTE_LOCATION_SHIFT) +#define ACMP_ROUTE_LOCATION(v) \ + (((v) << ACMP_ROUTE_LOCATION_SHIFT) & ACMP_ROUTE_LOCATION_MASK) +#define ACMP_ROUTE_LOCATION_LOCx(x) ACMP_ROUTE_LOCATION(x) +#define ACMP_ROUTE_LOCATION_LOC0 ACMP_ROUTE_LOCATIONx(0) +#define ACMP_ROUTE_LOCATION_LOC1 ACMP_ROUTE_LOCATIONx(1) +#define ACMP_ROUTE_LOCATION_LOC2 ACMP_ROUTE_LOCATIONx(2) + +#define ACMP_ROUTE_ACMPPEN (1 << 0) + +#define ACMP0 ACMP0_BASE +#define ACMP0_CTRL ACMP_CTRL(ACMP0) +#define ACMP0_INPUTSEL ACMP_INPUTSEL(ACMP0) +#define ACMP0_STATUS ACMP_STATUS(ACMP0) +#define ACMP0_IEN ACMP_IEN(ACMP0) +#define ACMP0_IF ACMP_IF(ACMP0) +#define ACMP0_IFS ACMP_IFS(ACMP0) +#define ACMP0_IFC ACMP_IFC(ACMP0) +#define ACMP0_ROUTE ACMP_ROUTE(ACMP0) + +#define ACMP1 ACMP1_BASE +#define ACMP1_CTRL ACMP_CTRL(ACMP1) +#define ACMP1_INPUTSEL ACMP_INPUTSEL(ACMP1) +#define ACMP1_STATUS ACMP_STATUS(ACMP1) +#define ACMP1_IEN ACMP_IEN(ACMP1) +#define ACMP1_IF ACMP_IF(ACMP1) +#define ACMP1_IFS ACMP_IFS(ACMP1) +#define ACMP1_IFC ACMP_IFC(ACMP1) +#define ACMP1_ROUTE ACMP_ROUTE(ACMP1) + +#endif + diff --git a/include/libopencm3/efm32/common/adc_common.h b/include/libopencm3/efm32/common/adc_common.h new file mode 100644 index 00000000..cc41c197 --- /dev/null +++ b/include/libopencm3/efm32/common/adc_common.h @@ -0,0 +1,457 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2015 Kuldeep Singh Dhaka + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_EFM32_ADC_H +#define LIBOPENCM3_EFM32_ADC_H + +#include +#include + +#define ADC_CTRL(base) MMIO32((base) + 0x000) +#define ADC_CMD(base) MMIO32((base) + 0x004) +#define ADC_STATUS(base) MMIO32((base) + 0x008) +#define ADC_SINGLECTRL(base) MMIO32((base) + 0x00C) +#define ADC_SCANCTRL(base) MMIO32((base) + 0x010) +#define ADC_IEN(base) MMIO32((base) + 0x014) +#define ADC_IF(base) MMIO32((base) + 0x018) +#define ADC_IFS(base) MMIO32((base) + 0x01C) +#define ADC_IFC(base) MMIO32((base) + 0x020) +#define ADC_SINGLEDATA(base) MMIO32((base) + 0x024) +#define ADC_SCANDATA(base) MMIO32((base) + 0x028) +#define ADC_SINGLEDATAP(base) MMIO32((base) + 0x02C) +#define ADC_SCANDATAP(base) MMIO32((base) + 0x030) +#define ADC_CAL(base) MMIO32((base) + 0x034) +#define ADC_BIASPROG(base) MMIO32((base) + 0x03C) + +/* ADC_CTRL */ +#define ADC_CTRL_OVERSEL_SHIFT (24) +#define ADC_CTRL_OVERSEL_MASK (0xF << ADC_CTRL_OVERSEL_SHIFT) +#define ADC_CTRL_OVERSEL(v) \ + (((v) << ADC_CTRL_OVERSEL_SHIFT) & ADC_CTRL_OVERSEL_MASK) +#define ADC_CTRL_OVERSEL_X2 0 +#define ADC_CTRL_OVERSEL_X4 1 +#define ADC_CTRL_OVERSEL_X8 2 +#define ADC_CTRL_OVERSEL_X16 3 +#define ADC_CTRL_OVERSEL_X32 4 +#define ADC_CTRL_OVERSEL_X64 5 +#define ADC_CTRL_OVERSEL_X128 6 +#define ADC_CTRL_OVERSEL_X256 7 +#define ADC_CTRL_OVERSEL_X512 8 +#define ADC_CTRL_OVERSEL_X1024 9 +#define ADC_CTRL_OVERSEL_X2048 10 +#define ADC_CTRL_OVERSEL_X4096 11 + +#define ADC_CTRL_TIMEBASE_SHIFT (16) +#define ADC_CTRL_TIMEBASE_MASK (0x3F << ADC_CTRL_TIMEBASE_SHIFT) +#define ADC_CTRL_TIMEBASE(v) \ + (((v) << ADC_CTRL_TIMEBASE_SHIFT) & ADC_CTRL_TIMEBASE_MASK) + +#define ADC_CTRL_PRESC_SHIFT (8) +#define ADC_CTRL_PRESC_MASK (0x3F << ADC_CTRL_PRESC_SHIFT) +#define ADC_CTRL_PRESC(v) \ + (((v) << ADC_CTRL_PRESC_SHIFT) & ADC_CTRL_PRESC_MASK) + +#define ADC_CTRL_LPFMODE_SHIFT (4) +#define ADC_CTRL_LPFMODE_MASK (0x3 << ADC_CTRL_LPFMODE_SHIFT) +#define ADC_CTRL_LPFMODE(v) \ + (((v) << ADC_CTRL_LPFMODE_SHIFT) & ADC_CTRL_LPFMODE_MASK) +#define ADC_CTRL_LPFMODE_BYPASS 0 +#define ADC_CTRL_LPFMODE_DECAP 1 +#define ADC_CTRL_LPFMODE_RCFILT 2 + +#define ADC_CTRL_TAILGATE (1 << 3) + +#define ADC_CTRL_WARMUPMODE_SHIFT (0) +#define ADC_CTRL_WARMUPMODE_MASK (0x3 << ADC_CTRL_WARMUPMODE_SHIFT) +#define ADC_CTRL_WARMUPMODE(v) \ + (((v) << ADC_CTRL_WARMUPMODE_SHIFT) & ADC_CTRL_WARMUPMODE_MASK) +#define ADC_CTRL_WARMUPMODE_NORMAL 0 +#define ADC_CTRL_WARMUPMODE_FASTBG 1 +#define ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM 2 +#define ADC_CTRL_WARMUPMODE_KEEPADCWARM 3 + +/* ADC_CMD */ +#define ADC_CMD_SCANSTOP (1 << 3) +#define ADC_CMD_SCANSTART (1 << 2) +#define ADC_CMD_SINGLESTOP (1 << 1) +#define ADC_CMD_SINGLESTART (1 << 0) + +/* ADC_STATUS */ +#define ADC_STATUS_SCANDATASRC_SHIFT (0) +#define ADC_STATUS_SCANDATASRC_MASK (0x7 << ADC_STATUS_SCANDATASRC_SHIFT) +#define ADC_STATUS_SCANDATASRC(v) \ + (((v) << ADC_STATUS_SCANDATASRC_SHIFT) & ADC_STATUS_SCANDATASRC_MASK) + +#define ADC_STATUS_SCANDV (1 << 17) +#define ADC_STATUS_SINGLEDV (1 << 16) +#define ADC_STATUS_WARM (1 << 12) +#define ADC_STATUS_SCANREFWARM (1 << 9) +#define ADC_STATUS_SINGLEREFWARM (1 << 8) +#define ADC_STATUS_SCANACT (1 << 1) +#define ADC_STATUS_SINGLEACT (1 << 0) + +/* ADC_SINGLECTRL */ +#define ADC_SINGLECTRL_PRSSEL_SHIFT (28) +#define ADC_SINGLECTRL_PRSSEL_MASK (0xF << ADC_SINGLECTRL_PRSSEL_SHIFT) +#define ADC_SINGLECTRL_PRSSEL(v) \ + (((v) << ADC_SINGLECTRL_PRSSEL_SHIFT) & ADC_SINGLECTRL_PRSSEL_MASK) +#define ADC_SINGLECTRL_PRSSEL_PRSCHx(x) ADC_SINGLECTRL_PRSSEL(x) +#define ADC_SINGLECTRL_PRSSEL_PRSCH0 0 +#define ADC_SINGLECTRL_PRSSEL_PRSCH1 1 +#define ADC_SINGLECTRL_PRSSEL_PRSCH2 2 +#define ADC_SINGLECTRL_PRSSEL_PRSCH3 3 +#define ADC_SINGLECTRL_PRSSEL_PRSCH4 4 +#define ADC_SINGLECTRL_PRSSEL_PRSCH5 5 +#define ADC_SINGLECTRL_PRSSEL_PRSCH6 6 +#define ADC_SINGLECTRL_PRSSEL_PRSCH7 7 +#define ADC_SINGLECTRL_PRSSEL_PRSCH8 8 +#define ADC_SINGLECTRL_PRSSEL_PRSCH9 9 +#define ADC_SINGLECTRL_PRSSEL_PRSCH10 10 +#define ADC_SINGLECTRL_PRSSEL_PRSCH11 11 + +#define ADC_SINGLECTRL_PRSEN (1 << 24) + +#define ADC_SINGLECTRL_AT_SHIFT (20) +#define ADC_SINGLECTRL_AT_MASK (0xF << ADC_SINGLECTRL_AT_SHIFT) +#define ADC_SINGLECTRL_AT(v) \ + (((v) << ADC_SINGLECTRL_AT_SHIFT) & ADC_SINGLECTRL_AT_MASK) +#define ADC_SINGLECTRL_AT_1CYCLE 0x0 +#define ADC_SINGLECTRL_AT_2CYCLES 0x1 +#define ADC_SINGLECTRL_AT_4CYCLES 0x2 +#define ADC_SINGLECTRL_AT_8CYCLES 0x3 +#define ADC_SINGLECTRL_AT_16CYCLES 0x4 +#define ADC_SINGLECTRL_AT_32CYCLES 0x5 +#define ADC_SINGLECTRL_AT_64CYCLES 0x6 +#define ADC_SINGLECTRL_AT_128CYCLES 0x7 +#define ADC_SINGLECTRL_AT_256CYCLES 0x8 + +#define ADC_SINGLECTRL_REF_SHIFT (16) +#define ADC_SINGLECTRL_REF_MASK (0xF << ADC_SINGLECTRL_REF_SHIFT) +#define ADC_SINGLECTRL_REF(v) \ + (((v) << ADC_SINGLECTRL_REF_SHIFT) & ADC_SINGLECTRL_REF_MASK) +#define ADC_SINGLECTRL_REF_1V25 0 +#define ADC_SINGLECTRL_REF_2V5 1 +#define ADC_SINGLECTRL_REF_VDD 2 +#define ADC_SINGLECTRL_REF_5VDIFF 3 +#define ADC_SINGLECTRL_REF_EXTSINGLE 4 +#define ADC_SINGLECTRL_REF_2XEXTDIFF 5 +#define ADC_SINGLECTRL_REF_2XVDD 6 + +#define ADC_SINGLECTRL_INPUTSEL_SHIFT (8) +#define ADC_SINGLECTRL_INPUTSEL_MASK (0xF << ADC_SINGLECTRL_INPUTSEL_SHIFT) +#define ADC_SINGLECTRL_INPUTSEL(v) \ + (((v) << ADC_SINGLECTRL_INPUTSEL_SHIFT) & ADC_SINGLECTRL_INPUTSEL_MASK) +/* DIFF=0 */ +#define ADC_SINGLECTRL_INPUTSEL_CHx(x) ADC_SINGLECTRL_INPUTSEL(x) +#define ADC_SINGLECTRL_INPUTSEL_CH0 0 +#define ADC_SINGLECTRL_INPUTSEL_CH1 1 +#define ADC_SINGLECTRL_INPUTSEL_CH2 2 +#define ADC_SINGLECTRL_INPUTSEL_CH3 3 +#define ADC_SINGLECTRL_INPUTSEL_CH4 4 +#define ADC_SINGLECTRL_INPUTSEL_CH5 5 +#define ADC_SINGLECTRL_INPUTSEL_CH6 6 +#define ADC_SINGLECTRL_INPUTSEL_CH7 7 +#define ADC_SINGLECTRL_INPUTSEL_TEMP 8 +#define ADC_SINGLECTRL_INPUTSEL_VDDDIV3 9 +#define ADC_SINGLECTRL_INPUTSEL_VDD 10 +#define ADC_SINGLECTRL_INPUTSEL_VSS 11 +#define ADC_SINGLECTRL_INPUTSEL_VREFDIV2 12 +#define ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 13 +#define ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 14 +/* DIFF=1 */ +#define ADC_SINGLECTRL_INPUTSEL_CH0CH1 0 +#define ADC_SINGLECTRL_INPUTSEL_CH2CH3 1 +#define ADC_SINGLECTRL_INPUTSEL_CH4CH5 2 +#define ADC_SINGLECTRL_INPUTSEL_CH6CH7 3 +#define ADC_SINGLECTRL_INPUTSEL_DIFF0 4 + +#define ADC_SINGLECTRL_RES_SHIFT (4) +#define ADC_SINGLECTRL_RES_MASK (0x3 << ADC_SINGLECTRL_RES_SHIFT) +#define ADC_SINGLECTRL_RES(v) \ + (((v) << ADC_SINGLECTRL_RES_SHIFT) & ADC_SINGLECTRL_RES_MASK) +#define ADC_SINGLECTRL_RES_12BIT 0 +#define ADC_SINGLECTRL_RES_8BIT 1 +#define ADC_SINGLECTRL_RES_6BIT 2 +#define ADC_SINGLECTRL_RES_OVS 3 + +#define ADC_SINGLECTRL_ADJ (1 << 2) +#define ADC_SINGLECTRL_DIFF (1 << 1) +#define ADC_SINGLECTRL_REP (1 << 0) + +/* ADC_SCANCTRL */ +#define ADC_SCANCTRL_PRSSEL_SHIFT (28) +#define ADC_SCANCTRL_PRSSEL_MASK (0xF << ADC_SCANCTRL_PRSSEL_SHIFT) +#define ADC_SCANCTRL_PRSSEL(v) \ + (((v) << ADC_SCANCTRL_PRSSEL_SHIFT) & ADC_SCANCTRL_PRSSEL_MASK) +#define ADC_SCANCTRL_PRSSEL_PRSCHx(x) ADC_SCANCTRL_PRSSEL(x) +#define ADC_SCANCTRL_PRSSEL_PRSCH0 0 +#define ADC_SCANCTRL_PRSSEL_PRSCH1 1 +#define ADC_SCANCTRL_PRSSEL_PRSCH2 2 +#define ADC_SCANCTRL_PRSSEL_PRSCH3 3 +#define ADC_SCANCTRL_PRSSEL_PRSCH4 4 +#define ADC_SCANCTRL_PRSSEL_PRSCH5 5 +#define ADC_SCANCTRL_PRSSEL_PRSCH6 6 +#define ADC_SCANCTRL_PRSSEL_PRSCH7 7 +#define ADC_SCANCTRL_PRSSEL_PRSCH8 8 +#define ADC_SCANCTRL_PRSSEL_PRSCH9 9 +#define ADC_SCANCTRL_PRSSEL_PRSCH10 10 +#define ADC_SCANCTRL_PRSSEL_PRSCH11 11 + +#define ADC_SCANCTRL_PRSEN (1 << 24) + +#define ADC_SCANCTRL_AT_SHIFT (20) +#define ADC_SCANCTRL_AT_MASK (0xF << ADC_SCANCTRL_AT_SHIFT) +#define ADC_SCANCTRL_AT(v) \ + (((v) << ADC_SCANCTRL_AT_SHIFT) & ADC_SCANCTRL_AT_MASK) +#define ADC_SCANCTRL_AT_1CYCLE 0 +#define ADC_SCANCTRL_AT_2CYCLES 1 +#define ADC_SCANCTRL_AT_4CYCLES 2 +#define ADC_SCANCTRL_AT_8CYCLES 3 +#define ADC_SCANCTRL_AT_16CYCLES 4 +#define ADC_SCANCTRL_AT_32CYCLES 5 +#define ADC_SCANCTRL_AT_64CYCLES 6 +#define ADC_SCANCTRL_AT_128CYCLES 7 +#define ADC_SCANCTRL_AT_256CYCLES 8 + +#define ADC_SCANCTRL_REF_SHIFT (16) +#define ADC_SCANCTRL_REF_MASK (0xF << ADC_SCANCTRL_REF_SHIFT) +#define ADC_SCANCTRL_REF(v) \ + (((v) << ADC_SCANCTRL_REF_SHIFT) & ADC_SCANCTRL_REF_MASK) +#define ADC_SCANCTRL_REF_1V25 0 +#define ADC_SCANCTRL_REF_2V5 1 +#define ADC_SCANCTRL_REF_VDD 2 +#define ADC_SCANCTRL_REF_5VDIFF 3 +#define ADC_SCANCTRL_REF_EXTSCAN 4 +#define ADC_SCANCTRL_REF_2XEXTDIFF 5 +#define ADC_SCANCTRL_REF_2XVDD 6 + + +#define ADC_SCANCTRL_INPUTSEL_SHIFT (8) +#define ADC_SCANCTRL_INPUTSEL_MASK (0xFF << ADC_SCANCTRL_INPUTSEL_SHIFT) +#define ADC_SCANCTRL_INPUTSEL(v) \ + (((v) << ADC_SCANCTRL_INPUTSEL_SHIFT) & ADC_SCANCTRL_INPUTSEL_MASK) +/* DIFF=0 */ +#define ADC_SCANCTRL_INPUTSEL_CHx(x) ADC_SCANCTRL_INPUTSEL(1 << (x)) +#define ADC_SCANCTRL_INPUTSEL_CH0 ADC_SCANCTRL_INPUTSEL_CHx(0) +#define ADC_SCANCTRL_INPUTSEL_CH1 ADC_SCANCTRL_INPUTSEL_CHx(1) +#define ADC_SCANCTRL_INPUTSEL_CH2 ADC_SCANCTRL_INPUTSEL_CHx(2) +#define ADC_SCANCTRL_INPUTSEL_CH3 ADC_SCANCTRL_INPUTSEL_CHx(3) +#define ADC_SCANCTRL_INPUTSEL_CH4 ADC_SCANCTRL_INPUTSEL_CHx(4) +#define ADC_SCANCTRL_INPUTSEL_CH5 ADC_SCANCTRL_INPUTSEL_CHx(5) +#define ADC_SCANCTRL_INPUTSEL_CH6 ADC_SCANCTRL_INPUTSEL_CHx(6) +#define ADC_SCANCTRL_INPUTSEL_CH7 ADC_SCANCTRL_INPUTSEL_CHx(7) +/* DIFF=1 */ +#define ADC_SCANCTRL_INPUTSEL_CH0CH1 ADC_SCANCTRL_INPUTSEL(1 << 0) +#define ADC_SCANCTRL_INPUTSEL_CH2CH3 ADC_SCANCTRL_INPUTSEL(1 << 1) +#define ADC_SCANCTRL_INPUTSEL_CH4CH5 ADC_SCANCTRL_INPUTSEL(1 << 2) +#define ADC_SCANCTRL_INPUTSEL_CH6CH7 ADC_SCANCTRL_INPUTSEL(1 << 3) + +#define ADC_SCANCTRL_RES_SHIFT (4) +#define ADC_SCANCTRL_RES_MASK (0x3 << ADC_SCANCTRL_RES_SHIFT) +#define ADC_SCANCTRL_RES(v) \ + (((v) << ADC_SCANCTRL_RES_SHIFT) & ADC_SCANCTRL_RES_MASK) +#define ADC_SCANCTRL_RES_12BIT 0 +#define ADC_SCANCTRL_RES_8BIT 1 +#define ADC_SCANCTRL_RES_6BIT 2 +#define ADC_SCANCTRL_RES_OVS 3 + +#define ADC_SCANCTRL_ADJ (1 << 2) +#define ADC_SCANCTRL_DIFF (1 << 1) +#define ADC_SCANCTRL_REP (1 << 0) + +/* ADC_IEN */ +#define ADC_IEN_SCANOF (1 << 9) +#define ADC_IEN_SINGLEOF (1 << 8) +#define ADC_IEN_SCAN (1 << 1) +#define ADC_IEN_SINGLE (1 << 0) + +/* ADC_IF */ +#define ADC_IF_SCANOF (1 << 9) +#define ADC_IF_SINGLEOF (1 << 8) +#define ADC_IF_SCAN (1 << 1) +#define ADC_IF_SINGLE (1 << 0) + +/* ADC_IFS */ +#define ADC_IFS_SCANOF (1 << 9) +#define ADC_IFS_SINGLEOF (1 << 8) +#define ADC_IFS_SCAN (1 << 1) +#define ADC_IFS_SINGLE (1 << 0) + +/* ADC_IFC */ +#define ADC_IFC_SCANOF (1 << 9) +#define ADC_IFC_SINGLEOF (1 << 8) +#define ADC_IFC_SCAN (1 << 1) +#define ADC_IFC_SINGLE (1 << 0) + +/* ADC_CAL */ +#define ADC_CAL_SCANGAIN_SHIFT (24) +#define ADC_CAL_SCANGAIN_MASK (0x7F) + +#define ADC_CAL_SCANOFF_SHIFT (16) +#define ADC_CAL_SCANOFF_MASK (0x7F) + +#define ADC_CAL_SINGLEGAIN_SHIFT (8) +#define ADC_CAL_SINGLEGAIN_MASK (0x7F) + +#define ADC_CAL_SINGLEOFF_SHIFT (0) +#define ADC_CAL_SINGLEOFF_MASK (0x7F) + +/* ADC_BIASPROG */ +#define ADC_BIASPROG_COMPBIAS_SHIFT (8) +#define ADC_BIASPROG_COMPBIAS_MASK (0xF) + +#define ADC_BIASPROG_HALFBIAS (1 << 6) + +#define ADC_BIASPROG_BIASPROG_SHIFT (0) +#define ADC_BIASPROG_BIASPROG_MASK (0xF) + +/* ADC0 */ +#define ADC0 ADC0_BASE +#define ADC0_CTRL ADC_CTRL(ADC0) +#define ADC0_CMD ADC_CMD(ADC0) +#define ADC0_STATUS ADC_STATUS(ADC0) +#define ADC0_SINGLECTRL ADC_SINGLECTRL(ADC0) +#define ADC0_SCANCTRL ADC_SCANCTRL(ADC0) +#define ADC0_IEN ADC_IEN(ADC0) +#define ADC0_IF ADC_IF(ADC0) +#define ADC0_IFS ADC_IFS(ADC0) +#define ADC0_IFC ADC_IFC(ADC0) +#define ADC0_SINGLEDATA ADC_SINGLEDATA(ADC0) +#define ADC0_SCANDATA ADC_SCANDATA(ADC0) +#define ADC0_SINGLEDATAP ADC_SINGLEDATAP(ADC0) +#define ADC0_SCANDATAP ADC_SCANDATAP(ADC0) +#define ADC0_CAL ADC_CAL(ADC0) +#define ADC0_BIASPROG ADC_BIASPROG(ADC0) + +/** @defgroup adc_ch ADC Channel Number +@ingroup adc_defines + +@{*/ +#define ADC_CH0 0 +#define ADC_CH1 1 +#define ADC_CH2 2 +#define ADC_CH3 3 +#define ADC_CH4 4 +#define ADC_CH5 5 +#define ADC_CH6 6 +#define ADC_CH7 7 +#define ADC_CH_TEMP 8 +#define ADC_CH_VDDDIV3 9 +#define ADC_CH_VDD 10 +#define ADC_CH_VSS 11 +#define ADC_CH_VREFDIV2 12 +#define ADC_CH_DAC0OUT0 13 +#define ADC_CH_DAC0OUT1 14 + +#define ADC_CH_CH0CH1 0 +#define ADC_CH_CH2CH3 1 +#define ADC_CH_CH4CH5 2 +#define ADC_CH_CH6CH7 3 +#define ADC_CH_DIFF0 4 +/**@}*/ + +BEGIN_DECLS + +void adc_set_oversampling(uint32_t adc, uint32_t oversamp); +void adc_set_warm_up(uint32_t adc, uint8_t clocks); +void adc_set_clock_prescaler(uint32_t adc, uint8_t factor); +void adc_set_lowpass_filter(uint32_t adc, uint32_t lpfmode); + +void adc_enable_tailgating(uint32_t adc); +void adc_disable_tailgating(uint32_t adc); + +void adc_set_warm_up_mode(uint32_t adc, uint32_t warmupmode); + +void adc_single_start(uint32_t adc); +void adc_single_stop(uint32_t adc); + +void adc_scan_start(uint32_t adc); +void adc_scan_stop(uint32_t adc); + +/* TODO: ADC_STATUS */ + +void adc_set_single_prs_trigger(uint32_t adc, uint8_t prssel); +void adc_enable_single_prs_trigger(uint32_t adc); +void adc_disable_single_prs_trigger(uint32_t adc); +void adc_set_single_acquisition_cycle(uint32_t adc, uint32_t at); +void adc_set_single_reference(uint32_t adc, uint32_t ref); +void adc_set_single_channel(uint32_t adc, uint8_t ch); +void adc_set_single_resolution(uint32_t adc, uint32_t res); +void adc_set_single_left_aligned(uint32_t adc); +void adc_set_single_right_aligned(uint32_t adc); +void adc_set_single_single_ended(uint32_t adc); +void adc_set_single_differential(uint32_t adc); +void adc_enable_single_repeat_conv(uint32_t adc); +void adc_disable_single_repeat_conv(uint32_t adc); + +void adc_set_scan_prs_trigger(uint32_t adc, uint8_t prssel); +void adc_enable_scan_prs_trigger(uint32_t adc); +void adc_disable_scan_prs_trigger(uint32_t adc); +void adc_set_scan_acquisition_cycle(uint32_t adc, uint32_t at); +void adc_set_scan_reference(uint32_t adc, uint32_t ref); +void adc_set_scan_channel(uint32_t adc, uint8_t length, + uint8_t channel[]); +void adc_set_scan_resolution(uint32_t adc, uint32_t res); +void adc_set_scan_left_aligned(uint32_t adc); +void adc_set_scan_right_aligned(uint32_t adc); +void adc_set_scan_single_ended(uint32_t adc); +void adc_set_scan_differential(uint32_t adc); +void adc_enable_scan_repeat_conv(uint32_t adc); +void adc_disable_scan_repeat_conv(uint32_t adc); + +void adc_enable_single_result_overflow_interrupt(uint32_t adc); +void adc_disable_single_result_overflow_interrupt(uint32_t adc); +void adc_enable_single_conversion_complete_interrupt(uint32_t adc); +void adc_disable_single_conversion_complete_interrupt(uint32_t adc); +void adc_enable_scan_result_overflow_interrupt(uint32_t adc); +void adc_disable_scan_result_overflow_interrupt(uint32_t adc); +void adc_enable_scan_conversion_complete_interrupt(uint32_t adc); +void adc_disable_scan_conversion_complete_interrupt(uint32_t adc); + +bool adc_get_single_result_overflow_flag(uint32_t adc); +bool adc_get_single_conversion_complete_flag(uint32_t adc); +bool adc_get_scan_result_overflow_flag(uint32_t adc); +bool adc_get_scan_conversion_complete_flag(uint32_t adc); + +void adc_set_single_result_overflow_flag(uint32_t adc); +void adc_set_single_conversion_complete_flag(uint32_t adc); +void adc_set_scan_result_overflow_flag(uint32_t adc); +void adc_set_scan_conversion_complete_flag(uint32_t adc); + +void adc_clear_single_result_overflow_flag(uint32_t adc); +void adc_clear_single_conversion_complete_flag(uint32_t adc); +void adc_clear_scan_result_overflow_flag(uint32_t adc); +void adc_clear_scan_conversion_complete_flag(uint32_t adc); + +uint32_t adc_single_data(uint32_t adc); +uint32_t adc_scan_data(uint32_t adc); + +uint32_t adc_single_data_peak(uint32_t adc); +uint32_t adc_scan_data_peak(uint32_t adc); + +void adc_set_calibration_scan_gain(uint32_t adc, uint8_t scan_gain); +void adc_set_calibration_scan_offset(uint32_t adc, uint8_t scan_offset); + +void adc_set_calibration_single_gain(uint32_t adc, uint8_t single_gain); +void adc_set_calibration_single_offset(uint32_t adc, uint8_t single_offset); + +END_DECLS + +#endif + diff --git a/include/libopencm3/efm32/common/burtc_common.h b/include/libopencm3/efm32/common/burtc_common.h new file mode 100644 index 00000000..73f78e1c --- /dev/null +++ b/include/libopencm3/efm32/common/burtc_common.h @@ -0,0 +1,170 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2015 Kuldeep Singh Dhaka + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_EFM32_BURTC_H +#define LIBOPENCM3_EFM32_BURTC_H + +#include +#include + +#define BURTC_CTRL MMIO32(BURTC_BASE + 0x000) +#define BURTC_LPMODE MMIO32(BURTC_BASE + 0x004) +#define BURTC_CNT MMIO32(BURTC_BASE + 0x008) +#define BURTC_COMP0 MMIO32(BURTC_BASE + 0x00C) +#define BURTC_TIMESTAMP MMIO32(BURTC_BASE + 0x010) +#define BURTC_LFXOFDET MMIO32(BURTC_BASE + 0x014) +#define BURTC_STATUS MMIO32(BURTC_BASE + 0x018) +#define BURTC_CMD MMIO32(BURTC_BASE + 0x01C) +#define BURTC_POWERDOWN MMIO32(BURTC_BASE + 0x020) +#define BURTC_LOCK MMIO32(BURTC_BASE + 0x024) +#define BURTC_IF MMIO32(BURTC_BASE + 0x028) +#define BURTC_IFS MMIO32(BURTC_BASE + 0x02C) +#define BURTC_IFC MMIO32(BURTC_BASE + 0x030) +#define BURTC_IEN MMIO32(BURTC_BASE + 0x034) +#define BURTC_FREEZE MMIO32(BURTC_BASE + 0x038) +#define BURTC_SYNCBUSY MMIO32(BURTC_BASE + 0x03C) + +#define RETx_REG(x) MMIO32(BURTC_BASE + 0x100 + (4 * (x))) +/* [for ease] */ +#define BURTC_RETx(x) RETx_REG(x) + +/* BURTC_CTRL */ +#define BURTC_CTRL_BUMODETSEN (1 << 14) + +#define BURTC_CTRL_CLKSEL_SHIFT (8) +#define BURTC_CTRL_CLKSEL_MASK (0x3 << BURTC_CTRL_CLKSEL_SHIFT) +#define BURTC_CTRL_CLKSEL(v) \ + (((v) << BURTC_CTRL_CLKSEL_SHIFT) & BURTC_CTRL_CLKSEL_MASK) +#define BURTC_CTRL_CLKSEL_NONE 0 +#define BURTC_CTRL_CLKSEL_LFRCO 1 +#define BURTC_CTRL_CLKSEL_LFXO 2 +#define BURTC_CTRL_CLKSEL_ULFRCO 3 + +#define BURTC_CTRL_PRESC_SHIFT (12) +#define BURTC_CTRL_PRESC_MASK (0x7 << BURTC_CTRL_PRESC_SHIFT) +#define BURTC_CTRL_PRESC(v) \ + (((v) << BURTC_CTRL_PRESC_SHIFT) & BURTC_CTRL_PRESC_MASK) +#define BURTC_CTRL_PRESC_DIV1 0 +#define BURTC_CTRL_PRESC_DIV2 1 +#define BURTC_CTRL_PRESC_DIV4 2 +#define BURTC_CTRL_PRESC_DIV8 3 +#define BURTC_CTRL_PRESC_DIV16 4 +#define BURTC_CTRL_PRESC_DIV32 5 +#define BURTC_CTRL_PRESC_DIV64 6 +#define BURTC_CTRL_PRESC_DIV128 7 +#define BURTC_CTRL_PRESC_NODIV BURTC_CTRL_PRESC_DIV1 + +#define BURTC_CTRL_LPCOMPC_SHIFT (5) +#define BURTC_CTRL_LPCOMPC_MASK (0x7 << BURTC_CTRL_LPCOMPC_SHIFT) +#define BURTC_CTRL_LPCOMPC(v) \ + (((v) << BURTC_CTRL_LPCOMPC_SHIFT) & BURTC_CTRL_LPCOMPC_MASK) +#define BURTC_CTRL_LPCOMPC_IGNxLSB(x) BURTC_CTRL_LPCOMPC(x) +#define BURTC_CTRL_LPCOMPC_IGN0LSB 0 +#define BURTC_CTRL_LPCOMPC_IGN1LSB 1 +#define BURTC_CTRL_LPCOMPC_IGN2LSB 2 +#define BURTC_CTRL_LPCOMPC_IGN3LSB 3 +#define BURTC_CTRL_LPCOMPC_IGN4LSB 4 +#define BURTC_CTRL_LPCOMPC_IGN5LSB 5 +#define BURTC_CTRL_LPCOMPC_IGN6LSB 6 +#define BURTC_CTRL_LPCOMPC_IGN7LSB 7 + +#define BURTC_CTRL_COMP0TOP (1 << 4) +#define BURTC_CTRL_RSTEN (1 << 3) +#define BURTC_CTRL_DEBUGRUN (1 << 2) + +#define BURTC_CTRL_MODE_SHIFT (0) +#define BURTC_CTRL_MODE_MASK (0x3 << BURTC_CTRL_MODE_SHIFT) +#define BURTC_CTRL_MODE(v) \ + (((v) << BURTC_CTRL_MODE_SHIFT) & BURTC_CTRL_MODE_MASK) +#define BURTC_CTRL_MODE_DISABLE 0 +#define BURTC_CTRL_MODE_EM2EN 1 +#define BURTC_CTRL_MODE_EM3EN 2 +#define BURTC_CTRL_MODE_EM4EN 3 + +/* BURTC_LPMODE */ +#define BURTC_LPMODE_LPMODE_SHIFT (0) +#define BURTC_LPMODE_LPMODE_MASK (0x3 << BURTC_LPMODE_LPMODE_SHIFT) +#define BURTC_LPMODE_LPMODE(v) \ + (((v) << BURTC_LPMODE_LPMODE_SHIFT) & BURTC_LPMODE_LPMODE_MASK) +#define BURTC_LPMODE_LPMODE_DISABLE 0 +#define BURTC_LPMODE_LPMODE_ENABLE 1 +#define BURTC_LPMODE_LPMODE_BUEN 2 + +/* BURTC_LFXOFDET */ +#define BURTC_LFXOFDET_TOP_SHIFT (4) +#define BURTC_LFXOFDET_TOP_MASK (0xF << BURTC_LFXOFDET_TOP_SHIFT) +#define BURTC_LFXOFDET_TOP(v) \ + (((v) << BURTC_LFXOFDET_TOP_SHIFT) & BURTC_LFXOFDET_TOP_MASK) + +#define BURTC_LFXOFDET_OSC_SHIFT (0) +#define BURTC_LFXOFDET_OSC_MASK (0x3 << BURTC_LFXOFDET_OSC_SHIFT) +#define BURTC_LFXOFDET_OSC(v) \ + (((v) << BURTC_LFXOFDET_OSC_SHIFT) & BURTC_LFXOFDET_OSC_MASK) +#define BURTC_LFXOFDET_OSC_DISABLE 0 +#define BURTC_LFXOFDET_OSC_LFRCO 1 +#define BURTC_LFXOFDET_OSC_ULFRCO 2 + +/* BURTC_STATUS */ +#define BURTC_STATUS_RAMWERR (1 << 2) +#define BURTC_STATUS_BUMODETS (1 << 1) +#define BURTC_STATUS_LPMODEACT (1 << 0) + +/* BURTC_CMD */ +#define BURTC_CMD_CLRSTATUS (1 << 0) + +/* BURTC_POWERDOWN */ +#define BURTC_POWERDOWN_RAM (1 << 0) + +/* BURTC_LOCK */ +#define BURTC_LOCK_LOCKKEY_SHIFT (0) +#define BURTC_LOCK_LOCKKEY_MASK (0xFFFF << BURTC_LOCK_LOCKKEY_SHIFT) +#define BURTC_LOCK_LOCKKEY_UNLOCKED (0x0000 << BURTC_LOCK_LOCKKEY_SHIFT) +#define BURTC_LOCK_LOCKKEY_LOCKED (0x0001 << BURTC_LOCK_LOCKKEY_SHIFT) +#define BURTC_LOCK_LOCKKEY_LOCK (0x0000 << BURTC_LOCK_LOCKKEY_SHIFT) +#define BURTC_LOCK_LOCKKEY_UNLOCK (0xAEE8 << BURTC_LOCK_LOCKKEY_SHIFT) + +/* BURTC_IF */ +#define BURTC_IF_LFXOFAIL (1 << 2) +#define BURTC_IF_COMP0 (1 << 1) +#define BURTC_IF_OF (1 << 0) + +/* BURTC_IFS */ +#define BURTC_IFS_LFXOFAIL (1 << 2) +#define BURTC_IFS_COMP0 (1 << 1) +#define BURTC_IFS_OF (1 << 0) + +/* BURTC_IFC */ +#define BURTC_IFC_LFXOFAIL (1 << 2) +#define BURTC_IFC_COMP0 (1 << 1) +#define BURTC_IFC_OF (1 << 0) + +/* BURTC_IEN */ +#define BURTC_IEN_LFXOFAIL (1 << 2) +#define BURTC_IEN_COMP0 (1 << 1) +#define BURTC_IEN_OF (1 << 0) + +/* BURTC_FREEZE */ +#define BURTC_FREEZE_REGFREEZE (1 << 0) + +/* BURTC_SYNCBUSY */ +#define BURTC_SYNCBUSY_COMP0 (1 << 1) +#define BURTC_SYNCBUSY_LPMODE (1 << 0) + +#endif + diff --git a/include/libopencm3/efm32/common/cmu_common.h b/include/libopencm3/efm32/common/cmu_common.h new file mode 100644 index 00000000..caac95de --- /dev/null +++ b/include/libopencm3/efm32/common/cmu_common.h @@ -0,0 +1,705 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2015 Kuldeep Singh Dhaka + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_EFM32_CMU_H +#define LIBOPENCM3_EFM32_CMU_H + +#include +#include + +#define CMU_CTRL MMIO32(CMU_BASE + 0x000) +#define CMU_HFCORECLKDIV MMIO32(CMU_BASE + 0x004) +#define CMU_HFPERCLKDIV MMIO32(CMU_BASE + 0x008) +#define CMU_HFRCOCTRL MMIO32(CMU_BASE + 0x00C) +#define CMU_LFRCOCTRL MMIO32(CMU_BASE + 0x010) +#define CMU_AUXHFRCOCTRL MMIO32(CMU_BASE + 0x014) +#define CMU_CALCTRL MMIO32(CMU_BASE + 0x018) +#define CMU_CALCNT MMIO32(CMU_BASE + 0x01C) +#define CMU_OSCENCMD MMIO32(CMU_BASE + 0x020) +#define CMU_CMD MMIO32(CMU_BASE + 0x024) +#define CMU_LFCLKSEL MMIO32(CMU_BASE + 0x028) +#define CMU_STATUS MMIO32(CMU_BASE + 0x02C) +#define CMU_IF MMIO32(CMU_BASE + 0x030) +#define CMU_IFS MMIO32(CMU_BASE + 0x034) +#define CMU_IFC MMIO32(CMU_BASE + 0x038) +#define CMU_IEN MMIO32(CMU_BASE + 0x03C) +#define CMU_HFCORECLKEN0 MMIO32(CMU_BASE + 0x040) +#define CMU_HFPERCLKEN0 MMIO32(CMU_BASE + 0x044) +#define CMU_SYNCBUSY MMIO32(CMU_BASE + 0x050) +#define CMU_FREEZE MMIO32(CMU_BASE + 0x054) +#define CMU_LFACLKEN0 MMIO32(CMU_BASE + 0x058) +#define CMU_LFBCLKEN0 MMIO32(CMU_BASE + 0x060) +#define CMU_LFAPRESC0 MMIO32(CMU_BASE + 0x068) +#define CMU_LFBPRESC0 MMIO32(CMU_BASE + 0x070) +#define CMU_PCNTCTRL MMIO32(CMU_BASE + 0x078) +#define CMU_LCDCTRL MMIO32(CMU_BASE + 0x07C) +#define CMU_ROUTE MMIO32(CMU_BASE + 0x080) +#define CMU_LOCK MMIO32(CMU_BASE + 0x084) + +/* CMU_CTRL */ +#define CMU_CTRL_HFLE (1 << 30) +#define CMU_CTRL_DBGCLK (1 << 28) + + +#define CMU_CTRL_CLKOUTSEL1_SHIFT (23) +#define CMU_CTRL_CLKOUTSEL1_MASK (0x7 << CMU_CTRL_CLKOUTSEL1_SHIFT) +#define CMU_CTRL_CLKOUTSEL1(v) \ + (((v) << CMU_CTRL_CLKOUTSEL1_SHIFT) & CMU_CTRL_CLKOUTSEL1_MASK) +#define CMU_CTRL_CLKOUTSEL1_LFRCO 0 +#define CMU_CTRL_CLKOUTSEL1_LFXO 1 +#define CMU_CTRL_CLKOUTSEL1_HFCLK 2 +#define CMU_CTRL_CLKOUTSEL1_LFXOQ 3 +#define CMU_CTRL_CLKOUTSEL1_HFXOQ 4 +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ 5 +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ 6 +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 7 + +#define CMU_CTRL_CLKOUTSEL0_SHIFT (23) +#define CMU_CTRL_CLKOUTSEL0_MASK (0x7 << CMU_CTRL_CLKOUTSEL0_SHIFT) +#define CMU_CTRL_CLKOUTSEL0(v) \ + (((v) << CMU_CTRL_CLKOUTSEL0_SHIFT) & CMU_CTRL_CLKOUTSEL0_MASK) +#define CMU_CTRL_CLKOUTSEL0_HFRCO 0 +#define CMU_CTRL_CLKOUTSEL0_HFXO 1 +#define CMU_CTRL_CLKOUTSEL0_HFCLK2 2 +#define CMU_CTRL_CLKOUTSEL0_HFCLK4 3 +#define CMU_CTRL_CLKOUTSEL0_HFCLK8 4 +#define CMU_CTRL_CLKOUTSEL0_HFCLK16 5 +#define CMU_CTRL_CLKOUTSEL0_ULFRCO 6 +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO 7 + +#define CMU_CTRL_LFXOTIMEOUT_SHIFT (18) +#define CMU_CTRL_LFXOTIMEOUT_MASK (0x3 << CMU_CTRL_LFXOTIMEOUT_SHIFT) +#define CMU_CTRL_LFXOTIMEOUT(v) \ + (((v) << CMU_CTRL_LFXOTIMEOUT_SHIFT) & CMU_CTRL_LFXOTIMEOUT_MASK) +#define CMU_CTRL_LFXOTIMEOUT_8CYCLES 0 +#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES 1 +#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES 2 +#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES 3 + +#define CMU_CTRL_LFXOBUFCUR (1 << 17) + +#define CMU_CTRL_HFCLKDIV_SHIFT (14) +#define CMU_CTRL_HFCLKDIV_MASK (0x7 << CMU_CTRL_HFCLKDIV_SHIFT) +#define CMU_CTRL_HFCLKDIV(v) \ + (((v) << CMU_CTRL_HFCLKDIV_SHIFT) & CMU_CTRL_HFCLKDIV_MASK) +#define CMU_CTRL_HFCLKDIV_NODIV 0 +#define CMU_CTRL_HFCLKDIV_DIV2 1 +#define CMU_CTRL_HFCLKDIV_DIV3 2 +#define CMU_CTRL_HFCLKDIV_DIV4 3 +#define CMU_CTRL_HFCLKDIV_DIV5 4 +#define CMU_CTRL_HFCLKDIV_DIV6 5 +#define CMU_CTRL_HFCLKDIV_DIV7 6 +#define CMU_CTRL_HFCLKDIV_DIV8 7 + +#define CMU_CTRL_LFXOBOOST (1 << 13) + +#define CMU_CTRL_LFXOMODE_SHIFT (11) +#define CMU_CTRL_LFXOMODE_MASK (0x3 << CMU_CTRL_LFXOMODE_SHIFT) +#define CMU_CTRL_LFXOMODE(v) \ + (((v) << CMU_CTRL_LFXOMODE_SHIFT) & CMU_CTRL_LFXOMODE_MASK) +#define CMU_CTRL_LFXOMODE_XTAL 0 +#define CMU_CTRL_LFXOMODE_BUFEXTCLK 1 +#define CMU_CTRL_LFXOMODE_DIGEXTCLK 2 + +#define CMU_CTRL_HFXOTIMEOUT_SHIFT (9) +#define CMU_CTRL_HFXOTIMEOUT_MASK (0x3 << CMU_CTRL_HFXOTIMEOUT_SHIFT) +#define CMU_CTRL_HFXOTIMEOUT(v) \ + (((v) << CMU_CTRL_HFXOTIMEOUT_SHIFT) & CMU_CTRL_HFXOTIMEOUT_MASK) +#define CMU_CTRL_HFXOTIMEOUT_8CYCLES 0 +#define CMU_CTRL_HFXOTIMEOUT_256CYCLES 1 +#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES 2 +#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES 3 + +#define CMU_CTRL_HFXOGLITCHDETEN (1 << 7) + +#define CMU_CTRL_HFXOBUFCUR_SHIFT (5) +#define CMU_CTRL_HFXOBUFCUR_MASK (0x3 << CMU_CTRL_HFXOBUFCUR_SHIFT) +#define CMU_CTRL_HFXOBUFCUR(v) \ + (((v) << CMU_CTRL_HFXOBUFCUR_SHIFT) & CMU_CTRL_HFXOBUFCUR_MASK) +#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 1 +#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 3 + +#define CMU_CTRL_HFXOBOOST_SHIFT (2) +#define CMU_CTRL_HFXOBOOST_MASK (0x3 << CMU_CTRL_HFXOBOOST_SHIFT) +#define CMU_CTRL_HFXOBOOST(v) \ + (((v) << CMU_CTRL_HFXOBOOST_SHIFT) & CMU_CTRL_HFXOBOOST_MASK) +#define CMU_CTRL_HFXOBOOST_50PCENT 0 +#define CMU_CTRL_HFXOBOOST_70PCENT 1 +#define CMU_CTRL_HFXOBOOST_80PCENT 2 +#define CMU_CTRL_HFXOBOOST_100PCENT 3 + +#define CMU_CTRL_HFXOMODE_SHIFT (0) +#define CMU_CTRL_HFXOMODE_MASK (0x3 << CMU_CTRL_HFXOMODE_SHIFT) +#define CMU_CTRL_HFXOMODE(v) \ + (((v) << CMU_CTRL_HFXOMODE_SHIFT) & CMU_CTRL_HFXOMODE_MASK) +#define CMU_CTRL_HFXOMODE_XTAL 0 +#define CMU_CTRL_HFXOMODE_BUFEXTCLK 1 +#define CMU_CTRL_HFXOMODE_DIGEXTCLK 2 + +/* CMU_HFCORECLKDIV */ +#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (1 << 8) + +#define CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT (0) +#define CMU_HFCORECLKDIV_HFCORECLKDIV_MASK \ + (0xF << CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT) +#define CMU_HFCORECLKDIV_HFCORECLKDIV(v) \ + (((v) << CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT) & \ + CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) +#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK \ + CMU_HFCORECLKDIV_HFCORECLKDIV(0) +#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 \ + CMU_HFCORECLKDIV_HFCORECLKDIV(1) +#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 \ + CMU_HFCORECLKDIV_HFCORECLKDIV(2) +#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 \ + CMU_HFCORECLKDIV_HFCORECLKDIV(3) +#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 \ + CMU_HFCORECLKDIV_HFCORECLKDIV(4) +#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 \ + CMU_HFCORECLKDIV_HFCORECLKDIV(5) +#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 \ + CMU_HFCORECLKDIV_HFCORECLKDIV(6) +#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 \ + CMU_HFCORECLKDIV_HFCORECLKDIV(7) +#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 \ + CMU_HFCORECLKDIV_HFCORECLKDIV(8) +#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 \ + CMU_HFCORECLKDIV_HFCORECLKDIV(9) + +#define CMU_HFCORECLKDIV_HFCORECLKDIV_NODIV \ + CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK +#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV2 \ + CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 +#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV4 \ + CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 +#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV8 \ + CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 +#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV16 \ + CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 +#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV32 \ + CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 +#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV64 \ + CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 +#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV128 \ + CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 +#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV256 \ + CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 +#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV512 \ + CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 + +/* CMU_HFPERCLKDIV */ +#define CMU_HFPERCLKDIV_HFPERCLKEN (1 << 8) + +#define CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT (0) +#define CMU_HFPERCLKDIV_HFPERCLKDIV_MASK \ + (0xF << CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT) +#define CMU_HFPERCLKDIV_HFPERCLKDIV(v) \ + (((v) << CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT) & \ + CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) +#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK CMU_HFPERCLKDIV_HFPERCLKDIV(0) +#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK2 CMU_HFPERCLKDIV_HFPERCLKDIV(1) +#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK4 CMU_HFPERCLKDIV_HFPERCLKDIV(2) +#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK8 CMU_HFPERCLKDIV_HFPERCLKDIV(3) +#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK16 CMU_HFPERCLKDIV_HFPERCLKDIV(4) +#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK32 CMU_HFPERCLKDIV_HFPERCLKDIV(5) +#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK64 CMU_HFPERCLKDIV_HFPERCLKDIV(6) +#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK128 CMU_HFPERCLKDIV_HFPERCLKDIV(7) +#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK256 CMU_HFPERCLKDIV_HFPERCLKDIV(8) +#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK512 CMU_HFPERCLKDIV_HFPERCLKDIV(9) + +/* CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK* to CMU_HFPERCLKDIV_HFPERCLKHFCLK_DIV* */ +#define CMU_HFPERCLKDIV_HFPERCLKDIV_NODIV \ + CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK +#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV2 \ + CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 +#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV4 \ + CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 +#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV8 \ + CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 +#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV16 \ + CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 +#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV32 \ + CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 +#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV64 \ + CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 +#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV128 \ + CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 +#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV256 \ + CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 +#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV512 \ + CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 + +/* CMU_HFRCOCTRL */ +#define CMU_HFRCOCTRL_SUDELAY_SHIFT (12) +#define CMU_HFRCOCTRL_SUDELAY_MASK (0x1F << CMU_HFRCOCTRL_SUDELAY_SHIFT) +#define CMU_HFRCOCTRL_SUDELAY(v) \ + ((((v) << CMU_HFRCOCTRL_SUDELAY_SHIFT) & CMU_HFRCOCTRL_SUDELAY_MASK)) + +#define CMU_HFRCOCTRL_BAND_SHIFT (8) +#define CMU_HFRCOCTRL_BAND_MASK (0x7 << CMU_HFRCOCTRL_BAND_SHIFT) +#define CMU_HFRCOCTRL_BAND(v) \ + (((v) << CMU_HFRCOCTRL_BAND_SHIFT) & CMU_HFRCOCTRL_BAND_MASK) +#define CMU_HFRCOCTRL_BAND_1MHZ 0 +#define CMU_HFRCOCTRL_BAND_7MHZ 1 +#define CMU_HFRCOCTRL_BAND_11MHZ 2 +#define CMU_HFRCOCTRL_BAND_14MHZ 3 +#define CMU_HFRCOCTRL_BAND_21MHZ 4 +#define CMU_HFRCOCTRL_BAND_28MHZ 5 + +#define CMU_HFRCOCTRL_TUNING_SHIFT (0) +#define CMU_HFRCOCTRL_TUNING_MASK (0xFF << CMU_HFRCOCTRL_TUNING_SHIFT) +#define CMU_HFRCOCTRL_TUNING(v) \ + (((v) << CMU_HFRCOCTRL_TUNING_SHIFT) & CMU_HFRCOCTRL_TUNING_MASK) + +/* CMU_LFRCOCTRL */ +#define CMU_LFRCOCTRL_TUNING_SHIFT (0) +#define CMU_LFRCOCTRL_TUNING_MASK (0xFF << CMU_LFRCOCTRL_TUNING_SHIFT) +#define CMU_LFRCOCTRL_TUNING(v) \ + (((v) << CMU_LFRCOCTRL_TUNING_SHIFT) & CMU_LFRCOCTRL_TUNING_MASK) + +/* CMU_AUXHFRCOCTRL */ +#define CMU_AUXHFRCOCTRL_BAND_SHIFT (8) +#define CMU_AUXHFRCOCTRL_BAND_MASK (0x7 << CMU_AUXHFRCOCTRL_BAND_SHIFT) +#define CMU_AUXHFRCOCTRL_BAND(v) \ + (((v) << CMU_AUXHFRCOCTRL_BAND_SHIFT) & CMU_AUXHFRCOCTRL_BAND_MASK) +#define CMU_AUXHFRCOCTRL_BAND_1MHZ 0 +#define CMU_AUXHFRCOCTRL_BAND_7MHZ 1 +#define CMU_AUXHFRCOCTRL_BAND_11MHZ 2 +#define CMU_AUXHFRCOCTRL_BAND_14MHZ 3 +#define CMU_AUXHFRCOCTRL_BAND_28MHZ 4 +#define CMU_AUXHFRCOCTRL_BAND_21MHZ 5 + +#define CMU_AUXHFRCOCTRL_TUNING_SHIFT (0) +#define CMU_AUXHFRCOCTRL_TUNING_MASK (0xFF << CMU_AUXHFRCOCTRL_TUNING_SHIFT) +#define CMU_AUXHFRCOCTRL_TUNING(v) \ + (((v) << CMU_AUXHFRCOCTRL_TUNING_SHIFT) & CMU_AUXHFRCOCTRL_TUNING_MASK) + +/* CMU_CALCTRL */ +#define CMU_CALCTRL_CONT (1 << 6) + +#define CMU_CALCTRL_DOWNSEL_SHIFT (3) +#define CMU_CALCTRL_DOWNSEL_MASK (0x7 << CMU_CALCTRL_DOWNSEL_SHIFT) +#define CMU_CALCTRL_DOWNSEL(v) \ + (((v) << CMU_CALCTRL_DOWNSEL_SHIFT) & CMU_CALCTRL_DOWNSEL_MASK) +#define CMU_CALCTRL_DOWNSEL_HFCLK 0 +#define CMU_CALCTRL_DOWNSEL_HFXO 1 +#define CMU_CALCTRL_DOWNSEL_LFXO 2 +#define CMU_CALCTRL_DOWNSEL_HFRCO 3 +#define CMU_CALCTRL_DOWNSEL_LFRCO 4 +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO 5 + +#define CMU_CALCTRL_UPSEL_SHIFT (3) +#define CMU_CALCTRL_UPSEL_MASK (0x7 << CMU_CALCTRL_UPSEL_SHIFT) +#define CMU_CALCTRL_UPSEL(v) \ + (((v) << CMU_CALCTRL_UPSEL_SHIFT) & CMU_CALCTRL_UPSEL_MASK) +#define CMU_CALCTRL_UPSEL_HFXO 0 +#define CMU_CALCTRL_UPSEL_LFXO 1 +#define CMU_CALCTRL_UPSEL_HFRCO 2 +#define CMU_CALCTRL_UPSEL_LFRCO 3 +#define CMU_CALCTRL_UPSEL_AUXHFRCO 4 + +/* CMU_CALCNT */ +#define CMU_CALCNT_CALCNT_SHIFT (0) +#define CMU_CALCNT_CALCNT_MASK (0xFFFFF << CMU_CALCNT_CALCNT_SHIFT) +#define CMU_CALCNT_CALCNT(v) \ + (((v) << CMU_CALCNT_CALCNT_SHIFT) & CMU_CALCNT_CALCNT_MASK) + +/* CMU_OSCENCMD */ +#define CMU_OSCENCMD_LFXODIS (1 << 9) +#define CMU_OSCENCMD_LFXOEN (1 << 8) +#define CMU_OSCENCMD_LFRCODIS (1 << 7) +#define CMU_OSCENCMD_LFRCOEN (1 << 6) +#define CMU_OSCENCMD_AUXHFRCODIS (1 << 5) +#define CMU_OSCENCMD_AUXHFRCOEN (1 << 4) +#define CMU_OSCENCMD_HFXODIS (1 << 3) +#define CMU_OSCENCMD_HFXOEN (1 << 2) +#define CMU_OSCENCMD_HFRCODIS (1 << 1) +#define CMU_OSCENCMD_HFRCOEN (1 << 0) + +/* CMU_CMD */ +#define CMU_CMD_USBCCLKSEL_SHIFT (5) +#define CMU_CMD_USBCCLKSEL_MASK (0x3 << CMU_CMD_USBCCLKSEL_SHIFT) +#define CMU_CMD_USBCCLKSEL(v) \ + (((v) << CMU_CMD_USBCCLKSEL_SHIFT) & CMU_CMD_USBCCLKSEL_MASK) +#define CMU_CMD_USBCCLKSEL_HFCLKNODIV 1 +#define CMU_CMD_USBCCLKSEL_LFXO 2 +#define CMU_CMD_USBCCLKSEL_LFRCO 3 + +#define CMU_CMD_CALSTOP (1 << 4) +#define CMU_CMD_CALSTART (1 << 3) + +#define CMU_CMD_HFCLKSEL_SHIFT (0) +#define CMU_CMD_HFCLKSEL_MASK (0x7 << CMU_CMD_HFCLKSEL_SHIFT) +#define CMU_CMD_HFCLKSEL(v) \ + (((v) << CMU_CMD_HFCLKSEL_SHIFT) & CMU_CMD_HFCLKSEL_MASK) +#define CMU_CMD_HFCLKSEL_HFRCO 1 +#define CMU_CMD_HFCLKSEL_HFXO 2 +#define CMU_CMD_HFCLKSEL_LFRCO 3 +#define CMU_CMD_HFCLKSEL_LFXO 4 + +/* CMU_LFCLKSEL */ +#define CMU_LFCLKSEL_LFBE (1 << 20) +#define CMU_LFCLKSEL_LFAE (1 << 16) + +#define CMU_LFCLKSEL_LFB_SHIFT (2) +#define CMU_LFCLKSEL_LFB_MASK (0x3 << CMU_LFCLKSEL_LFB_MASK) +#define CMU_LFCLKSEL_LFB(v) \ + (((v) << CMU_LFCLKSEL_LFB_MASK) & CMU_LFCLKSEL_LFB_MASK) + +#define CMU_LFCLKSEL_LFA_SHIFT (0) +#define CMU_LFCLKSEL_LFA_MASK (0x3 << CMU_LFCLKSEL_LFA_MASK) +#define CMU_LFCLKSEL_LFA(v) \ + (((v) << CMU_LFCLKSEL_LFA_MASK) & CMU_LFCLKSEL_LFA_MASK) + +/* CMU_STATUS */ +#define CMU_STATUS_USBCLFRCOSEL (1 << 17) +#define CMU_STATUS_USBCLFXOSEL (1 << 16) +#define CMU_STATUS_USBCHFCLKSEL (1 << 15) +#define CMU_STATUS_CALBSY (1 << 14) +#define CMU_STATUS_LFXOSEL (1 << 13) +#define CMU_STATUS_LFRCOSEL (1 << 12) +#define CMU_STATUS_HFXOSEL (1 << 11) +#define CMU_STATUS_HFRCOSEL (1 << 10) +#define CMU_STATUS_LFXORDY (1 << 9) +#define CMU_STATUS_LFXOENS (1 << 8) +#define CMU_STATUS_LFRCORDY (1 << 7) +#define CMU_STATUS_LFRCOENS (1 << 6) +#define CMU_STATUS_AUXHFRCORDY (1 << 5) +#define CMU_STATUS_AUXHFRCOENS (1 << 4) +#define CMU_STATUS_HFXORDY (1 << 3) +#define CMU_STATUS_HFXOENS (1 << 2) +#define CMU_STATUS_HFRCORDY (1 << 1) +#define CMU_STATUS_HFRCOENS (1 << 0) + +/* CMU_IF */ +#define CMU_IF_USBCHFCLKSEL (1 << 7) +#define CMU_IF_CALOF (1 << 6) +#define CMU_IF_CALRDY (1 << 5) +#define CMU_IF_AUXHFRCORDY (1 << 4) +#define CMU_IF_LFXORDY (1 << 3) +#define CMU_IF_LFRCORDY (1 << 2) +#define CMU_IF_HFXORDY (1 << 1) +#define CMU_IF_HFRCORDY (1 << 0) + +/* CMU_IFS */ +#define CMU_IFS_USBCHFCLKSEL (1 << 7) +#define CMU_IFS_CALOF (1 << 6) +#define CMU_IFS_CALRDY (1 << 5) +#define CMU_IFS_AUXHFRCORDY (1 << 4) +#define CMU_IFS_LFXORDY (1 << 3) +#define CMU_IFS_LFRCORDY (1 << 2) +#define CMU_IFS_HFXORDY (1 << 1) +#define CMU_IFS_HFRCORDY (1 << 0) + +/* CMU_IFC */ +#define CMU_IFC_USBCHFCLKSEL (1 << 7) +#define CMU_IFC_CALOF (1 << 6) +#define CMU_IFC_CALRDY (1 << 5) +#define CMU_IFC_AUXHFRCORDY (1 << 4) +#define CMU_IFC_LFXORDY (1 << 3) +#define CMU_IFC_LFRCORDY (1 << 2) +#define CMU_IFC_HFXORDY (1 << 1) +#define CMU_IFC_HFRCORDY (1 << 0) + +/* CMU_IEN */ +#define CMU_IEN_USBCHFCLKSEL (1 << 7) +#define CMU_IEN_CALOF (1 << 6) +#define CMU_IEN_CALRDY (1 << 5) +#define CMU_IEN_AUXHFRCORDY (1 << 4) +#define CMU_IEN_LFXORDY (1 << 3) +#define CMU_IEN_LFRCORDY (1 << 2) +#define CMU_IEN_HFXORDY (1 << 1) +#define CMU_IEN_HFRCORDY (1 << 0) + +/* CMU_HFCORECLKEN0 */ +#define CMU_HFCORECLKEN0_EBI (1 << 5) +#define CMU_HFCORECLKEN0_LE (1 << 4) +#define CMU_HFCORECLKEN0_USB (1 << 3) +#define CMU_HFCORECLKEN0_USBC (1 << 2) +#define CMU_HFCORECLKEN0_AES (1 << 1) +#define CMU_HFCORECLKEN0_DMA (1 << 0) + +/* CMU_HFPERCLKEN0 */ +#define CMU_HFPERCLKEN0_DAC0 (1 << 17) +#define CMU_HFPERCLKEN0_ADC0 (1 << 16) +#define CMU_HFPERCLKEN0_PRS (1 << 15) +#define CMU_HFPERCLKEN0_VCMP (1 << 14) +#define CMU_HFPERCLKEN0_GPIO (1 << 13) +#define CMU_HFPERCLKEN0_I2C1 (1 << 12) +#define CMU_HFPERCLKEN0_I2C0 (1 << 11) +#define CMU_HFPERCLKEN0_ACMP1 (1 << 10) +#define CMU_HFPERCLKEN0_ACMP0 (1 << 9) +#define CMU_HFPERCLKEN0_TIMER3 (1 << 8) +#define CMU_HFPERCLKEN0_TIMER2 (1 << 7) +#define CMU_HFPERCLKEN0_TIMER1 (1 << 6) +#define CMU_HFPERCLKEN0_TIMER0 (1 << 5) +#define CMU_HFPERCLKEN0_UART1 (1 << 4) +#define CMU_HFPERCLKEN0_UART0 (1 << 3) +#define CMU_HFPERCLKEN0_USART2 (1 << 2) +#define CMU_HFPERCLKEN0_USART1 (1 << 1) +#define CMU_HFPERCLKEN0_USART0 (1 << 0) + +/* CMU_SYNCBUSY */ +#define CMU_SYNCBUSY_LFBPRESC0 (1 << 6) +#define CMU_SYNCBUSY_LFBCLKEN0 (1 << 4) +#define CMU_SYNCBUSY_LFAPRESC0 (1 << 2) +#define CMU_SYNCBUSY_LFACLKEN0 (1 << 0) + +/* CMU_FREEZE */ +#define CMU_FREEZE_REGFREEZE (1 << 0) + +/* CMU_LFACLKEN0 */ +#define CMU_LFACLKEN0_LCD (1 << 3) +#define CMU_LFACLKEN0_LETIMER0 (1 << 2) +#define CMU_LFACLKEN0_RTC (1 << 1) +#define CMU_LFACLKEN0_LESENSE (1 << 0) + +/* CMU_LFBCLKEN0 */ +#define CMU_LFBCLKEN0_LEUART1 (1 << 1) +#define CMU_LFBCLKEN0_LEUART0 (1 << 0) + +/* CMU_LFAPRESC0 */ +#define CMU_LFAPRESC0_LCD_SHIFT (12) +#define CMU_LFAPRESC0_LCD_MASK (0x3 << CMU_LFAPRESC0_LCD_SHIFT) +#define CMU_LFAPRESC0_LCD(v) \ + (((v) << CMU_LFAPRESC0_LCD_SHIFT) & CMU_LFAPRESC0_LCD_MASK) +#define CMU_LFAPRESC0_LCD_DIV16 0 +#define CMU_LFAPRESC0_LCD_DIV32 1 +#define CMU_LFAPRESC0_LCD_DIV64 2 +#define CMU_LFAPRESC0_LCD_DIV128 3 + +#define CMU_LFAPRESC0_LETIMER0_SHIFT (8) +#define CMU_LFAPRESC0_LETIMER0_MASK (0xF << CMU_LFAPRESC0_LETIMER0_SHIFT) +#define CMU_LFAPRESC0_LETIMER0(v) \ + (((v) << CMU_LFAPRESC0_LETIMER0_SHIFT) & CMU_LFAPRESC0_LETIMER0_MASK) +#define CMU_LFAPRESC0_LETIMER0_DIV1 0 +#define CMU_LFAPRESC0_LETIMER0_DIV2 1 +#define CMU_LFAPRESC0_LETIMER0_DIV4 2 +#define CMU_LFAPRESC0_LETIMER0_DIV8 3 +#define CMU_LFAPRESC0_LETIMER0_DIV16 4 +#define CMU_LFAPRESC0_LETIMER0_DIV32 5 +#define CMU_LFAPRESC0_LETIMER0_DIV64 6 +#define CMU_LFAPRESC0_LETIMER0_DIV128 7 +#define CMU_LFAPRESC0_LETIMER0_DIV256 8 +#define CMU_LFAPRESC0_LETIMER0_DIV512 9 +#define CMU_LFAPRESC0_LETIMER0_DIV1024 10 +#define CMU_LFAPRESC0_LETIMER0_DIV2048 11 +#define CMU_LFAPRESC0_LETIMER0_DIV4096 12 +#define CMU_LFAPRESC0_LETIMER0_DIV8192 13 +#define CMU_LFAPRESC0_LETIMER0_DIV16384 14 +#define CMU_LFAPRESC0_LETIMER0_DIV32768 15 +#define CMU_LFAPRESC0_LETIMER0_NODIV CMU_LFAPRESC0_LETIMER0_DIV1 + +#define CMU_LFAPRESC0_RTC_SHIFT (4) +#define CMU_LFAPRESC0_RTC_MASK (0xF << CMU_LFAPRESC0_RTC_SHIFT) +#define CMU_LFAPRESC0_RTC(v) \ + (((v) << CMU_LFAPRESC0_RTC_SHIFT) & CMU_LFAPRESC0_RTC_MASK) +#define CMU_LFAPRESC0_RTC_DIV1 0 +#define CMU_LFAPRESC0_RTC_DIV2 1 +#define CMU_LFAPRESC0_RTC_DIV4 2 +#define CMU_LFAPRESC0_RTC_DIV8 3 +#define CMU_LFAPRESC0_RTC_DIV16 4 +#define CMU_LFAPRESC0_RTC_DIV32 5 +#define CMU_LFAPRESC0_RTC_DIV64 6 +#define CMU_LFAPRESC0_RTC_DIV128 7 +#define CMU_LFAPRESC0_RTC_DIV256 8 +#define CMU_LFAPRESC0_RTC_DIV512 9 +#define CMU_LFAPRESC0_RTC_DIV1024 10 +#define CMU_LFAPRESC0_RTC_DIV2048 11 +#define CMU_LFAPRESC0_RTC_DIV4096 12 +#define CMU_LFAPRESC0_RTC_DIV8192 13 +#define CMU_LFAPRESC0_RTC_DIV16384 14 +#define CMU_LFAPRESC0_RTC_DIV32768 15 +#define CMU_LFAPRESC0_RTC_NODIV CMU_LFAPRESC0_RTC_DIV1 + +#define CMU_LFAPRESC0_LESENSE_SHIFT (12) +#define CMU_LFAPRESC0_LESENSE_MASK (0x3 << CMU_LFAPRESC0_LESENSE_SHIFT) +#define CMU_LFAPRESC0_LESENSE(v) \ + (((v) << CMU_LFAPRESC0_LESENSE_SHIFT) & CMU_LFAPRESC0_LESENSE_MASK) +#define CMU_LFAPRESC0_LESENSE_DIV1 0 +#define CMU_LFAPRESC0_LESENSE_DIV2 1 +#define CMU_LFAPRESC0_LESENSE_DIV4 2 +#define CMU_LFAPRESC0_LESENSE_DIV8 3 +#define CMU_LFAPRESC0_LESENSE_NODIV CMU_LFAPRESC0_LESENSE_DIV1 + +/* CMU_LFBPRESC0 */ +#define CMU_LFBPRESC0_LEUART1_SHIFT (4) +#define CMU_LFBPRESC0_LEUART1_MASK (0x3 << CMU_LFBPRESC0_LEUART1_SHIFT) +#define CMU_LFBPRESC0_LEUART1(v) \ + (((v) << CMU_LFBPRESC0_LEUART1_SHIFT) & CMU_LFBPRESC0_LEUART1_MASK) +#define CMU_LFBPRESC0_LEUART1_DIV1 0 +#define CMU_LFBPRESC0_LEUART1_DIV2 1 +#define CMU_LFBPRESC0_LEUART1_DIV4 2 +#define CMU_LFBPRESC0_LEUART1_DIV8 3 +#define CMU_LFBPRESC0_LEUART1_NODIV CMU_LFBPRESC0_LEUART1_DIV1 + +#define CMU_LFBPRESC0_LEUART0_SHIFT (0) +#define CMU_LFBPRESC0_LEUART0_MASK (0x3 << CMU_LFBPRESC0_LEUART0_SHIFT) +#define CMU_LFBPRESC0_LEUART0(v) \ + (((v) << CMU_LFBPRESC0_LEUART0_SHIFT) & CMU_LFBPRESC0_LEUART0_MASK) +#define CMU_LFBPRESC0_LEUART0_DIV1 0 +#define CMU_LFBPRESC0_LEUART0_DIV2 1 +#define CMU_LFBPRESC0_LEUART0_DIV4 2 +#define CMU_LFBPRESC0_LEUART0_DIV8 3 +#define CMU_LFBPRESC0_LEUART0_NODIV CMU_LFBPRESC0_LEUART0_DIV1 + +/* CMU_PCNTCTRL */ +#define CMU_PCNTCTRL_PCNT2CLKSE (1 << 5) +#define CMU_PCNTCTRL_PCNT2CLKEN (1 << 4) +#define CMU_PCNTCTRL_PCNT1CLKSEL (1 << 3) +#define CMU_PCNTCTRL_PCNT1CLKEN (1 << 2) +#define CMU_PCNTCTRL_PCNT0CLKSEL (1 << 1) +#define CMU_PCNTCTRL_PCNT0CLKEN (1 << 0) + +/* CMU_LCDCTRL */ +#define CMU_LCDCTRL_VBFDIV_SHIFT (4) +#define CMU_LCDCTRL_VBFDIV_MASK (0xF << CMU_LCDCTRL_VBFDIV_SHIFT) +#define CMU_LCDCTRL_VBFDIV(v) \ + (((v) << CMU_LCDCTRL_VBFDIV_SHIFT) & CMU_LCDCTRL_VBFDIV_MASK) +#define CMU_LCDCTRL_VBFDIV_DIV1 0 +#define CMU_LCDCTRL_VBFDIV_DIV2 1 +#define CMU_LCDCTRL_VBFDIV_DIV4 2 +#define CMU_LCDCTRL_VBFDIV_DIV8 3 +#define CMU_LCDCTRL_VBFDIV_DIV16 4 +#define CMU_LCDCTRL_VBFDIV_DIV32 5 +#define CMU_LCDCTRL_VBFDIV_DIV64 6 +#define CMU_LCDCTRL_VBFDIV_DIV128 7 +#define CMU_LCDCTRL_VBFDIV_NODIV CMU_LCDCTRL_VBFDIV_DIV1 + +#define CMU_LCDCTRL_VBOOSTEN (1 << 3) + +#define CMU_LCDCTRL_FDIV_SHIFT (0) +#define CMU_LCDCTRL_FDIV_MASK (0x3 << CMU_LCDCTRL_FDIV_SHIFT) +#define CMU_LCDCTRL_FDIV(v) \ + (((v) & CMU_LCDCTRL_FDIV_MASK) << CMU_LCDCTRL_FDIV_SHIFT) + +/* CMU_ROUTE */ +#define CMU_ROUTE_LOCATION_SHIFT (2) +#define CMU_ROUTE_LOCATION_MASK (0x7 << CMU_ROUTE_LOCATION_SHIFT) +#define CMU_ROUTE_LOCATION_LOCx(i) \ + (((i) << CMU_ROUTE_LOCATION_SHIFT) & CMU_ROUTE_LOCATION_MASK) +#define CMU_ROUTE_LOCATION_LOC0 0 +#define CMU_ROUTE_LOCATION_LOC1 1 +#define CMU_ROUTE_LOCATION_LOC2 2 + +#define CMU_ROUTE_CLKOUT1PEN (1 << 1) +#define CMU_ROUTE_CLKOUT0PEN (1 << 0) + +/* CMU_LOCK */ +#define CMU_LOCK_LOCKKEY_SHIFT (0) +#define CMU_LOCK_LOCKKEY_MASK (0xFFFF << CMU_LOCK_LOCKKEY_SHIFT) +#define CMU_LOCK_LOCKKEY_UNLOCKED (0x0000 << CMU_LOCK_LOCKKEY_SHIFT) +#define CMU_LOCK_LOCKKEY_LOCKED (0x0001 << CMU_LOCK_LOCKKEY_SHIFT) +#define CMU_LOCK_LOCKKEY_LOCK (0x0000 << CMU_LOCK_LOCKKEY_SHIFT) +#define CMU_LOCK_LOCKKEY_UNLOCK (0x580E << CMU_LOCK_LOCKKEY_SHIFT) + +#define _REG_BIT(base, bit) (((base) << 5) + (bit)) + +enum cmu_periph_clken { + /* CMU_PCNTCTRL */ + CMU_PCNT2 = _REG_BIT(0x078, 4), + CMU_PCNT1 = _REG_BIT(0x078, 2), + CMU_PCNT0 = _REG_BIT(0x078, 0), + + /* CMU_LFBCLKEN0 */ + CMU_LEUART1 = _REG_BIT(0x060, 1), + CMU_LEUART0 = _REG_BIT(0x060, 0), + + /* CMU_LFACLKEN0 */ + CMU_LCD = _REG_BIT(0x058, 3), + CMU_LETIMER0 = _REG_BIT(0x058, 2), + CMU_RTC = _REG_BIT(0x058, 1), + CMU_LESENSE = _REG_BIT(0x058, 0), + + /* CMU_HFPERCLKEN0 */ + CMU_DAC0 = _REG_BIT(0x044, 17), + CMU_ADC0 = _REG_BIT(0x044, 16), + CMU_PRS = _REG_BIT(0x044, 15), + CMU_VCMP = _REG_BIT(0x044, 14), + CMU_GPIO = _REG_BIT(0x044, 13), + CMU_I2C1 = _REG_BIT(0x044, 12), + CMU_I2C0 = _REG_BIT(0x044, 11), + CMU_ACMP1 = _REG_BIT(0x044, 10), + CMU_ACMP0 = _REG_BIT(0x044, 9), + CMU_TIMER3 = _REG_BIT(0x044, 8), + CMU_TIMER2 = _REG_BIT(0x044, 7), + CMU_TIMER1 = _REG_BIT(0x044, 6), + CMU_TIMER0 = _REG_BIT(0x044, 5), + CMU_UART1 = _REG_BIT(0x044, 4), + CMU_UART0 = _REG_BIT(0x044, 3), + CMU_USART2 = _REG_BIT(0x044, 2), + CMU_USART1 = _REG_BIT(0x044, 1), + CMU_USART0 = _REG_BIT(0x044, 0), + + /* CMU_HFCORECLKEN0 */ + CMU_EBI = _REG_BIT(0x040, 5), + CMU_LE = _REG_BIT(0x040, 4), + CMU_USB = _REG_BIT(0x040, 3), + CMU_USBC = _REG_BIT(0x040, 2), + CMU_AES = _REG_BIT(0x040, 1), + CMU_DMA = _REG_BIT(0x040, 0) +}; + +enum cmu_osc { + HFRCO, /**< Internal, 1 - 28Mhz */ + LFRCO, /**< Internal, 32.768kHz */ + ULFRCO, /**< Internal, 1Khz */ + HFXO, /**< External, 4-48Mhz */ + LFXO, /**< External, 32.768kHz */ + AUXHFRCO, /**< Internal, 1-28Mhz */ +}; + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void cmu_enable_lock(void); +void cmu_disable_lock(void); +bool cmu_get_lock_flag(void); + +void cmu_periph_clock_enable(enum cmu_periph_clken periph); +void cmu_periph_clock_disable(enum cmu_periph_clken periph); + +/* TODO: CMU_CTRL, CMU_HFCORECLKDIV, CMU_HFPERCLKDIV, CMU_HFRCOCTRL, + * CMU_LFRCOCTRL, CMU_AUXHFRCOCTRL, CMU_CALCTRL, CMU_CALCNT */ + +void cmu_osc_on(enum cmu_osc osc); +void cmu_osc_off(enum cmu_osc osc); + +/* TODO: CMU_CMD, CMU_LFCLKSEL */ + +/* TODO: portions of CMU_STATUS */ +bool cmu_osc_ready_flag(enum cmu_osc osc); +void cmu_wait_for_osc_ready(enum cmu_osc osc); +void cmu_set_hfclk_source(enum cmu_osc osc); +void cmu_set_usbclk_source(enum cmu_osc osc); +enum cmu_osc cmu_get_hfclk_source(void); + +/* TODO: CMU_IF, CMU_IFS, CMU_IFC, CMU_IEN */ + +/* TODO: CMU_SYNCBUSY, CMU_FREEZE, CMU_LFACLKEN0 */ + +/* TODO: CMU_LFAPRESC0, CMU_LFBPRESC0, CMU_PCNTCTRL, CMU_LCDCTRL, CMU_ROUTE */ + +void cmu_clock_setup_in_hfxo_out_48mhz(void); + +END_DECLS + +#endif + diff --git a/include/libopencm3/efm32/common/dac_common.h b/include/libopencm3/efm32/common/dac_common.h new file mode 100644 index 00000000..ff07d4fa --- /dev/null +++ b/include/libopencm3/efm32/common/dac_common.h @@ -0,0 +1,512 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2015 Kuldeep Singh Dhaka + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_EFM32_DAC_H +#define LIBOPENCM3_EFM32_DAC_H + +#include +#include +#include + +#define DAC_CTRL(base) MMIO32((base) + 0x00) +#define DAC_STATUS(base) MMIO32((base) + 0x04) +#define DAC_CHx_CTRL(base, x) MMIO32((base) + 0x08 + (0x04 * (x))) +#define DAC_CH0CTRL(base) DAC_CHx_CTRL(base, 0) +#define DAC_CH1CTRL(base) DAC_CHx_CTRL(base, 1) +#define DAC_IEN(base) MMIO32((base) + 0x010) +#define DAC_IF(base) MMIO32((base) + 0x014) +#define DAC_IFS(base) MMIO32((base) + 0x018) +#define DAC_IFC(base) MMIO32((base) + 0x01C) +#define DAC_CH0DATA(base) MMIO32((base) + 0x020) +#define DAC_CH1DATA(base) MMIO32((base) + 0x024) +#define DAC_COMBDATA(base) MMIO32((base) + 0x028) +#define DAC_CAL(base) MMIO32((base) + 0x02C) +#define DAC_BIASPROG(base) MMIO32((base) + 0x030) +#define DAC_OPACTRL(base) MMIO32((base) + 0x054) +#define DAC_OPAOFFSET(base) MMIO32((base) + 0x058) +#define DAC_OPA0MUX(base) MMIO32((base) + 0x05C) +#define DAC_OPA1MUX(base) MMIO32((base) + 0x060) +#define DAC_OPA2MUX(base) MMIO32((base) + 0x064) + +/* DAC_CTRL */ +#define DAC_CTRL_REFRSEL_SHIFT (20) +#define DAC_CTRL_REFRSEL_MASK (0x3 << DAC_CTRL_REFRSEL_SHIFT) +#define DAC_CTRL_REFRSEL(v) \ + (((v) << DAC_CTRL_REFRSEL_SHIFT) & DAC_CTRL_REFRSEL_MASK) +#define DAC_CTRL_REFRSEL_8CYCLES 0 +#define DAC_CTRL_REFRSEL_16CYCLES 1 +#define DAC_CTRL_REFRSEL_32CYCLES 2 +#define DAC_CTRL_REFRSEL_64CYCLES 3 + +#define DAC_CTRL_PRESC_SHIFT (16) +#define DAC_CTRL_PRESC_MASK (0x7 << DAC_CTRL_PRESC_SHIFT) +#define DAC_CTRL_PRESC(v) \ + (((v) << DAC_CTRL_PRESC_SHIFT) & DAC_CTRL_PRESC_MASK) +#define DAC_CTRL_PRESC_DIV1 0 +#define DAC_CTRL_PRESC_DIV2 1 +#define DAC_CTRL_PRESC_DIV4 2 +#define DAC_CTRL_PRESC_DIV8 3 +#define DAC_CTRL_PRESC_DIV16 4 +#define DAC_CTRL_PRESC_DIV32 5 +#define DAC_CTRL_PRESC_DIV64 6 +#define DAC_CTRL_PRESC_DIV128 7 +#define DAC_CTRL_PRESC_NODIV DAC_CTRL_PRESC_DIV1 + +#define DAC_CTRL_REFSEL_SHIFT (8) +#define DAC_CTRL_REFSEL_MASK (0x3 << DAC_CTRL_REFSEL_SHIFT) +#define DAC_CTRL_REFSEL(v) \ + (((v) << DAC_CTRL_REFSEL_SHIFT) & DAC_CTRL_REFSEL_MASK) +#define DAC_CTRL_REFSEL_1V25 0 +#define DAC_CTRL_REFSEL_2V5 1 +#define DAC_CTRL_REFSEL_VDD 2 + +#define DAC_CTRL_CH0PRESCRST (1 << 7) +#define DAC_CTRL_OUTENPRS (1 << 6) + +#define DAC_CTRL_OUTMODE_SHIFT (4) +#define DAC_CTRL_OUTMODE_MASK (0x3 << DAC_CTRL_OUTMODE_SHIFT) +#define DAC_CTRL_OUTMODE(v) \ + (((v) << DAC_CTRL_OUTMODE_SHIFT) & DAC_CTRL_OUTMODE_MASK) +#define DAC_CTRL_OUTMODE_DISABLE 0 +#define DAC_CTRL_OUTMODE_PIN 1 +#define DAC_CTRL_OUTMODE_ADC 2 +#define DAC_CTRL_OUTMODE_PINADC 3 + +#define DAC_CTRL_CONVMODE_SHIFT (2) +#define DAC_CTRL_CONVMODE_MASK (0x3 << DAC_CTRL_CONVMODE_SHIFT) +#define DAC_CTRL_CONVMODE(v) \ + (((v) << DAC_CTRL_CONVMODE_SHIFT) & DAC_CTRL_CONVMODE_MASK) +#define DAC_CTRL_CONVMODE_CONTINUOUS 0 +#define DAC_CTRL_CONVMODE_SAMPLEHOLD 1 +#define DAC_CTRL_CONVMODE_SAMPLEOFF 2 + +#define DAC_CTRL_SINMODE (1 << 1) +#define DAC_CTRL_DIFF (1 << 0) + +/* DAC_STATUS */ +#define DAC_STATUS_CH1DV (1 << 1) +#define DAC_STATUS_CH0DV (1 << 0) + +/* DAC_CH_CTRL */ +#define DAC_CH_CTRL_PRSSEL_SHIFT (4) +#define DAC_CH_CTRL_PRSSEL_MASK (0xF << DAC_CH_CTRL_PRSSEL_SHIFT) +#define DAC_CH_CTRL_PRSSEL(v) \ + (((v) << DAC_CH_CTRL_PRSSEL_SHIFT) & DAC_CH_CTRL_PRSSEL_MASK) +#define DAC_CH_CTRL_PRSSEL_PRSCHx(x) DAC_CH_CTRL_PRSSEL(x) +#define DAC_CH_CTRL_PRSSEL_PRSCH0 0 +#define DAC_CH_CTRL_PRSSEL_PRSCH1 1 +#define DAC_CH_CTRL_PRSSEL_PRSCH2 2 +#define DAC_CH_CTRL_PRSSEL_PRSCH3 3 +#define DAC_CH_CTRL_PRSSEL_PRSCH4 4 +#define DAC_CH_CTRL_PRSSEL_PRSCH5 5 +#define DAC_CH_CTRL_PRSSEL_PRSCH6 6 +#define DAC_CH_CTRL_PRSSEL_PRSCH7 7 +#define DAC_CH_CTRL_PRSSEL_PRSCH8 8 +#define DAC_CH_CTRL_PRSSEL_PRSCH9 9 +#define DAC_CH_CTRL_PRSSEL_PRSCH10 10 +#define DAC_CH_CTRL_PRSSEL_PRSCH11 11 + +#define DAC_CH_CTRL_PRSEN (1 << 2) +#define DAC_CH_CTRL_REFREN (1 << 1) +#define DAC_CH_CTRL_EN (1 << 0) + +/* DAC_CH0CTRL */ +#define DAC_CH0CTRL_PRSSEL_SHIFT DAC_CH_CTRL_PRSSEL_SHIFT +#define DAC_CH0CTRL_PRSSEL_MASK DAC_CH_CTRL_PRSSEL_MASK +#define DAC_CH0CTRL_PRSSEL(v) DAC_CH_CTRL_PRSSEL(v) +#define DAC_CH0CTRL_PRSSEL_PRSCHx(x) DAC_CH_CTRL_PRSSEL_PRSCHx(x) +#define DAC_CH0CTRL_PRSSEL_PRSCH0 DAC_CH0CTRL_PRSSEL_PRSCH0 +#define DAC_CH0CTRL_PRSSEL_PRSCH1 DAC_CH_CTRL_PRSSEL_PRSCH1 +#define DAC_CH0CTRL_PRSSEL_PRSCH2 DAC_CH_CTRL_PRSSEL_PRSCH2 +#define DAC_CH0CTRL_PRSSEL_PRSCH3 DAC_CH_CTRL_PRSSEL_PRSCH3 +#define DAC_CH0CTRL_PRSSEL_PRSCH4 DAC_CH_CTRL_PRSSEL_PRSCH4 +#define DAC_CH0CTRL_PRSSEL_PRSCH5 DAC_CH_CTRL_PRSSEL_PRSCH5 +#define DAC_CH0CTRL_PRSSEL_PRSCH6 DAC_CH_CTRL_PRSSEL_PRSCH6 +#define DAC_CH0CTRL_PRSSEL_PRSCH7 DAC_CH_CTRL_PRSSEL_PRSCH7 +#define DAC_CH0CTRL_PRSSEL_PRSCH8 DAC_CH_CTRL_PRSSEL_PRSCH8 +#define DAC_CH0CTRL_PRSSEL_PRSCH9 DAC_CH_CTRL_PRSSEL_PRSCH9 +#define DAC_CH0CTRL_PRSSEL_PRSCH10 DAC_CH_CTRL_PRSSEL_PRSCH10 +#define DAC_CH0CTRL_PRSSEL_PRSCH11 DAC_CH_CTRL_PRSSEL_PRSCH11 + +#define DAC_CH0CTRL_PRSEN DAC_CH_CTRL_PRSEN +#define DAC_CH0CTRL_REFREN DAC_CH_CTRL_REFREN +#define DAC_CH0CTRL_EN DAC_CH_CTRL_EN + +/* DAC_CH1CTRL */ +#define DAC_CH1CTRL_PRSSEL_SHIFT DAC_CH_CTRL_PRSSEL_SHIFT +#define DAC_CH1CTRL_PRSSEL_MASK DAC_CH_CTRL_PRSSEL_MASK +#define DAC_CH1CTRL_PRSSEL(v) DAC_CH_CTRL_PRSSEL(v) +#define DAC_CH1CTRL_PRSSEL_PRSCHx(x) DAC_CH_CTRL_PRSSEL_PRSCHx(x) +#define DAC_CH1CTRL_PRSSEL_PRSCH0 DAC_CH_CTRL_PRSSEL_PRSCH0 +#define DAC_CH1CTRL_PRSSEL_PRSCH1 DAC_CH_CTRL_PRSSEL_PRSCH1 +#define DAC_CH1CTRL_PRSSEL_PRSCH2 DAC_CH_CTRL_PRSSEL_PRSCH2 +#define DAC_CH1CTRL_PRSSEL_PRSCH3 DAC_CH_CTRL_PRSSEL_PRSCH3 +#define DAC_CH1CTRL_PRSSEL_PRSCH4 DAC_CH_CTRL_PRSSEL_PRSCH4 +#define DAC_CH1CTRL_PRSSEL_PRSCH5 DAC_CH_CTRL_PRSSEL_PRSCH5 +#define DAC_CH1CTRL_PRSSEL_PRSCH6 DAC_CH_CTRL_PRSSEL_PRSCH6 +#define DAC_CH1CTRL_PRSSEL_PRSCH7 DAC_CH_CTRL_PRSSEL_PRSCH7 +#define DAC_CH1CTRL_PRSSEL_PRSCH8 DAC_CH_CTRL_PRSSEL_PRSCH8 +#define DAC_CH1CTRL_PRSSEL_PRSCH9 DAC_CH_CTRL_PRSSEL_PRSCH9 +#define DAC_CH1CTRL_PRSSEL_PRSCH10 DAC_CH_CTRL_PRSSEL_PRSCH10 +#define DAC_CH1CTRL_PRSSEL_PRSCH11 DAC_CH_CTRL_PRSSEL_PRSCH11 + +#define DAC_CH1CTRL_PRSEN DAC_CH_CTRL_PRSEN +#define DAC_CH1CTRL_REFREN DAC_CH_CTRL_REFREN +#define DAC_CH1CTRL_EN DAC_CH_CTRL_EN + +/* DAC_IEN */ +#define DAC_IEN_CH1UF (5 << 0) +#define DAC_IEN_CH0UF (4 << 0) +#define DAC_IEN_CH1 (1 << 1) +#define DAC_IEN_CH0 (1 << 0) + +/* DAC_IF */ +#define DAC_IF_CH1UF (5 << 0) +#define DAC_IF_CH0UF (4 << 0) +#define DAC_IF_CH1 (1 << 1) +#define DAC_IF_CH0 (1 << 0) + +/* DAC_IFS */ +#define DAC_IFS_CH1UF (5 << 0) +#define DAC_IFS_CH0UF (4 << 0) +#define DAC_IFS_CH1 (1 << 1) +#define DAC_IFS_CH0 (1 << 0) + +/* DAC_IFC */ +#define DAC_IFC_CH1UF (5 << 0) +#define DAC_IFC_CH0UF (4 << 0) +#define DAC_IFC_CH1 (1 << 1) +#define DAC_IFC_CH0 (1 << 0) + +/* DAC_CAL */ +#define DAC_CAL_GAIN_SHIFT (16) +#define DAC_CAL_GAIN_MASK (0x7F << DAC_CAL_GAIN_SHIFT) +#define DAC_CAL_GAIN(v) \ + (((v) << DAC_CAL_GAIN_SHIFT) & DAC_CAL_GAIN_MASK) + +#define DAC_CAL_CH1OFFSET_SHIFT (8) +#define DAC_CAL_CH1OFFSET_MASK (0x3F << DAC_CAL_CH1OFFSET_SHIFT) +#define DAC_CAL_CH1OFFSET(v) \ + (((v) << DAC_CAL_CH1OFFSET_SHIFT) & DAC_CAL_CH1OFFSET_MASK) + +#define DAC_CAL_CH0OFFSET_SHIFT (0) +#define DAC_CAL_CH0OFFSET_MASK (0x3F << DAC_CAL_CH0OFFSET_SHIFT) +#define DAC_CAL_CH0OFFSET(v) \ + (((v) << DAC_CAL_CH0OFFSET_SHIFT) & DAC_CAL_CH0OFFSET_MASK) + +/* DAC_BIASPROG */ +#define DAC_BIASPROG_OPA2HALFBIAS (1 << 14) + +#define DAC_BIASPROG_OPA2BIASPROG_SHIFT (8) +#define DAC_BIASPROG_OPA2BIASPROG_MASK (0xF << DAC_BIASPROG_OPA2BIASPROG_SHIFT) +#define DAC_BIASPROG_OPA2BIASPROG(v) \ + ((((v) << DAC_BIASPROG_OPA2BIASPROG_SHIFT)) & \ + DAC_BIASPROG_OPA2BIASPROG_MASK) + +#define DAC_BIASPROG_HALFBIAS (1 << 6) + +#define DAC_BIASPROG_BIASPROG_SHIFT (0) +#define DAC_BIASPROG_BIASPROG_MASK (0xF << DAC_BIASPROG_BIASPROG_SHIFT) +#define DAC_BIASPROG_BIASPROG(v) \ + ((((v) << DAC_BIASPROG_BIASPROG_SHIFT)) & DAC_BIASPROG_BIASPROG_MASK) + +/* DAC_OPACTRL */ +#define DAC_OPACTRL_OPA2SHORT (1 << 24) +#define DAC_OPACTRL_OPA1SHORT (1 << 23) +#define DAC_OPACTRL_OPA0SHORT (1 << 22) + +#define DAC_OPACTRL_OPA2LPFDIS_SHIFT (16) +#define DAC_OPACTRL_OPA2LPFDIS_MASK (0x3 << DAC_OPACTRL_OPA2LPFDIS_SHIFT) +#define DAC_OPACTRL_OPA2LPFDIS(v) \ + (((v) << DAC_OPACTRL_OPA2LPFDIS_SHIFT) & DAC_OPACTRL_OPA2LPFDIS_MASK) +#define DAC_OPACTRL_OPA2LPFDIS_PLPFDIS 0b01 +#define DAC_OPACTRL_OPA2LPFDIS_NLPFDIS 0b10 + +#define DAC_OPACTRL_OPA1LPFDIS_SHIFT (14) +#define DAC_OPACTRL_OPA1LPFDIS_MASK (0x3 << DAC_OPACTRL_OPA1LPFDIS_SHIFT) +#define DAC_OPACTRL_OPA1LPFDIS(v) \ + (((v) << DAC_OPACTRL_OPA1LPFDIS_SHIFT) & DAC_OPACTRL_OPA1LPFDIS_MASK) +#define DAC_OPACTRL_OPA1LPFDIS_PLPFDIS 0b01 +#define DAC_OPACTRL_OPA1LPFDIS_NLPFDIS 0b10 + +#define DAC_OPACTRL_OPA0LPFDIS_SHIFT (14) +#define DAC_OPACTRL_OPA0LPFDIS_MASK (0x3 << DAC_OPACTRL_OPA0LPFDIS_SHIFT) +#define DAC_OPACTRL_OPA0LPFDIS(v) \ + (((v) << DAC_OPACTRL_OPA0LPFDIS_SHIFT) & DAC_OPACTRL_OPA0LPFDIS_MASK) +#define DAC_OPACTRL_OPA0LPFDIS_PLPFDIS 0b01 +#define DAC_OPACTRL_OPA0LPFDIS_NLPFDIS 0b10 + +#define DAC_OPACTRL_OPA2HCMDIS (1 << 8) +#define DAC_OPACTRL_OPA1HCMDIS (1 << 7) +#define DAC_OPACTRL_OPA0HCMDIS (1 << 6) + +#define DAC_OPACTRL_OPA2EN (1 << 2) +#define DAC_OPACTRL_OPA1EN (1 << 1) +#define DAC_OPACTRL_OPA0EN (1 << 0) + +/* DAC_OPA0MUX */ +#define DAC_OPA0MUX_RESSEL_SHIFT (28) +#define DAC_OPA0MUX_RESSEL_MASK (0x7 << DAC_OPA0MUX_RESSEL_SHIFT) +#define DAC_OPA0MUX_RESSEL_RESSEL(v) \ + ((((v) << DAC_OPA0MUX_RESSEL_SHIFT)) & DAC_OPA0MUX_RESSEL_MASK) +#define DAC_OPA0MUX_RESSEL_RESSEL_RESx(x) DAC_OPA0MUX_RESSEL_RESSEL(x) +#define DAC_OPA0MUX_RESSEL_RESSEL_RES0 DAC_OPA0MUX_RESSEL_RESSEL_RESx(0) +#define DAC_OPA0MUX_RESSEL_RESSEL_RES1 DAC_OPA0MUX_RESSEL_RESSEL_RESx(1) +#define DAC_OPA0MUX_RESSEL_RESSEL_RES2 DAC_OPA0MUX_RESSEL_RESSEL_RESx(2) +#define DAC_OPA0MUX_RESSEL_RESSEL_RES3 DAC_OPA0MUX_RESSEL_RESSEL_RESx(3) +#define DAC_OPA0MUX_RESSEL_RESSEL_RES4 DAC_OPA0MUX_RESSEL_RESSEL_RESx(4) +#define DAC_OPA0MUX_RESSEL_RESSEL_RES5 DAC_OPA0MUX_RESSEL_RESSEL_RESx(5) +#define DAC_OPA0MUX_RESSEL_RESSEL_RES6 DAC_OPA0MUX_RESSEL_RESSEL_RESx(6) +#define DAC_OPA0MUX_RESSEL_RESSEL_RES7 DAC_OPA0MUX_RESSEL_RESSEL_RESx(7) + +#define DAC_OPA0MUX_NEXTOUT (1 << 26) + +#define DAC_OPA0MUX_OUTMODE_SHIFT (22) +#define DAC_OPA0MUX_OUTMODE_MASK (0x3 << DAC_OPA0MUX_OUTMODE_SHIFT) +#define DAC_OPA0MUX_OUTMODE(v) \ + (((v) << DAC_OPA0MUX_OUTMODE_SHIFT) & DAC_OPA0MUX_OUTMODE_MASK) +#define DAC_OPA0MUX_OUTMODE_DISABLE 0 +#define DAC_OPA0MUX_OUTMODE_MAIN 1 +#define DAC_OPA0MUX_OUTMODE_ALT 2 +#define DAC_OPA0MUX_OUTMODE_ALL 3 + +#define DAC_OPA0MUX_OUTPEN_SHIFT (18) +#define DAC_OPA0MUX_OUTPEN_MASK (0x1F << DAC_OPA0MUX_OUTPEN_SHIFT) +#define DAC_OPA0MUX_OUTPEN(v) \ + (((v) << DAC_OPA0MUX_OUTPEN_SHIFT) & DAC_OPA0MUX_OUTPEN_MASK) +#define DAC_OPA0MUX_OUTPEN_OUT0 DAC_OPA0MUX_OUTPEN(1 << 0) +#define DAC_OPA0MUX_OUTPEN_OUT1 DAC_OPA0MUX_OUTPEN(1 << 1) +#define DAC_OPA0MUX_OUTPEN_OUT2 DAC_OPA0MUX_OUTPEN(1 << 2) +#define DAC_OPA0MUX_OUTPEN_OUT3 DAC_OPA0MUX_OUTPEN(1 << 3) +#define DAC_OPA0MUX_OUTPEN_OUT4 DAC_OPA0MUX_OUTPEN(1 << 4) + +#define DAC_OPA0MUX_NPEN (1 << 13) +#define DAC_OPA0MUX_PPEN (1 << 12) + +#define DAC_OPA0MUX_RESINMUX_SHIFT (8) +#define DAC_OPA0MUX_RESINMUX_MASK (0x7 << DAC_OPA0MUX_RESINMUX_SHIFT) +#define DAC_OPA0MUX_RESINMUX(v) \ + (((v) << DAC_OPA0MUX_RESINMUX_SHIFT) & DAC_OPA0MUX_RESINMUX_MASK) +#define DAC_OPA0MUX_RESINMUX_DISABLE 0 +#define DAC_OPA0MUX_RESINMUX_OPA0INP 1 +#define DAC_OPA0MUX_RESINMUX_NEGPAD 2 +#define DAC_OPA0MUX_RESINMUX_POSPAD 3 +#define DAC_OPA0MUX_RESINMUX_VSS 4 + +#define DAC_OPA0MUX_NEGSEL_SHIFT (4) +#define DAC_OPA0MUX_NEGSEL_MASK (0x3 << DAC_OPA0MUX_NEGSEL_SHIFT) +#define DAC_OPA0MUX_NEGSEL(v) \ + (((v) << DAC_OPA0MUX_NEGSEL_SHIFT) & DAC_OPA0MUX_NEGSEL_MASK) +#define DAC_OPA0MUX_NEGSEL_DISABLE 0 +#define DAC_OPA0MUX_NEGSEL_UG 1 +#define DAC_OPA0MUX_NEGSEL_OPATAP 2 +#define DAC_OPA0MUX_NEGSEL_NEGPAD 3 + +#define DAC_OPA0MUX_POSSEL_SHIFT (0) +#define DAC_OPA0MUX_POSSEL_MASK (0x7 << DAC_OPA0MUX_POSSEL_SHIFT) +#define DAC_OPA0MUX_POSSEL(v) \ + (((v) << DAC_OPA0MUX_POSSEL_SHIFT) & DAC_OPA0MUX_POSSEL_MASK) +#define DAC_OPA0MUX_POSSEL_DISABLE 0 +#define DAC_OPA0MUX_POSSEL_DAC 1 +#define DAC_OPA0MUX_POSSEL_POSPAD 2 +#define DAC_OPA0MUX_POSSEL_OPA0INP 3 +#define DAC_OPA0MUX_POSSEL_OPATAP 4 + +/* DAC_OPA1MUX */ +#define DAC_OPA1MUX_RESSEL_SHIFT (28) +#define DAC_OPA1MUX_RESSEL_MASK (0x7 << DAC_OPA1MUX_RESSEL_SHIFT) +#define DAC_OPA1MUX_RESSEL_RESSEL(v) \ + ((((v) << DAC_OPA1MUX_RESSEL_SHIFT)) & DAC_OPA1MUX_RESSEL_MASK) +#define DAC_OPA1MUX_RESSEL_RESSEL_RESx(x) DAC_OPA1MUX_RESSEL_RESSEL(x) +#define DAC_OPA1MUX_RESSEL_RESSEL_RES0 DAC_OPA1MUX_RESSEL_RESSEL_RESx(0) +#define DAC_OPA1MUX_RESSEL_RESSEL_RES1 DAC_OPA1MUX_RESSEL_RESSEL_RESx(1) +#define DAC_OPA1MUX_RESSEL_RESSEL_RES2 DAC_OPA1MUX_RESSEL_RESSEL_RESx(2) +#define DAC_OPA1MUX_RESSEL_RESSEL_RES3 DAC_OPA1MUX_RESSEL_RESSEL_RESx(3) +#define DAC_OPA1MUX_RESSEL_RESSEL_RES4 DAC_OPA1MUX_RESSEL_RESSEL_RESx(4) +#define DAC_OPA1MUX_RESSEL_RESSEL_RES5 DAC_OPA1MUX_RESSEL_RESSEL_RESx(5) +#define DAC_OPA1MUX_RESSEL_RESSEL_RES6 DAC_OPA1MUX_RESSEL_RESSEL_RESx(6) +#define DAC_OPA1MUX_RESSEL_RESSEL_RES7 DAC_OPA1MUX_RESSEL_RESSEL_RESx(7) + +#define DAC_OPA1MUX_NEXTOUT (1 << 26) + +#define DAC_OPA1MUX_OUTMODE_SHIFT (22) +#define DAC_OPA1MUX_OUTMODE_MASK (0x3 << DAC_OPA1MUX_OUTMODE_SHIFT) +#define DAC_OPA1MUX_OUTMODE(v) \ + (((v) << DAC_OPA1MUX_OUTMODE_SHIFT) & DAC_OPA1MUX_OUTMODE_MASK) +#define DAC_OPA1MUX_OUTMODE_DISABLE 0 +#define DAC_OPA1MUX_OUTMODE_MAIN 1 +#define DAC_OPA1MUX_OUTMODE_ALT 2 +#define DAC_OPA1MUX_OUTMODE_ALL 3 + +#define DAC_OPA1MUX_OUTPEN_SHIFT (18) +#define DAC_OPA1MUX_OUTPEN_MASK (0x1F << DAC_OPA1MUX_OUTPEN_SHIFT) +#define DAC_OPA1MUX_OUTPEN(v) \ + (((v) << DAC_OPA1MUX_OUTPEN_SHIFT) & DAC_OPA1MUX_OUTPEN_MASK) +#define DAC_OPA1MUX_OUTPEN_OUT0 DAC_OPA1MUX_OUTPEN(1 << 0) +#define DAC_OPA1MUX_OUTPEN_OUT1 DAC_OPA1MUX_OUTPEN(1 << 1) +#define DAC_OPA1MUX_OUTPEN_OUT2 DAC_OPA1MUX_OUTPEN(1 << 2) +#define DAC_OPA1MUX_OUTPEN_OUT3 DAC_OPA1MUX_OUTPEN(1 << 3) +#define DAC_OPA1MUX_OUTPEN_OUT4 DAC_OPA1MUX_OUTPEN(1 << 4) + +#define DAC_OPA1MUX_NPEN (1 << 13) +#define DAC_OPA1MUX_PPEN (1 << 12) + +#define DAC_OPA1MUX_RESINMUX_SHIFT (8) +#define DAC_OPA1MUX_RESINMUX_MASK (0x7 << DAC_OPA1MUX_RESINMUX_SHIFT) +#define DAC_OPA1MUX_RESINMUX(v) \ + (((v) << DAC_OPA1MUX_RESINMUX_SHIFT) & DAC_OPA1MUX_RESINMUX_MASK) +#define DAC_OPA1MUX_RESINMUX_DISABLE 0 +#define DAC_OPA1MUX_RESINMUX_OPA0INP 1 +#define DAC_OPA1MUX_RESINMUX_NEGPAD 2 +#define DAC_OPA1MUX_RESINMUX_POSPAD 3 +#define DAC_OPA1MUX_RESINMUX_VSS 4 + +#define DAC_OPA1MUX_NEGSEL_SHIFT (4) +#define DAC_OPA1MUX_NEGSEL_MASK (0x3 << DAC_OPA1MUX_NEGSEL_SHIFT) +#define DAC_OPA1MUX_NEGSEL(v) \ + (((v) << DAC_OPA1MUX_NEGSEL_SHIFT) & DAC_OPA1MUX_NEGSEL_MASK) +#define DAC_OPA1MUX_NEGSEL_DISABLE 0 +#define DAC_OPA1MUX_NEGSEL_UG 1 +#define DAC_OPA1MUX_NEGSEL_OPATAP 2 +#define DAC_OPA1MUX_NEGSEL_NEGPAD 3 + +#define DAC_OPA1MUX_POSSEL_SHIFT (0) +#define DAC_OPA1MUX_POSSEL_MASK (0x7 << DAC_OPA1MUX_POSSEL_SHIFT) +#define DAC_OPA1MUX_POSSEL(v) \ + (((v) << DAC_OPA1MUX_POSSEL_SHIFT) & DAC_OPA1MUX_POSSEL_MASK) +#define DAC_OPA1MUX_POSSEL_DISABLE 0 +#define DAC_OPA1MUX_POSSEL_DAC 1 +#define DAC_OPA1MUX_POSSEL_POSPAD 2 +#define DAC_OPA1MUX_POSSEL_OPA0INP 3 +#define DAC_OPA1MUX_POSSEL_OPATAP 4 + + +/* DAC_OPA2MUX */ +#define DAC_OPA2MUX_RESSEL_SHIFT (28) +#define DAC_OPA2MUX_RESSEL_MASK (0x7 << DAC_OPA2MUX_RESSEL_SHIFT) +#define DAC_OPA2MUX_RESSEL_RESSEL(v) \ + ((((v) << DAC_OPA2MUX_RESSEL_SHIFT)) & DAC_OPA2MUX_RESSEL_MASK) +#define DAC_OPA2MUX_RESSEL_RESSEL_RESx(x) DAC_OPA2MUX_RESSEL_RESSEL(x) +#define DAC_OPA2MUX_RESSEL_RESSEL_RES0 DAC_OPA2MUX_RESSEL_RESSEL_RESx(0) +#define DAC_OPA2MUX_RESSEL_RESSEL_RES1 DAC_OPA2MUX_RESSEL_RESSEL_RESx(1) +#define DAC_OPA2MUX_RESSEL_RESSEL_RES2 DAC_OPA2MUX_RESSEL_RESSEL_RESx(2) +#define DAC_OPA2MUX_RESSEL_RESSEL_RES3 DAC_OPA2MUX_RESSEL_RESSEL_RESx(3) +#define DAC_OPA2MUX_RESSEL_RESSEL_RES4 DAC_OPA2MUX_RESSEL_RESSEL_RESx(4) +#define DAC_OPA2MUX_RESSEL_RESSEL_RES5 DAC_OPA2MUX_RESSEL_RESSEL_RESx(5) +#define DAC_OPA2MUX_RESSEL_RESSEL_RES6 DAC_OPA2MUX_RESSEL_RESSEL_RESx(6) +#define DAC_OPA2MUX_RESSEL_RESSEL_RES7 DAC_OPA2MUX_RESSEL_RESSEL_RESx(7) + +#define DAC_OPA2MUX_NEXTOUT (1 << 26) + +#define DAC_OPA2MUX_OUTMODE (1 << 22) + +#define DAC_OPA2MUX_OUTPEN_SHIFT (14) +#define DAC_OPA2MUX_OUTPEN_MASK (0x3 << DAC_OPA2MUX_OUTPEN_SHIFT) +#define DAC_OPA2MUX_OUTPEN(v) \ + (((v) << DAC_OPA2MUX_OUTPEN_SHIFT) & DAC_OPA2MUX_OUTPEN_MASK) +#define DAC_OPA2MUX_OUTPEN_OUT0 0 +#define DAC_OPA2MUX_OUTPEN_OUT1 1 + +#define DAC_OPA2MUX_NPEN (1 << 13) +#define DAC_OPA2MUX_PPEN (1 << 12) + +#define DAC_OPA2MUX_RESINMUX_SHIFT (8) +#define DAC_OPA2MUX_RESINMUX_MASK (0x7 << DAC_OPA2MUX_RESINMUX_SHIFT) +#define DAC_OPA2MUX_RESINMUX(v) \ + (((v) << DAC_OPA2MUX_RESINMUX_SHIFT) & DAC_OPA2MUX_RESINMUX_MASK) +#define DAC_OPA2MUX_RESINMUX_DISABLE 0 +#define DAC_OPA2MUX_RESINMUX_OPA1INP 1 +#define DAC_OPA2MUX_RESINMUX_NEGPAD 2 +#define DAC_OPA2MUX_RESINMUX_POSPAD 3 +#define DAC_OPA2MUX_RESINMUX_VSS 4 + +#define DAC_OPA2MUX_NEGSEL_SHIFT (4) +#define DAC_OPA2MUX_NEGSEL_MASK (0x3 << DAC_OPA2MUX_NEGSEL_SHIFT) +#define DAC_OPA2MUX_NEGSEL(v) \ + (((v) << DAC_OPA2MUX_NEGSEL_SHIFT) & DAC_OPA2MUX_NEGSEL_MASK) +#define DAC_OPA2MUX_NEGSEL_DISABLE 0 +#define DAC_OPA2MUX_NEGSEL_UG 1 +#define DAC_OPA2MUX_NEGSEL_OPATAP 2 +#define DAC_OPA2MUX_NEGSEL_NEGPAD 3 + +#define DAC_OPA2MUX_POSSEL_SHIFT (0) +#define DAC_OPA2MUX_POSSEL_MASK (0x7 << DAC_OPA2MUX_POSSEL_SHIFT) +#define DAC_OPA2MUX_POSSEL(v) \ + (((v) << DAC_OPA2MUX_POSSEL_SHIFT) & DAC_OPA2MUX_POSSEL_MASK) +#define DAC_OPA2MUX_POSSEL_DISABLE 0 +#define DAC_OPA2MUX_POSSEL_DAC 1 +#define DAC_OPA2MUX_POSSEL_POSPAD 2 +#define DAC_OPA2MUX_POSSEL_OPA1INP 3 +#define DAC_OPA2MUX_POSSEL_OPATAP 4 + +/* DAC0 */ +#define DAC0 DAC0_BASE +#define DAC0_CTRL DAC_CTRL(DAC0) +#define DAC0_STATUS DAC_STATUS(DAC0) +#define DAC0_CH0CTRL DAC_CH0CTRL(DAC0) +#define DAC0_CH1CTRL DAC_CH1CTRL(DAC0) +#define DAC0_IEN DAC_IEN(DAC0) +#define DAC0_IF DAC_IF(DAC0) +#define DAC0_IFS DAC_IFS(DAC0) +#define DAC0_IFC DAC_IFC(DAC0) +#define DAC0_CH0DATA DAC_CH0DATA(DAC0) +#define DAC0_CH1DATA DAC_CH1DATA(DAC0) +#define DAC0_COMBDATA DAC_COMBDATA(DAC0) +#define DAC0_CAL DAC_CAL(DAC0) +#define DAC0_BIASPROG DAC_BIASPROG(DAC0) +#define DAC0_OPACTRL DAC_OPACTRL(DAC0) +#define DAC0_OPAOFFSET DAC_OPAOFFSET(DAC0) +#define DAC0_OPAOFFSET DAC_OPAOFFSET(DAC0) +#define DAC0_OPA1MUX DAC_OPA1MUX(DAC0) +#define DAC0_OPA2MUX DAC_OPA2MUX(DAC0) + +/** @defgroup dac_ch DAC Channel Number +@ingroup dac_defines + +@{*/ +enum dac_ch { + DAC_CH0 = 0, + DAC_CH1 +}; +/**@}*/ + +BEGIN_DECLS + +void dac_set_refresh_cycle(uint32_t dac_base, uint32_t refrsel); +void dac_set_clock_prescaler(uint32_t dac_base, uint32_t presc); +void dac_set_reference(uint32_t dac_base, uint32_t refsel); +void dac_set_out_mode(uint32_t dac_base, uint32_t outmode); +void dac_set_conversion_mode(uint32_t dac_base, uint32_t convmode); +void dac_enable_sine(uint32_t dac_base); +void dac_disable_sine(uint32_t dac_base); + +void dac_set_prs_trigger(uint32_t dac_base, enum dac_ch dac_chan, + enum prs_ch prs_chan); +void dac_enable_prs_trigger(uint32_t dac_base, enum dac_ch ch); +void dac_disable_prs_trigger(uint32_t dac_base, enum dac_ch ch); +void dac_enable_auto_refresh(uint32_t dac_base, enum dac_ch ch); +void dac_disable_auto_refresh(uint32_t dac_base, enum dac_ch ch); + +void dac_enable_channel(uint32_t dac_base, enum dac_ch ch); +void dac_disable_channel(uint32_t dac_base, enum dac_ch ch); + +END_DECLS + +#endif + diff --git a/include/libopencm3/efm32/common/dma_common.h b/include/libopencm3/efm32/common/dma_common.h new file mode 100644 index 00000000..6e46d9d0 --- /dev/null +++ b/include/libopencm3/efm32/common/dma_common.h @@ -0,0 +1,912 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2015 Kuldeep Singh Dhaka + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_EFM32_DMA_H +#define LIBOPENCM3_EFM32_DMA_H + +#include +#include + +/* + * As per the datasheet, it is an PL230 (licenced from ARM) + * note: but only implement 12 channel (PL230 can have upto 32 channels) + * + * in-future: we can move this to a common peripherial directory + * that is idependent of core and as well as uC. + * something like device tree in Linux kernel + * + * note: DMA_STATUS contain the number of PL230 channel are implemented + */ + +#define DMA DMA_BASE + +#define DMA_STATUS MMIO32(DMA_BASE + 0x000) +#define DMA_CONFIG MMIO32(DMA_BASE + 0x004) +#define DMA_CTRLBASE MMIO32(DMA_BASE + 0x008) +#define DMA_ALTCTRLBASE MMIO32(DMA_BASE + 0x00C) + +#define DMA_CHWAITSTATUS MMIO32(DMA_BASE + 0x010) +#define DMA_CHSWREQ MMIO32(DMA_BASE + 0x014) +#define DMA_CHUSEBURSTS MMIO32(DMA_BASE + 0x018) +#define DMA_CHUSEBURSTC MMIO32(DMA_BASE + 0x01C) +#define DMA_CHREQMASKS MMIO32(DMA_BASE + 0x020) +#define DMA_CHREQMASKC MMIO32(DMA_BASE + 0x024) +#define DMA_CHENS MMIO32(DMA_BASE + 0x028) +#define DMA_CHENC MMIO32(DMA_BASE + 0x02C) +#define DMA_CHALTS MMIO32(DMA_BASE + 0x030) +#define DMA_CHALTC MMIO32(DMA_BASE + 0x034) +#define DMA_CHPRIS MMIO32(DMA_BASE + 0x038) +#define DMA_CHPRIC MMIO32(DMA_BASE + 0x03C) +#define DMA_ERRORC MMIO32(DMA_BASE + 0x04C) +#define DMA_CHREQSTATUS MMIO32(DMA_BASE + 0xE10) +#define DMA_CHSREQSTATUS MMIO32(DMA_BASE + 0xE18) +#define DMA_IF MMIO32(DMA_BASE + 0x1000) +#define DMA_IFS MMIO32(DMA_BASE + 0x1004) +#define DMA_IFC MMIO32(DMA_BASE + 0x1008) +#define DMA_IEN MMIO32(DMA_BASE + 0x100C) +#define DMA_CTRL MMIO32(DMA_BASE + 0x1010) +#define DMA_RDS MMIO32(DMA_BASE + 0x1014) + +#define DMA_LOOPx(i) MMIO32(DMA_BASE + 0x1020 + ((i) * 0x4)) +#define DMA_LOOP0 DMA_LOOPx(0) +#define DMA_LOOP1 DMA_LOOPx(1) + +#define DMA_RECTx(i) MMIO32(DMA_BASE + 0x1060 + ((i) * 0x4)) +#define DMA_RECT0 DMA_RECT(0) + +#define DMA_CHx_CTRL(i) MMIO32(DMA_BASE + 0x1100 + ((i) * 0x4)) +#define DMA_CH0_CTRL DMA_CHx_CTRL(0) +#define DMA_CH1_CTRL DMA_CHx_CTRL(1) +#define DMA_CH2_CTRL DMA_CHx_CTRL(2) +#define DMA_CH3_CTRL DMA_CHx_CTRL(3) +#define DMA_CH4_CTRL DMA_CHx_CTRL(4) +#define DMA_CH5_CTRL DMA_CHx_CTRL(5) +#define DMA_CH6_CTRL DMA_CHx_CTRL(6) +#define DMA_CH7_CTRL DMA_CHx_CTRL(7) +#define DMA_CH8_CTRL DMA_CHx_CTRL(8) +#define DMA_CH9_CTRL DMA_CHx_CTRL(9) +#define DMA_CH10_CTRL DMA_CHx_CTRL(10) +#define DMA_CH11_CTRL DMA_CHx_CTRL(11) + +/* DMA_STATUS */ +#define DMA_STATUS_CHNUM_SHIFT (16) +#define DMA_STATUS_CHNUM_MASK (0x1F << DMA_STATUS_CHNUM_SHIFT) + +#define DMA_STATUS_STATE_SHIFT (4) +#define DMA_STATUS_STATE_MASK (0xF << DMA_STATUS_STATE_SHIFT) +#define DMA_STATUS_STATE(v) \ + (((v) << DMA_STATUS_STATE_SHIFT) & DMA_STATUS_STATE_MASK) +#define DMA_STATUS_STATE_IDLE 0 +#define DMA_STATUS_STATE_RDCHCTRLDATA 1 +#define DMA_STATUS_STATE_RDSRCENDPTR 2 +#define DMA_STATUS_STATE_RDDSTENDPTR 3 +#define DMA_STATUS_STATE_RDSRCDATA 4 +#define DMA_STATUS_STATE_WRDSTDATA 5 +#define DMA_STATUS_STATE_WAITREQCLR 6 +#define DMA_STATUS_STATE_WRCHCTRLDATA 7 +#define DMA_STATUS_STATE_STALLED 8 +#define DMA_STATUS_STATE_DONE 9 +#define DMA_STATUS_STATE_PERSCATTRANS 10 + +#define DMA_STATUS_EN (1 << 0) + +/* DMA_CONFIG */ +#define DMA_CONFIG_CHPROT (1 << 5) +#define DMA_CONFIG_EN (1 << 0) + +/* DMA_CHWAITSTATUS */ +#define DMA_CHWAITSTATUS_CHxWAITSTATUS(i) (1 << (i)) +#define DMA_CHWAITSTATUS_CH11WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(11) +#define DMA_CHWAITSTATUS_CH10WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(10) +#define DMA_CHWAITSTATUS_CH9WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(9) +#define DMA_CHWAITSTATUS_CH8WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(8) +#define DMA_CHWAITSTATUS_CH7WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(7) +#define DMA_CHWAITSTATUS_CH6WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(6) +#define DMA_CHWAITSTATUS_CH5WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(5) +#define DMA_CHWAITSTATUS_CH4WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(4) +#define DMA_CHWAITSTATUS_CH3WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(3) +#define DMA_CHWAITSTATUS_CH2WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(2) +#define DMA_CHWAITSTATUS_CH1WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(1) +#define DMA_CHWAITSTATUS_CH0WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(0) + +/* DMA_CHSWREQ */ +#define DMA_CHSWREQ_CHxSWREQ(i) (1 << (i)) +#define DMA_CHSWREQ_CH11SWREQ DMA_CHSWREQ_CHxSWREQ(11) +#define DMA_CHSWREQ_CH10SWREQ DMA_CHSWREQ_CHxSWREQ(10) +#define DMA_CHSWREQ_CH9SWREQ DMA_CHSWREQ_CHxSWREQ(9) +#define DMA_CHSWREQ_CH8SWREQ DMA_CHSWREQ_CHxSWREQ(8) +#define DMA_CHSWREQ_CH7SWREQ DMA_CHSWREQ_CHxSWREQ(7) +#define DMA_CHSWREQ_CH6SWREQ DMA_CHSWREQ_CHxSWREQ(6) +#define DMA_CHSWREQ_CH5SWREQ DMA_CHSWREQ_CHxSWREQ(5) +#define DMA_CHSWREQ_CH4SWREQ DMA_CHSWREQ_CHxSWREQ(4) +#define DMA_CHSWREQ_CH3SWREQ DMA_CHSWREQ_CHxSWREQ(3) +#define DMA_CHSWREQ_CH2SWREQ DMA_CHSWREQ_CHxSWREQ(2) +#define DMA_CHSWREQ_CH1SWREQ DMA_CHSWREQ_CHxSWREQ(1) +#define DMA_CHSWREQ_CH0SWREQ DMA_CHSWREQ_CHxSWREQ(0) + +/* DMA_CHUSEBURSTS */ +#define DMA_CHUSEBURSTS_CHxSUSEBURSTS(i) (1 << (i)) +#define DMA_CHUSEBURSTS_CH11SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(11) +#define DMA_CHUSEBURSTS_CH10SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(10) +#define DMA_CHUSEBURSTS_CH9SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(9) +#define DMA_CHUSEBURSTS_CH8SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(8) +#define DMA_CHUSEBURSTS_CH7SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(7) +#define DMA_CHUSEBURSTS_CH6SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(6) +#define DMA_CHUSEBURSTS_CH5SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(5) +#define DMA_CHUSEBURSTS_CH4SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(4) +#define DMA_CHUSEBURSTS_CH3SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(3) +#define DMA_CHUSEBURSTS_CH2SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(2) +#define DMA_CHUSEBURSTS_CH1SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(1) +#define DMA_CHUSEBURSTS_CH0SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(0) + +/* DMA_CHUSEBURSTC */ +#define DMA_CHUSEBURSTC_CHxSUSEBURSTC(i) (1 << (i)) +#define DMA_CHUSEBURSTC_CH11SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(11) +#define DMA_CHUSEBURSTC_CH10SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(10) +#define DMA_CHUSEBURSTC_CH9SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(9) +#define DMA_CHUSEBURSTC_CH8SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(8) +#define DMA_CHUSEBURSTC_CH7SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(7) +#define DMA_CHUSEBURSTC_CH6SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(6) +#define DMA_CHUSEBURSTC_CH5SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(5) +#define DMA_CHUSEBURSTC_CH4SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(4) +#define DMA_CHUSEBURSTC_CH3SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(3) +#define DMA_CHUSEBURSTC_CH2SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(2) +#define DMA_CHUSEBURSTC_CH1SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(1) +#define DMA_CHUSEBURSTC_CH0SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(0) + +/* DMA_CHREQMASKS */ +#define DMA_CHREQMASKS_CHxSREQMASKS(i) (1 << (i)) +#define DMA_CHREQMASKS_CH11SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(11) +#define DMA_CHREQMASKS_CH10SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(10) +#define DMA_CHREQMASKS_CH9SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(9) +#define DMA_CHREQMASKS_CH8SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(8) +#define DMA_CHREQMASKS_CH7SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(7) +#define DMA_CHREQMASKS_CH6SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(6) +#define DMA_CHREQMASKS_CH5SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(5) +#define DMA_CHREQMASKS_CH4SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(4) +#define DMA_CHREQMASKS_CH3SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(3) +#define DMA_CHREQMASKS_CH2SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(2) +#define DMA_CHREQMASKS_CH1SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(1) +#define DMA_CHREQMASKS_CH0SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(0) + +/* DMA_CHREQMASKC */ +#define DMA_CHREQMASKC_CHxSREQMASKC(i) (1 << (i)) +#define DMA_CHREQMASKC_CH11SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(11) +#define DMA_CHREQMASKC_CH10SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(10) +#define DMA_CHREQMASKC_CH9SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(9) +#define DMA_CHREQMASKC_CH8SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(8) +#define DMA_CHREQMASKC_CH7SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(7) +#define DMA_CHREQMASKC_CH6SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(6) +#define DMA_CHREQMASKC_CH5SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(5) +#define DMA_CHREQMASKC_CH4SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(4) +#define DMA_CHREQMASKC_CH3SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(3) +#define DMA_CHREQMASKC_CH2SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(2) +#define DMA_CHREQMASKC_CH1SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(1) +#define DMA_CHREQMASKC_CH0SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(0) + +/* DMA_CHENS */ +#define DMA_CHENS_CHxSENS(i) (1 << (i)) +#define DMA_CHENS_CH11SENS DMA_CHENS_CHxSENS(11) +#define DMA_CHENS_CH10SENS DMA_CHENS_CHxSENS(10) +#define DMA_CHENS_CH9SENS DMA_CHENS_CHxSENS(9) +#define DMA_CHENS_CH8SENS DMA_CHENS_CHxSENS(8) +#define DMA_CHENS_CH7SENS DMA_CHENS_CHxSENS(7) +#define DMA_CHENS_CH6SENS DMA_CHENS_CHxSENS(6) +#define DMA_CHENS_CH5SENS DMA_CHENS_CHxSENS(5) +#define DMA_CHENS_CH4SENS DMA_CHENS_CHxSENS(4) +#define DMA_CHENS_CH3SENS DMA_CHENS_CHxSENS(3) +#define DMA_CHENS_CH2SENS DMA_CHENS_CHxSENS(2) +#define DMA_CHENS_CH1SENS DMA_CHENS_CHxSENS(1) +#define DMA_CHENS_CH0SENS DMA_CHENS_CHxSENS(0) + +/* DMA_CHENC */ +#define DMA_CHENC_CHxSENC(i) (1 << (i)) +#define DMA_CHENC_CH11SENC DMA_CHENC_CHxSENC(11) +#define DMA_CHENC_CH10SENC DMA_CHENC_CHxSENC(10) +#define DMA_CHENC_CH9SENC DMA_CHENC_CHxSENC(9) +#define DMA_CHENC_CH8SENC DMA_CHENC_CHxSENC(8) +#define DMA_CHENC_CH7SENC DMA_CHENC_CHxSENC(7) +#define DMA_CHENC_CH6SENC DMA_CHENC_CHxSENC(6) +#define DMA_CHENC_CH5SENC DMA_CHENC_CHxSENC(5) +#define DMA_CHENC_CH4SENC DMA_CHENC_CHxSENC(4) +#define DMA_CHENC_CH3SENC DMA_CHENC_CHxSENC(3) +#define DMA_CHENC_CH2SENC DMA_CHENC_CHxSENC(2) +#define DMA_CHENC_CH1SENC DMA_CHENC_CHxSENC(1) +#define DMA_CHENC_CH0SENC DMA_CHENC_CHxSENC(0) + +/* DMA_CHALTS */ +#define DMA_CHALTS_CHxSALTS(i) (1 << (i)) +#define DMA_CHALTS_CH11SALTS DMA_CHALTS_CHxSALTS(11) +#define DMA_CHALTS_CH10SALTS DMA_CHALTS_CHxSALTS(10) +#define DMA_CHALTS_CH9SALTS DMA_CHALTS_CHxSALTS(9) +#define DMA_CHALTS_CH8SALTS DMA_CHALTS_CHxSALTS(8) +#define DMA_CHALTS_CH7SALTS DMA_CHALTS_CHxSALTS(7) +#define DMA_CHALTS_CH6SALTS DMA_CHALTS_CHxSALTS(6) +#define DMA_CHALTS_CH5SALTS DMA_CHALTS_CHxSALTS(5) +#define DMA_CHALTS_CH4SALTS DMA_CHALTS_CHxSALTS(4) +#define DMA_CHALTS_CH3SALTS DMA_CHALTS_CHxSALTS(3) +#define DMA_CHALTS_CH2SALTS DMA_CHALTS_CHxSALTS(2) +#define DMA_CHALTS_CH1SALTS DMA_CHALTS_CHxSALTS(1) +#define DMA_CHALTS_CH0SALTS DMA_CHALTS_CHxSALTS(0) + +/* DMA_CHALTC */ +#define DMA_CHALTC_CHxSALTC(i) (1 << (i)) +#define DMA_CHALTC_CH11SALTC DMA_CHALTC_CHxSALTC(11) +#define DMA_CHALTC_CH10SALTC DMA_CHALTC_CHxSALTC(10) +#define DMA_CHALTC_CH9SALTC DMA_CHALTC_CHxSALTC(9) +#define DMA_CHALTC_CH8SALTC DMA_CHALTC_CHxSALTC(8) +#define DMA_CHALTC_CH7SALTC DMA_CHALTC_CHxSALTC(7) +#define DMA_CHALTC_CH6SALTC DMA_CHALTC_CHxSALTC(6) +#define DMA_CHALTC_CH5SALTC DMA_CHALTC_CHxSALTC(5) +#define DMA_CHALTC_CH4SALTC DMA_CHALTC_CHxSALTC(4) +#define DMA_CHALTC_CH3SALTC DMA_CHALTC_CHxSALTC(3) +#define DMA_CHALTC_CH2SALTC DMA_CHALTC_CHxSALTC(2) +#define DMA_CHALTC_CH1SALTC DMA_CHALTC_CHxSALTC(1) +#define DMA_CHALTC_CH0SALTC DMA_CHALTC_CHxSALTC(0) + +/* DMA_CHPRIS */ +#define DMA_CHPRIS_CHxSPRIC(i) (1 << (i)) +#define DMA_CHPRIS_CH11SPRIC DMA_CHPRIS_CHxSPRIC(11) +#define DMA_CHPRIS_CH10SPRIC DMA_CHPRIS_CHxSPRIC(10) +#define DMA_CHPRIS_CH9SPRIC DMA_CHPRIS_CHxSPRIC(9) +#define DMA_CHPRIS_CH8SPRIC DMA_CHPRIS_CHxSPRIC(8) +#define DMA_CHPRIS_CH7SPRIC DMA_CHPRIS_CHxSPRIC(7) +#define DMA_CHPRIS_CH6SPRIC DMA_CHPRIS_CHxSPRIC(6) +#define DMA_CHPRIS_CH5SPRIC DMA_CHPRIS_CHxSPRIC(5) +#define DMA_CHPRIS_CH4SPRIC DMA_CHPRIS_CHxSPRIC(4) +#define DMA_CHPRIS_CH3SPRIC DMA_CHPRIS_CHxSPRIC(3) +#define DMA_CHPRIS_CH2SPRIC DMA_CHPRIS_CHxSPRIC(2) +#define DMA_CHPRIS_CH1SPRIC DMA_CHPRIS_CHxSPRIC(1) +#define DMA_CHPRIS_CH0SPRIC DMA_CHPRIS_CHxSPRIC(0) + +/* DMA_CHPRIC */ +#define DMA_CHPRIC_CHxSPRIC(i) (1 << (i)) +#define DMA_CHPRIC_CH11SPRIC DMA_CHPRIC_CHxSPRIC(11) +#define DMA_CHPRIC_CH10SPRIC DMA_CHPRIC_CHxSPRIC(10) +#define DMA_CHPRIC_CH9SPRIC DMA_CHPRIC_CHxSPRIC(9) +#define DMA_CHPRIC_CH8SPRIC DMA_CHPRIC_CHxSPRIC(8) +#define DMA_CHPRIC_CH7SPRIC DMA_CHPRIC_CHxSPRIC(7) +#define DMA_CHPRIC_CH6SPRIC DMA_CHPRIC_CHxSPRIC(6) +#define DMA_CHPRIC_CH5SPRIC DMA_CHPRIC_CHxSPRIC(5) +#define DMA_CHPRIC_CH4SPRIC DMA_CHPRIC_CHxSPRIC(4) +#define DMA_CHPRIC_CH3SPRIC DMA_CHPRIC_CHxSPRIC(3) +#define DMA_CHPRIC_CH2SPRIC DMA_CHPRIC_CHxSPRIC(2) +#define DMA_CHPRIC_CH1SPRIC DMA_CHPRIC_CHxSPRIC(1) +#define DMA_CHPRIC_CH0SPRIC DMA_CHPRIC_CHxSPRIC(0) + +/* DMA_ERRORC */ +#define DMA_ERRORC_ERRORC (1 << 0) + +/* DMA_CHREQSTATUS */ +#define DMA_CHREQSTATUS_CHxSREQSTATUS(i) (1 << (i)) +#define DMA_CHREQSTATUS_CH11SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(11) +#define DMA_CHREQSTATUS_CH10SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(10) +#define DMA_CHREQSTATUS_CH9SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(9) +#define DMA_CHREQSTATUS_CH8SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(8) +#define DMA_CHREQSTATUS_CH7SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(7) +#define DMA_CHREQSTATUS_CH6SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(6) +#define DMA_CHREQSTATUS_CH5SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(5) +#define DMA_CHREQSTATUS_CH4SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(4) +#define DMA_CHREQSTATUS_CH3SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(3) +#define DMA_CHREQSTATUS_CH2SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(2) +#define DMA_CHREQSTATUS_CH1SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(1) +#define DMA_CHREQSTATUS_CH0SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(0) + +/* DMA_CHSREQSTATUS */ +#define DMA_CHSREQSTATUS_CHxSREQSTATUS(i) (1 << (i)) +#define DMA_CHSREQSTATUS_CH11SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(11) +#define DMA_CHSREQSTATUS_CH10SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(10) +#define DMA_CHSREQSTATUS_CH9SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(9) +#define DMA_CHSREQSTATUS_CH8SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(8) +#define DMA_CHSREQSTATUS_CH7SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(7) +#define DMA_CHSREQSTATUS_CH6SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(6) +#define DMA_CHSREQSTATUS_CH5SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(5) +#define DMA_CHSREQSTATUS_CH4SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(4) +#define DMA_CHSREQSTATUS_CH3SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(3) +#define DMA_CHSREQSTATUS_CH2SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(2) +#define DMA_CHSREQSTATUS_CH1SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(1) +#define DMA_CHSREQSTATUS_CH0SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(0) + +/* DMA_IF */ +#define DMA_IF_ERR (1UL << 31) +#define DMA_IF_CHxDONE(x) (1 << (x)) +#define DMA_IF_CH11DONE DMA_IF_CHxDONE(11) +#define DMA_IF_CH10DONE DMA_IF_CHxDONE(10) +#define DMA_IF_CH9DONE DMA_IF_CHxDONE(9) +#define DMA_IF_CH8DONE DMA_IF_CHxDONE(8) +#define DMA_IF_CH7DONE DMA_IF_CHxDONE(7) +#define DMA_IF_CH6DONE DMA_IF_CHxDONE(6) +#define DMA_IF_CH5DONE DMA_IF_CHxDONE(5) +#define DMA_IF_CH4DONE DMA_IF_CHxDONE(4) +#define DMA_IF_CH3DONE DMA_IF_CHxDONE(3) +#define DMA_IF_CH2DONE DMA_IF_CHxDONE(2) +#define DMA_IF_CH1DONE DMA_IF_CHxDONE(1) +#define DMA_IF_CH0DONE DMA_IF_CHxDONE(0) + + +/* DMA_IFS */ +#define DMA_IFS_ERR (1 << 31) +#define DMA_IFS_CHxDONE(x) (1 << (x)) +#define DMA_IFS_CH11DONE DMA_IFS_CHxDONE(11) +#define DMA_IFS_CH10DONE DMA_IFS_CHxDONE(10) +#define DMA_IFS_CH9DONE DMA_IFS_CHxDONE(9) +#define DMA_IFS_CH8DONE DMA_IFS_CHxDONE(8) +#define DMA_IFS_CH7DONE DMA_IFS_CHxDONE(7) +#define DMA_IFS_CH6DONE DMA_IFS_CHxDONE(6) +#define DMA_IFS_CH5DONE DMA_IFS_CHxDONE(5) +#define DMA_IFS_CH4DONE DMA_IFS_CHxDONE(4) +#define DMA_IFS_CH3DONE DMA_IFS_CHxDONE(3) +#define DMA_IFS_CH2DONE DMA_IFS_CHxDONE(2) +#define DMA_IFS_CH1DONE DMA_IFS_CHxDONE(1) +#define DMA_IFS_CH0DONE DMA_IFS_CHxDONE(0) + +/* DMA_IFC */ +#define DMA_IFC_ERR (1 << 31) +#define DMA_IFC_CHxDONE(x) (1 << (x)) +#define DMA_IFC_CH11DONE DMA_IFC_CHxDONE(11) +#define DMA_IFC_CH10DONE DMA_IFC_CHxDONE(10) +#define DMA_IFC_CH9DONE DMA_IFC_CHxDONE(9) +#define DMA_IFC_CH8DONE DMA_IFC_CHxDONE(8) +#define DMA_IFC_CH7DONE DMA_IFC_CHxDONE(7) +#define DMA_IFC_CH6DONE DMA_IFC_CHxDONE(6) +#define DMA_IFC_CH5DONE DMA_IFC_CHxDONE(5) +#define DMA_IFC_CH4DONE DMA_IFC_CHxDONE(4) +#define DMA_IFC_CH3DONE DMA_IFC_CHxDONE(3) +#define DMA_IFC_CH2DONE DMA_IFC_CHxDONE(2) +#define DMA_IFC_CH1DONE DMA_IFC_CHxDONE(1) +#define DMA_IFC_CH0DONE DMA_IFC_CHxDONE(0) + +/* DMA_IEN */ +#define DMA_IEN_ERR (1 << 31) +#define DMA_IEN_CHxDONE(x) (1 << (x)) +#define DMA_IEN_CH11DONE DMA_IEN_CHxDONE(11) +#define DMA_IEN_CH10DONE DMA_IEN_CHxDONE(10) +#define DMA_IEN_CH9DONE DMA_IEN_CHxDONE(9) +#define DMA_IEN_CH8DONE DMA_IEN_CHxDONE(8) +#define DMA_IEN_CH7DONE DMA_IEN_CHxDONE(7) +#define DMA_IEN_CH6DONE DMA_IEN_CHxDONE(6) +#define DMA_IEN_CH5DONE DMA_IEN_CHxDONE(5) +#define DMA_IEN_CH4DONE DMA_IEN_CHxDONE(4) +#define DMA_IEN_CH3DONE DMA_IEN_CHxDONE(3) +#define DMA_IEN_CH2DONE DMA_IEN_CHxDONE(2) +#define DMA_IEN_CH1DONE DMA_IEN_CHxDONE(1) +#define DMA_IEN_CH0DONE DMA_IEN_CHxDONE(0) + +/* DMA_CTRL */ +#define DMA_CTRL_PRDU (1 << 1) +#define DMA_CTRL_DESCRECT (1 << 0) + +/* DMA_RDS */ +#define DMA_RDS_RDSCHx(i) (1 << (i)) +#define DMA_RDS_RDSCH11 DMA_RDS_RDSCHx(11) +#define DMA_RDS_RDSCH10 DMA_RDS_RDSCHx(10) +#define DMA_RDS_RDSCH9 DMA_RDS_RDSCHx(9) +#define DMA_RDS_RDSCH8 DMA_RDS_RDSCHx(8) +#define DMA_RDS_RDSCH7 DMA_RDS_RDSCHx(7) +#define DMA_RDS_RDSCH6 DMA_RDS_RDSCHx(6) +#define DMA_RDS_RDSCH5 DMA_RDS_RDSCHx(5) +#define DMA_RDS_RDSCH4 DMA_RDS_RDSCHx(4) +#define DMA_RDS_RDSCH3 DMA_RDS_RDSCHx(3) +#define DMA_RDS_RDSCH2 DMA_RDS_RDSCHx(2) +#define DMA_RDS_RDSCH1 DMA_RDS_RDSCHx(1) +#define DMA_RDS_RDSCH0 DMA_RDS_RDSCHx(0) + +/* DMA_LOOP */ +#define DMA_LOOP_EN (1 << 16) +#define DMA_LOOP_WIDTH_SHIFT (0) +#define DMA_LOOP_WIDTH_MASK (0x3FF << DMA_LOOP_WIDTH_SHIFT) +#define DMA_LOOP_WIDTH(v) \ + (((v) << DMA_LOOP_WIDTH_SHIFT) & DMA_LOOP_WIDTH_MASK) + +/* DMA_RECT */ +#define DMA_RECT_DSTSTRIDE_SHIFT (21) +#define DMA_RECT_DSTSTRIDE_MASK (0x7FF << DMA_RECT_DSTSTRIDE_SHIFT) +#define DMA_RECT_DSTSTRIDE(v) \ + (((v) << DMA_RECT_DSTSTRIDE_SHIFT) & DMA_RECT_DSTSTRIDE_MASK) + +#define DMA_RECT_SRCSTRIDE_SHIFT (10) +#define DMA_RECT_SRCSTRIDE_MASK (0x7FF << DMA_RECT_SRCSTRIDE_SHIFT) +#define DMA_RECT_SRCSTRIDE(v) \ + (((v) << DMA_RECT_SRCSTRIDE_SHIFT) & DMA_RECT_SRCSTRIDE_MASK) + +#define DMA_RECT_HEIGHT_SHIFT (0) +#define DMA_RECT_HEIGHT_MASK (0x3FF << DMA_RECT_HEIGHT_SHIFT) +#define DMA_RECT_HEIGHT(v) \ + (((v) << DMA_RECT_HEIGHT_SHIFT) & DMA_RECT_HEIGHT_MASK) + +/* DMA_CH_CTRL */ +#define DMA_CH_CTRL_SOURCESEL_SHIFT (16) +#define DMA_CH_CTRL_SOURCESEL_MASK (0x3F << DMA_CH_CTRL_SOURCESEL_SHIFT) +#define DMA_CH_CTRL_SOURCESEL(v) \ + (((v) << DMA_CH_CTRL_SOURCESEL_SHIFT) & DMA_CH_CTRL_SOURCESEL_MASK) +#define DMA_CH_CTRL_SOURCESEL_NONE 0b000000 +#define DMA_CH_CTRL_SOURCESEL_ADC0 0b001000 +#define DMA_CH_CTRL_SOURCESEL_DAC0 0b001010 +#define DMA_CH_CTRL_SOURCESEL_USART0 0b001100 +#define DMA_CH_CTRL_SOURCESEL_USART1 0b001101 +#define DMA_CH_CTRL_SOURCESEL_USART2 0b001110 +#define DMA_CH_CTRL_SOURCESEL_LEUART0 0b010000 +#define DMA_CH_CTRL_SOURCESEL_LEUART1 0b010001 +#define DMA_CH_CTRL_SOURCESEL_I2C0 0b010100 +#define DMA_CH_CTRL_SOURCESEL_I2C1 0b010101 +#define DMA_CH_CTRL_SOURCESEL_TIMER0 0b011000 +#define DMA_CH_CTRL_SOURCESEL_TIMER1 0b011001 +#define DMA_CH_CTRL_SOURCESEL_TIMER2 0b011010 +#define DMA_CH_CTRL_SOURCESEL_TIMER3 0b011011 +#define DMA_CH_CTRL_SOURCESEL_UART0 0b101100 +#define DMA_CH_CTRL_SOURCESEL_UART1 0b101101 +#define DMA_CH_CTRL_SOURCESEL_MSC 0b110000 +#define DMA_CH_CTRL_SOURCESEL_AES 0b110001 +#define DMA_CH_CTRL_SOURCESEL_LESENSE 0b110010 +#define DMA_CH_CTRL_SOURCESEL_EBI 0b110011 + +#define DMA_CH_CTRL_SIGSEL_SHIFT (0) +#define DMA_CH_CTRL_SIGSEL_MASK (0xF << DMA_CH_CTRL_SIGSEL_SHIFT) +#define DMA_CH_CTRL_SIGSEL(v) \ + (((v) << DMA_CH_CTRL_SIGSEL_SHIFT) & DMA_CH_CTRL_SIGSEL_MASK) + +#define DMA_CH_CTRL_SIGSEL_OFF 0 +#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0 +#define DMA_CH_CTRL_SIGSEL_ADC0SCAN 1 +#define DMA_CH_CTRL_SIGSEL_DAC0CH0 0 +#define DMA_CH_CTRL_SIGSEL_DAC0CH1 1 +#define DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0 +#define DMA_CH_CTRL_SIGSEL_USART0TXBL 1 +#define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 2 +#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0 +#define DMA_CH_CTRL_SIGSEL_USART1TXBL 1 +#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 2 +#define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 3 +#define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 4 +#define DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0 +#define DMA_CH_CTRL_SIGSEL_USART2TXBL 1 +#define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 2 +#define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 3 +#define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 4 +#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0 +#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL 1 +#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 2 +#define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0 +#define DMA_CH_CTRL_SIGSEL_LEUART1TXBL 1 +#define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 2 +#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0 +#define DMA_CH_CTRL_SIGSEL_I2C0TXBL 1 +#define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0 +#define DMA_CH_CTRL_SIGSEL_I2C1TXBL 1 +#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0 +#define DMA_CH_CTRL_SIGSEL_TIMER0CC0 1 +#define DMA_CH_CTRL_SIGSEL_TIMER0CC1 2 +#define DMA_CH_CTRL_SIGSEL_TIMER0CC2 3 +#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0 +#define DMA_CH_CTRL_SIGSEL_TIMER1CC0 1 +#define DMA_CH_CTRL_SIGSEL_TIMER1CC1 2 +#define DMA_CH_CTRL_SIGSEL_TIMER1CC2 3 +#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0 +#define DMA_CH_CTRL_SIGSEL_TIMER2CC0 1 +#define DMA_CH_CTRL_SIGSEL_TIMER2CC1 2 +#define DMA_CH_CTRL_SIGSEL_TIMER2CC2 3 +#define DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0 +#define DMA_CH_CTRL_SIGSEL_TIMER3CC0 1 +#define DMA_CH_CTRL_SIGSEL_TIMER3CC1 2 +#define DMA_CH_CTRL_SIGSEL_TIMER3CC2 3 +#define DMA_CH_CTRL_SIGSEL_UART0RXDATAV 0 +#define DMA_CH_CTRL_SIGSEL_UART0TXBL 1 +#define DMA_CH_CTRL_SIGSEL_UART0TXEMPTY 2 +#define DMA_CH_CTRL_SIGSEL_UART1RXDATAV 0 +#define DMA_CH_CTRL_SIGSEL_UART1TXBL 1 +#define DMA_CH_CTRL_SIGSEL_UART1TXEMPTY 2 +#define DMA_CH_CTRL_SIGSEL_MSCWDATA 0 +#define DMA_CH_CTRL_SIGSEL_AESDATAWR 0 +#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR 1 +#define DMA_CH_CTRL_SIGSEL_AESDATARD 2 +#define DMA_CH_CTRL_SIGSEL_AESKEYWR 3 +#define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0 +#define DMA_CH_CTRL_SIGSEL_EBIPXL0EMPTY 0 +#define DMA_CH_CTRL_SIGSEL_EBIPXL1EMPTY 1 +#define DMA_CH_CTRL_SIGSEL_EBIPXLFULL 2 +#define DMA_CH_CTRL_SIGSEL_EBIDDEMPTY 3 + +/* generic of above */ +#define DMA_CH_CTRL_SIGSEL_ADC_SINGLE 0 +#define DMA_CH_CTRL_SIGSEL_ADC_SCAN 1 +#define DMA_CH_CTRL_SIGSEL_DAC_CHx(x) DMA_CH_CTRL_SIGSEL(x) +#define DMA_CH_CTRL_SIGSEL_DAC_CH0 0 +#define DMA_CH_CTRL_SIGSEL_DAC_CH1 1 +#define DMA_CH_CTRL_SIGSEL_USART_RXDATAV 0 +#define DMA_CH_CTRL_SIGSEL_USART_TXBL 1 +#define DMA_CH_CTRL_SIGSEL_USART_TXEMPTY 2 +#define DMA_CH_CTRL_SIGSEL_USART_RXDATAVRIGHT 3 +#define DMA_CH_CTRL_SIGSEL_USART_TXBLRIGHT 4 +#define DMA_CH_CTRL_SIGSEL_LEUART_RXDATAV 0 +#define DMA_CH_CTRL_SIGSEL_LEUART_TXBL 1 +#define DMA_CH_CTRL_SIGSEL_LEUART_TXEMPTY 2 +#define DMA_CH_CTRL_SIGSEL_I2C_RXDATAV 0 +#define DMA_CH_CTRL_SIGSEL_I2C_TXBL 1 +#define DMA_CH_CTRL_SIGSEL_I2C_RXDATAV 0 +#define DMA_CH_CTRL_SIGSEL_I2C_TXBL 1 +#define DMA_CH_CTRL_SIGSEL_TIMER_UFOF 0 +#define DMA_CH_CTRL_SIGSEL_TIMER_CCx(x) DMA_CH_CTRL_SIGSEL((x) + 1) +#define DMA_CH_CTRL_SIGSEL_TIMER_CC0 DMA_CH_CTRL_SIGSEL_TIMER_CCx(0) +#define DMA_CH_CTRL_SIGSEL_TIMER_CC1 DMA_CH_CTRL_SIGSEL_TIMER_CCx(1) +#define DMA_CH_CTRL_SIGSEL_TIMER_CC2 DMA_CH_CTRL_SIGSEL_TIMER_CCx(3) +#define DMA_CH_CTRL_SIGSEL_UART_RXDATAV 0 +#define DMA_CH_CTRL_SIGSEL_UART_TXBL 1 +#define DMA_CH_CTRL_SIGSEL_UART_TXEMPTY 2 +#define DMA_CH_CTRL_SIGSEL_MSC_WDATA 0 +#define DMA_CH_CTRL_SIGSEL_AES_DATA_WR 0 +#define DMA_CH_CTRL_SIGSEL_AES_XOR_DATA_WR 1 +#define DMA_CH_CTRL_SIGSEL_AES_DATA_RD 2 +#define DMA_CH_CTRL_SIGSEL_AES_KEY_WR 3 +#define DMA_CH_CTRL_SIGSEL_LESENSE_BUF_DATAV 0 +#define DMA_CH_CTRL_SIGSEL_EBI_PXLx_EMPTY(x) DMA_CH_CTRL_SIGSEL(x) +#define DMA_CH_CTRL_SIGSEL_EBI_PXL0_EMPTY \ + 0 +#define DMA_CH_CTRL_SIGSEL_EBI_PXL1_EMPTY \ + 1 +#define DMA_CH_CTRL_SIGSEL_EBI_PXL_FULL 2 +#define DMA_CH_CTRL_SIGSEL_EBI_DD_EMPTY 3 + +/** + * Application needs to allocate (DMA_DESC_CH_SIZE * N) byte + * where N is the number of first N channels to use. + * and this allocated memory needs to be assigned to DMA using + * dma_set_desc_address(). + * + * if the application code needs alternate descriptor facility also. + * it needs to allocate the required memory (usually equal to the one above) + * and assign the memory using dma_set_alternate_desc_address() + * + * rest of the work will be transparently managed by convience functions. + * + * all the memory above should be aligned to 256bit + * (ie LSB 8bits of array address should be 0) + * use gcc's __attribute__((aligned(256))) + */ +#define DMA_DESC_CH_SIZE (0x4 * 0x4) +#define DMA_DESC_CHx_BASE(base, x) \ + ((base) + ((x) * DMA_DESC_CH_SIZE)) +#define DMA_DESC_CHx_SRC_DATA_END_PTR(base, x) \ + MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x00) +#define DMA_DESC_CHx_DEST_DATA_END_PTR(base, x) \ + MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x04) +#define DMA_DESC_CHx_CFG(base, x) \ + MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x08) +#define DMA_DESC_CHx_USER_DATA(base, x) \ + MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x0C) + +/* DMA_DESC_CH_CFG */ +#define DMA_DESC_CH_CFG_DEST_INC_SHIFT (30) +#define DMA_DESC_CH_CFG_DEST_INC_MASK \ + (0x3 << DMA_DESC_CH_CFG_DEST_INC_SHIFT) +#define DMA_DESC_CH_CFG_DEST_INC(v) \ + (((v) << DMA_DESC_CH_CFG_DEST_INC_SHIFT) & \ + DMA_DESC_CH_CFG_DEST_INC_MASK) +#define DMA_DESC_CH_CFG_DEST_INC_BYTE DMA_DESC_CH_CFG_DEST_INC(0) +#define DMA_DESC_CH_CFG_DEST_INC_HALFWORD DMA_DESC_CH_CFG_DEST_INC(1) +#define DMA_DESC_CH_CFG_DEST_INC_WORD DMA_DESC_CH_CFG_DEST_INC(2) +#define DMA_DESC_CH_CFG_DEST_INC_NOINC DMA_DESC_CH_CFG_DEST_INC(3) + +#define DMA_DESC_CH_CFG_DEST_SIZE_SHIFT (28) +#define DMA_DESC_CH_CFG_DEST_SIZE_MASK \ + (0x3 << DMA_DESC_CH_CFG_DEST_SIZE_SHIFT) +#define DMA_DESC_CH_CFG_DEST_SIZE(v) \ + (((v) << DMA_DESC_CH_CFG_DEST_SIZE_SHIFT) & \ + DMA_DESC_CH_CFG_DEST_SIZE_MASK) +#define DMA_DESC_CH_CFG_DEST_SIZE_BYTE DMA_DESC_CH_CFG_DEST_SIZE(0) +#define DMA_DESC_CH_CFG_DEST_SIZE_HALFWORD DMA_DESC_CH_CFG_DEST_SIZE(1) +#define DMA_DESC_CH_CFG_DEST_SIZE_WORD DMA_DESC_CH_CFG_DEST_SIZE(2) +#define DMA_DESC_CH_CFG_DEST_SIZE_NOINC DMA_DESC_CH_CFG_DEST_SIZE(3) + +#define DMA_DESC_CH_CFG_SRC_INC_SHIFT (26) +#define DMA_DESC_CH_CFG_SRC_INC_MASK \ + (0x3 << DMA_DESC_CH_CFG_SRC_INC_SHIFT) +#define DMA_DESC_CH_CFG_SRC_INC(v) \ + (((v) << DMA_DESC_CH_CFG_SRC_INC_SHIFT) & \ + DMA_DESC_CH_CFG_SRC_INC_MASK) +#define DMA_DESC_CH_CFG_SRC_INC_BYTE DMA_DESC_CH_CFG_SRC_INC(0) +#define DMA_DESC_CH_CFG_SRC_INC_HALFWORD DMA_DESC_CH_CFG_SRC_INC(1) +#define DMA_DESC_CH_CFG_SRC_INC_WORD DMA_DESC_CH_CFG_SRC_INC(2) +#define DMA_DESC_CH_CFG_SRC_INC_NOINC DMA_DESC_CH_CFG_SRC_INC(3) + +#define DMA_DESC_CH_CFG_SRC_SIZE_SHIFT (24) +#define DMA_DESC_CH_CFG_SRC_SIZE_MASK \ + (0x3 << DMA_DESC_CH_CFG_SRC_SIZE_SHIFT) +#define DMA_DESC_CH_CFG_SRC_SIZE(v) \ + (((v) << DMA_DESC_CH_CFG_SRC_SIZE_SHIFT) & \ + DMA_DESC_CH_CFG_SRC_SIZE_MASK) +#define DMA_DESC_CH_CFG_SRC_SIZE_BYTE DMA_DESC_CH_CFG_SRC_SIZE(0) +#define DMA_DESC_CH_CFG_SRC_SIZE_HALFWORD DMA_DESC_CH_CFG_SRC_SIZE(1) +#define DMA_DESC_CH_CFG_SRC_SIZE_WORD DMA_DESC_CH_CFG_SRC_SIZE(2) +#define DMA_DESC_CH_CFG_SRC_SIZE_NOINC DMA_DESC_CH_CFG_SRC_SIZE(3) + +#define DMA_DESC_CH_CFG_R_POWER_SHIFT (14) +#define DMA_DESC_CH_CFG_R_POWER_MASK \ + (0xF << DMA_DESC_CH_CFG_R_POWER_SHIFT) +#define DMA_DESC_CH_CFG_R_POWER(v) \ + (((v) << DMA_DESC_CH_CFG_R_POWER_SHIFT) & \ + DMA_DESC_CH_CFG_R_POWER_MASK) + +#define DMA_DESC_CH_CFG_CYCLE_CTRL_SHIFT (0) +#define DMA_DESC_CH_CFG_CYCLE_CTRL_MASK \ + (0x7 << DMA_DESC_CH_CFG_CYCLE_CTRL_SHIFT) +#define DMA_DESC_CH_CFG_CYCLE_CTRL(v) \ + (((v) << DMA_DESC_CH_CFG_CYCLE_CTRL_SHIFT) & \ + DMA_DESC_CH_CFG_CYCLE_CTRL_MASK) +#define DMA_DESC_CH_CFG_CYCLE_CTRL_INVALD \ + DMA_DESC_CH_CFG_CYCLE_CTRL(0) +#define DMA_DESC_CH_CFG_CYCLE_CTRL_BASIC \ + DMA_DESC_CH_CFG_CYCLE_CTRL(1) +#define DMA_DESC_CH_CFG_CYCLE_CTRL_AUTOREQUEST \ + DMA_DESC_CH_CFG_CYCLE_CTRL(2) +#define DMA_DESC_CH_CFG_CYCLE_CTRL_PINGPONG \ + DMA_DESC_CH_CFG_CYCLE_CTRL(3) +#define DMA_DESC_CH_CFG_CYCLE_CTRL_MEM_SCAT_GATH_PRIM \ + DMA_DESC_CH_CFG_CYCLE_CTRL(4) +#define DMA_DESC_CH_CFG_CYCLE_CTRL_MEM_SCAT_GATH_ALT \ + DMA_DESC_CH_CFG_CYCLE_CTRL(5) +#define DMA_DESC_CH_CFG_CYCLE_CTRL_PERIPH_SCAT_GATH_PRIM \ + DMA_DESC_CH_CFG_CYCLE_CTRL(6) +#define DMA_DESC_CH_CFG_CYCLE_CTRL_PERIPH_SCAT_GATH_ALT \ + DMA_DESC_CH_CFG_CYCLE_CTRL(7) + +#define DMA_DESC_CH_CFG_DEST_PROT_CTRL_SHIFT (21) +#define DMA_DESC_CH_CFG_DEST_PROT_CTRL_MASK \ + (0x7 << DMA_DESC_CH_CFG_DEST_PROT_CTRL_SHIFT) +#define DMA_DESC_CH_CFG_DEST_PROT_CTRL(v) \ + (((v) << DMA_DESC_CH_CFG_DEST_PROT_CTRL_SHIFT) & \ + DMA_DESC_CH_CFG_DEST_PROT_CTRL_MASK) + +#define DMA_DESC_CH_CFG_SRC_PROT_CTRL_SHIFT (18) +#define DMA_DESC_CH_CFG_SRC_PROT_CTRL_MASK \ + (0x7 << DMA_DESC_CH_CFG_SRC_PROT_CTRL_SHIFT) +#define DMA_DESC_CH_CFG_SRC_PROT_CTRL(v) \ + (((v) << DMA_DESC_CH_CFG_SRC_PROT_CTRL_SHIFT) & \ + DMA_DESC_CH_CFG_SRC_PROT_CTRL_SHIFT) + +#define DMA_DESC_CH_CFG_N_MINUS_1_SHIFT (4) +#define DMA_DESC_CH_CFG_N_MINUS_1_MASK \ + (0x3FF << DMA_DESC_CH_CFG_N_MINUS_1_SHIFT) +#define DMA_DESC_CH_CFG_N_MINUS_1(v) \ + (((v) << DMA_DESC_CH_CFG_N_MINUS_1_SHIFT) & \ + DMA_DESC_CH_CFG_N_MINUS_1_MASK) + +#define DMA_DESC_CH_CFG_NEXT_USEBURST (1 << 3) + +/* DMA Channel Descriptor in structure style */ +struct dma_chan_desc { + uint32_t src_data_end_ptr; + uint32_t dst_data_end_ptr; + uint32_t cfg; + uint32_t user_data; +} __attribute__((packed)); + +/** @defgroup dma_ch DMA Channel Number +@ingroup dma_defines + +@{*/ +enum dma_ch { + DMA_CH0 = 0, + DMA_CH1, + DMA_CH2, + DMA_CH3, + DMA_CH4, + DMA_CH5, + DMA_CH6, + DMA_CH7, + DMA_CH8, + DMA_CH9, + DMA_CH10, + DMA_CH11 +}; +/**@}*/ + +/* API version for {src, dest} * {size, inc} */ +enum dma_mem { + DMA_MEM_BYTE = 0, + DMA_MEM_HALF_WORD, + DMA_MEM_WORD, + DMA_MEM_NONE +}; + +/* API version of DMA_DESC_CH_CFG_CYCLE_CTRL_* */ +enum dma_mode { + DMA_MODE_INVALID = 0, + DMA_MODE_BASIC, + DMA_MODE_AUTO_REQUEST, + DMA_MODE_PING_PONG, + DMA_MODE_MEM_SCAT_GATH_PRIM, + DMA_MODE_MEM_SCAT_GATH_ALT, + DMA_MODE_PERIPH_SCAT_GATH_PRIM, + DMA_MODE_PERIPH_SCAT_GATH_ALT, +}; + +/* API version of DMA_DESC_CH_CFG_R_POWER() */ +enum dma_r_power { + DMA_R_POWER_1 = 0, + DMA_R_POWER_2, + DMA_R_POWER_4, + DMA_R_POWER_8, + DMA_R_POWER_16, + DMA_R_POWER_32, + DMA_R_POWER_64, + DMA_R_POWER_128, + DMA_R_POWER_256, + DMA_R_POWER_512, + DMA_R_POWER_1024 +}; + +BEGIN_DECLS + +void dma_enable(void); +void dma_disable(void); + +bool dma_get_wait_on_request_flag(enum dma_ch ch); + +/*bool dma_get_wait_flag(enum dma_ch ch);*/ + +void dma_enable_with_unprivileged_access(void); +void dma_enable_with_privileged_access(void); + +void dma_set_desc_address(uint32_t desc_base); + +void dma_generate_software_request(enum dma_ch ch); + +void dma_enable_burst_only(enum dma_ch ch); +void dma_enable_single_and_burst(enum dma_ch ch); + +void dma_enable_periph_request(enum dma_ch ch); +void dma_disable_periph_request(enum dma_ch ch); + +void dma_enable_channel(enum dma_ch ch); +void dma_disable_channel(enum dma_ch ch); + +void dma_disable_alternate_structure(enum dma_ch ch); +void dma_enable_alternate_structure(enum dma_ch ch); + +void dma_enable_priority(enum dma_ch ch); +void dma_disable_priority(enum dma_ch ch); + +bool dma_get_bus_error_flag(void); +void dma_clear_bus_error_flag(void); + +bool dma_get_request_flag(enum dma_ch ch); + +/*bool dma_get_single_request_flag(enum dma_ch ch);*/ + +bool dma_get_bus_error_interrupt_flag(void); +bool dma_get_done_interrupt_flag(enum dma_ch ch); + +void dma_set_bus_error_interrupt_flag(void); +void dma_set_done_interrupt_flag(enum dma_ch ch); + +void dma_clear_bus_error_interrupt_flag(void); +void dma_clear_done_interrupt_flag(enum dma_ch ch); + +void dma_enable_bus_error_interrupt(void); +void dma_disable_bus_error_interrupt(void); +void dma_enable_done_interrupt(enum dma_ch ch); +void dma_disable_done_interrupt(enum dma_ch ch); + +/* TODO: DMA_CTRL, DMA_RDS, DMA_LOOP0, DMA_LOOP1, DMA_RECT0 */ + +void dma_set_source(enum dma_ch ch, uint32_t source); +void dma_set_signal(enum dma_ch ch, uint32_t signal); + +void dma_channel_reset(enum dma_ch ch); + +void dma_set_loop_count(enum dma_ch ch, uint16_t count); +void dma_enable_loop(enum dma_ch ch); +void dma_disable_loop(enum dma_ch ch); + +/* descriptor convient function. (prefix "dma_desc_") */ +void dma_desc_set_dest_size(uint32_t desc_base, enum dma_ch ch, + enum dma_mem size); +void dma_desc_set_dest_inc(uint32_t desc_base, enum dma_ch ch, + enum dma_mem inc); +void dma_desc_set_src_size(uint32_t desc_base, enum dma_ch ch, + enum dma_mem size); +void dma_desc_set_src_inc(uint32_t desc_base, enum dma_ch ch, + enum dma_mem inc); + +void dma_desc_set_r_power(uint32_t desc_base, enum dma_ch ch, + enum dma_r_power r_power); + +void dma_desc_enable_next_useburst(uint32_t desc_base, enum dma_ch ch); +void dma_desc_disable_next_useburst(uint32_t desc_base, enum dma_ch ch); + +void dma_desc_set_count(uint32_t desc_base, enum dma_ch ch, uint16_t count); + +void dma_desc_set_user_data(uint32_t desc_base, enum dma_ch ch, + uint32_t user_data); +uint32_t dma_desc_get_user_data(uint32_t desc_base, enum dma_ch ch); + +void dma_desc_set_src_address(uint32_t desc_base, enum dma_ch ch, + uint32_t src); +void dma_desc_set_dest_address(uint32_t desc_base, enum dma_ch ch, + uint32_t dest); + +void dma_desc_set_mode(uint32_t desc_base, enum dma_ch ch, enum dma_mode mode); + +/* based on descriptor convient, macro are passing + * {DMA_CTRLBASE, CTRL_ALTCTRLBASE} as per naming */ +#define dma_set_dest_size(ch, size) \ + dma_desc_set_dest_size(DMA_CTRLBASE, ch, size) +#define dma_set_dest_inc(ch, inc) \ + dma_desc_set_dest_inc(DMA_CTRLBASE, ch, inc) +#define dma_set_src_size(ch, size) \ + dma_desc_set_src_size(DMA_CTRLBASE, ch, size) +#define dma_set_src_inc(ch, inc) \ + dma_desc_set_src_inc(DMA_CTRLBASE, ch, inc) + +#define dma_set_alt_dest_size(ch, size) \ + dma_desc_set_dest_size(DMA_ALTCTRLBASE, ch, size) +#define dma_set_alt_dest_inc(ch, inc) \ + dma_desc_set_dest_inc(DMA_ALTCTRLBASE, ch, inc) +#define dma_set_alt_src_size(ch, size) \ + dma_desc_set_src_size(DMA_ALTCTRLBASE, ch, size) +#define dma_set_alt_src_inc(ch, inc) \ + dma_desc_set_src_inc(DMA_ALTCTRLBASE, ch, inc) + +#define dma_set_r_power(ch, r_power) \ + dma_desc_set_r_power(DMA_CTRLBASE, ch, r_power) +#define dma_set_alt_r_power(ch, r_power) \ + dma_desc_set_r_power(DMA_ALTCTRLBASE, ch, r_power) + +#define dma_enable_next_useburst(ch) \ + dma_desc_enable_next_useburst(DMA_CTRLBASE, ch) +#define dma_disable_next_useburst(ch) \ + dma_desc_disable_next_useburst(DMA_CTRLBASE, ch) +#define dma_enable_alt_next_useburst(ch) \ + dma_desc_enable_alt_next_useburst(DMA_CTRLBASE, ch) +#define dma_disable_alt_next_useburst(ch) \ + dma_desc_disable_alt_next_useburst(DMA_CTRLBASE, ch) + +#define dma_set_count(ch, count) \ + dma_desc_set_count(DMA_CTRLBASE, ch, count) +#define dma_set_alt_count(ch, count) \ + dma_desc_set_count(DMA_ALTCTRLBASE, ch, count) + +#define dma_set_user_data(ch, user_data) \ + dma_desc_set_user_data(DMA_CTRLBASE, ch, user_data) +#define dma_set_alt_user_data(ch, user_data) \ + dma_desc_set_user_data(DMA_ALTCTRLBASE, ch, user_data) + +#define dma_get_user_data(ch) \ + dma_desc_get_user_data(DMA_CTRLBASE, ch) +#define dma_get_alt_user_data(ch) \ + dma_desc_get_user_data(DMA_ALTCTRLBASE, ch) + +#define dma_set_src_address(ch, src) \ + dma_desc_set_src_address(DMA_CTRLBASE, ch, src) +#define dma_set_alt_src_address(ch, src) \ + dma_desc_set_src_address(DMA_ALTCTRLBASE, ch, src) +#define dma_set_dest_address(ch, dest) \ + dma_desc_set_dest_address(DMA_CTRLBASE, ch, dest) +#define dma_set_alt_dest_address(ch, dest) \ + dma_desc_set_dest_address(DMA_ALTCTRLBASE, ch, dest) + +#define dma_set_mode(ch, mode) \ + dma_desc_set_mode(DMA_CTRLBASE, ch, mode) +#define dma_set_alt_mode(ch, mode) \ + dma_desc_set_mode(DMA_ALTCTRLBASE, ch, mode) + +END_DECLS + +#endif + diff --git a/include/libopencm3/efm32/common/emu_common.h b/include/libopencm3/efm32/common/emu_common.h new file mode 100644 index 00000000..7d220c50 --- /dev/null +++ b/include/libopencm3/efm32/common/emu_common.h @@ -0,0 +1,189 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2015 Kuldeep Singh Dhaka + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_EFM32_EMU_H +#define LIBOPENCM3_EFM32_EMU_H + +#include +#include + +#define EMU_CTRL MMIO32(EMU_BASE + 0x000) +#define EMU_LOCK MMIO32(EMU_BASE + 0x008) +#define EMU_AUXCTRL MMIO32(EMU_BASE + 0x024) +#define EMU_EM4CONF MMIO32(EMU_BASE + 0x02C) +#define EMU_BUCTRL MMIO32(EMU_BASE + 0x030) +#define EMU_PWRCONF MMIO32(EMU_BASE + 0x034) +#define EMU_BUINACT MMIO32(EMU_BASE + 0x038) +#define EMU_BUACT MMIO32(EMU_BASE + 0x03C) +#define EMU_STATUS MMIO32(EMU_BASE + 0x040) +#define EMU_ROUTE MMIO32(EMU_BASE + 0x044) +#define EMU_IF MMIO32(EMU_BASE + 0x048) +#define EMU_IFS MMIO32(EMU_BASE + 0x04C) +#define EMU_IFC MMIO32(EMU_BASE + 0x050) +#define EMU_IEN MMIO32(EMU_BASE + 0x054) +#define EMU_BUBODBUVINCAL MMIO32(EMU_BASE + 0x058) +#define EMU_BUBODUNREGCAL MMIO32(EMU_BASE + 0x05C) + +/* EMU_CTRL */ +#define EMU_CTRL_EM4CTRL_SHIFT (2) +#define EMU_CTRL_EM4CTRL_MASK (0x3 << EMU_CTRL_EM4CTRL_SHIFT) +#define EMU_CTLR_EM4CTRL(v) \ + (((v) << EMU_CTRL_EM4CTRL_SHIFT) & EMU_CTRL_EM4CTRL_MASK) + +#define EMU_CTRL_EM2BLOCK (1 << 1) +#define EMU_CTRL_EMVREG (1 << 0) + +/* EMU_LOCK */ +#define EMU_LOCK_LOCKKEY_MASK (0xFFFF) +#define EMU_LOCK_LOCKKEY_LOCK (0) +#define EMU_LOCK_LOCKKEY_UNLOCK (0xADE8) + +/* EMU_AUXCTRL */ +#define EMU_AUXCTRL_HRCCLR (1 << 0) + +/* EMU_EM4CONF */ +#define EMU_EM4CONF_LOCKCONF (1 << 16) +#define EMU_EM4CONF_BUBODRSTDIS (1 << 4) + +#define EMU_EM4CONF_OSC_SHIFT (2) +#define EMU_EM4CONF_OSC_MASK (0x3 << EMU_EM4CONF_OSC_SHIFT) +#define EMU_EM4CONF_OSC(v) \ + (((v) << EMU_EM4CONF_OSC_SHIFT) & EMU_EM4CONF_OSC_MASK) +#define EMU_EM4CONF_OSC_ULFRCO 0 +#define EMU_EM4CONF_OSC_LFRCO 1 +#define EMU_EM4CONF_OSC_LFXO 2 + +#define EMU_EM4CONF_BURTCWU (1 << 1) +#define EMU_EM4CONF_VREGEN (1 << 0) + +/* EMU_BUCTRL */ +#define EMU_BUCTRL_PROBE_SHIFT (5) +#define EMU_BUCTRL_PROBE_MASK (0x3 << EMU_BUCTRL_PROBE_SHIFT) +#define EMU_BUCTRL_PROBE(v) \ + (((v) << EMU_BUCTRL_PROBE_SHIFT) & EMU_BUCTRL_PROBE_MASK) +#define EMU_BUCTRL_PROBE_DISABLE 0 +#define EMU_BUCTRL_PROBE_VDDDREG 1 +#define EMU_BUCTRL_PROBE_BUIN 2 +#define EMU_BUCTRL_PROBE_BUOUT 3 + +#define EMU_BUCTRL_BUMODEBODEN (1 << 3) +#define EMU_BUCTRL_BODCAL (1 << 2) +#define EMU_BUCTRL_STATEN (1 << 1) +#define EMU_BUCTRL_EN (1 << 0) + +/* EMU_PWRCONF */ +#define EMU_PWRCONF_PWRRES_SHIFT (3) +#define EMU_PWRCONF_PWRRES_MASK (0x3 << EMU_PWRCONF_PWRRES_SHIFT) +#define EMU_PWRCONF_PWRRES(v) \ + (((v) << EMU_PWRCONF_PWRRES_SHIFT) & EMU_PWRCONF_PWRRES_MASK) +#define EMU_PWRCONF_PWRRES_DISABLE 0 +#define EMU_PWRCONF_PWRRES_VDDDREG 1 +#define EMU_PWRCONF_PWRRES_BUIN 2 +#define EMU_PWRCONF_PWRRES_BUOUT 3 + +#define EMU_PWRCONF_VOUTSTRONG (1 << 2) +#define EMU_PWRCONF_VOUTMED (1 << 1) +#define EMU_PWRCONF_VOUTWEAK (1 << 0) + +/* EMU_BUINACT */ +#define EMU_BUINACT_PWRCON_SHIFT (5) +#define EMU_BUINACT_PWRCON_MASK (0x3 << EMU_BUINACT_PWRCON_SHIFT) +#define EMU_BUINACT_PWRCON(v) \ + (((v) << EMU_BUINACT_PWRCON_SHIFT) & EMU_BUINACT_PWRCON_MASK) +#define EMU_BUINACT_PWRCON_NONE 0 +#define EMU_BUINACT_PWRCON_BUMAIN 1 +#define EMU_BUINACT_PWRCON_MAINBU 2 +#define EMU_BUINACT_PWRCON_NODIODE 3 + +#define EMU_BUINACT_BUENRANGE_SHIFT (3) +#define EMU_BUINACT_BUENRANGE_MASK (0x3 << EMU_BUINACT_BUENRANGE_SHIFT) +#define EMU_BUINACT_BUENRANGE(v) \ + (((v) << EMU_BUINACT_BUENRANGE_SHIFT) & EMU_BUINACT_BUENRANGE_MASK) + +#define EMU_BUINACT_BUENTHRES_SHIFT (0) +#define EMU_BUINACT_BUENTHRES_MASK (0x7 << EMU_BUINACT_BUENTHRES_SHIFT) +#define EMU_BUINACT_BUENTHRES(v) \ + (((v) << EMU_BUINACT_BUENTHRES_SHIFT) & EMU_BUINACT_BUENTHRES_MASK) + +/* EMU_BUACT */ +#define EMU_BUACT_PWRCON_SHIFT (5) +#define EMU_BUACT_PWRCON_MASK (0x3 << EMU_BUACT_PWRCON_SHIFT) +#define EMU_BUACT_PWRCON(v) \ + (((v) << EMU_BUACT_PWRCON_SHIFT) & EMU_BUACT_PWRCON_MASK) +#define EMU_BUACT_PWRCON_NONE 0 +#define EMU_BUACT_PWRCON_BUMAIN 1 +#define EMU_BUACT_PWRCON_MAINBU 2 +#define EMU_BUACT_PWRCON_NODIODE 3 + +#define EMU_BUACT_BUEXRANGE_SHIFT (3) +#define EMU_BUACT_BUEXRANGE_MASK (0x3 << EMU_BUACT_BUEXRANGE_SHIFT) +#define EMU_BUACT_BUEXRANGE(v) \ + (((v) << EMU_BUACT_BUEXRANGE_SHIFT) & EMU_BUACT_BUEXRANGE_MASK) + +#define EMU_BUACT_BUEXTHRES_SHIFT (0) +#define EMU_BUACT_BUEXTHRES_MASK (0x7 << EMU_BUACT_BUEXTHRES_SHIFT) +#define EMU_BUACT_BUEXTHRES(v) \ + (((v) << EMU_BUACT_BUEXTHRES_SHIFT) & EMU_BUACT_BUEXTHRES_MASK) + +/* EMU_STATUS */ +#define EMU_STATUS_BURDY (1 << 0) + +/* EMU_ROUTE */ +#define EMU_ROUTE_BUVINPEN (1 << 0) + +/* EMU_IF */ +#define EMU_IF_BURDY (1 << 0) + +/* EMU_IFS */ +#define EMU_IFS_BURDY (1 << 0) + +/* EMU_IFC */ +#define EMU_IFC_BURDY (1 << 0) + +/* EMU_IEN */ +#define EMU_IEN_BURDY (1 << 0) + +/* EMU_BUBODBUVINCAL */ +#define EMU_BUBODBUVINCAL_RANGE_SHIFT (3) +#define EMU_BUBODBUVINCAL_RANGE_MASK (0x3 << EMU_BUBODBUVINCAL_RANGE_SHIFT) +#define EMU_BUBODBUVINCAL_RANGE(v) \ + (((v) << EMU_BUBODBUVINCAL_RANGE_SHIFT) & \ + EMU_BUBODBUVINCAL_RANGE_MASK) + +#define EMU_BUBODBUVINCAL_THRES_SHIFT (0) +#define EMU_BUBODBUVINCAL_THRES_MASK (0x7 << EMU_BUBODBUVINCAL_THRES_SHIFT) +#define EMU_BUBODBUVINCAL_THRES(v) \ + (((v) << EMU_BUBODBUVINCAL_THRES_SHIFT) & \ + EMU_BUBODBUVINCAL_THRES_MASK) + +/* EMU_BUBODUNREGCAL */ +#define EMU_BUBODUNREGCAL_RANGE_SHIFT (3) +#define EMU_BUBODUNREGCAL_RANGE_MASK (0x3 << EMU_BUBODUNREGCAL_RANGE_SHIFT) +#define EMU_BUBODUNREGCAL_RANGE(v) \ + (((v) << EMU_BUBODUNREGCAL_RANGE_SHIFT) & \ + EMU_BUBODUNREGCAL_RANGE_MASK) + +#define EMU_BUBODUNREGCAL_THRES_SHIFT (0) +#define EMU_BUBODUNREGCAL_THRES_MASK (0x7 << EMU_BUBODUNREGCAL_THRES_SHIFT) +#define EMU_BUBODUNREGCAL_THRES(v) \ + (((v) << EMU_BUBODUNREGCAL_THRES_SHIFT) & \ + EMU_BUBODUNREGCAL_THRES_MASK) + +#endif + diff --git a/include/libopencm3/efm32/common/gpio_common.h b/include/libopencm3/efm32/common/gpio_common.h new file mode 100644 index 00000000..d8bce510 --- /dev/null +++ b/include/libopencm3/efm32/common/gpio_common.h @@ -0,0 +1,330 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2015 Kuldeep Singh Dhaka + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_EFM32_GPIO_H +#define LIBOPENCM3_EFM32_GPIO_H + +#include +#include + +#define GPIO_P(i) (GPIO_BASE + (0x24 * (i))) +#define GPIO_PA GPIO_P(0) +#define GPIO_PB GPIO_P(1) +#define GPIO_PC GPIO_P(2) +#define GPIO_PD GPIO_P(3) +#define GPIO_PE GPIO_P(4) +#define GPIO_PF GPIO_P(5) + +#define GPIO_P_CTRL(port) MMIO32((port) + 0x00) +#define GPIO_PA_CTRL GPIO_P_CTRL(GPIO_PA) +#define GPIO_PB_CTRL GPIO_P_CTRL(GPIO_PB) +#define GPIO_PC_CTRL GPIO_P_CTRL(GPIO_PC) +#define GPIO_PD_CTRL GPIO_P_CTRL(GPIO_PD) +#define GPIO_PE_CTRL GPIO_P_CTRL(GPIO_PE) +#define GPIO_PF_CTRL GPIO_P_CTRL(GPIO_PF) + +#define GPIO_P_CTRL_DRIVEMODE_SHIFT (0) +#define GPIO_P_CTRL_DRIVEMODE_MASK (0x03 << GPIO_P_CTRL_DRIVEMODE_SHIFT) +#define GPIO_P_CTRL_DRIVEMODE(v) \ + (((v) << GPIO_P_CTRL_DRIVEMODE_SHIFT) & GPIO_P_CTRL_DRIVEMODE_MASK) +#define GPIO_P_CTRL_DRIVEMODE_STANDARD 0 +#define GPIO_P_CTRL_DRIVEMODE_LOWEST 1 +#define GPIO_P_CTRL_DRIVEMODE_HIGH 2 +#define GPIO_P_CTRL_DRIVEMODE_LOW 3 + +/* NOTE: GPIO_MODE and GPIO_MODE_MASK is generic. + * it is used with both GPIO_Px_MODEL and GPIO_Px_MODEH */ +#define GPIO_P_MODE_MODEx_MASK(x) (0x0F << (((x) & 0x7) * 4)) +/* for mode: use GPIO_MODE_* */ +#define GPIO_P_MODE_MODEx(x, mode) \ + (((mode) << (((x) & 0x7) * 4)) & GPIO_P_MODE_MODEx_MASK(x)) + +#define GPIO_P_MODEL(port) MMIO32((port) + 0x04) +#define GPIO_PA_MODEL GPIO_P_MODEL(GPIO_PA) +#define GPIO_PB_MODEL GPIO_P_MODEL(GPIO_PB) +#define GPIO_PC_MODEL GPIO_P_MODEL(GPIO_PC) +#define GPIO_PD_MODEL GPIO_P_MODEL(GPIO_PD) +#define GPIO_PE_MODEL GPIO_P_MODEL(GPIO_PE) + +#define GPIO_P_MODEL_MODEx_MASK(x) GPIO_P_MODE_MODEx_MASK(x) +#define GPIO_P_MODEL_MODEx(x, mode) GPIO_P_MODE_MODEx(x, mode) + +#define GPIO_P_MODEL_MODE0_MASK GPIO_P_MODEL_MODEx_MASK(0) +#define GPIO_P_MODEL_MODE0(mode) GPIO_P_MODEL_MODEx(0, mode) + +#define GPIO_P_MODEL_MODE1_MASK GPIO_P_MODEL_MODEx_MASK(1) +#define GPIO_P_MODEL_MODE1(mode) GPIO_P_MODEL_MODEx(1, mode) + +#define GPIO_P_MODEL_MODE2_MASK GPIO_P_MODEL_MODEx_MASK(2) +#define GPIO_P_MODEL_MODE2(mode) GPIO_P_MODEL_MODEx(2, mode) + +#define GPIO_P_MODEL_MODE3_MASK GPIO_P_MODEL_MODEx_MASK(3) +#define GPIO_P_MODEL_MODE3(mode) GPIO_P_MODEL_MODEx(3, mode) + +#define GPIO_P_MODEL_MODE4_MASK GPIO_P_MODEL_MODEx_MASK(4) +#define GPIO_P_MODEL_MODE4(mode) GPIO_P_MODEL_MODEx(4, mode) + +#define GPIO_P_MODEL_MODE5_MASK GPIO_P_MODEL_MODEx_MASK(5) +#define GPIO_P_MODEL_MODE5(mode) GPIO_P_MODEL_MODEx(5, mode) + +#define GPIO_P_MODEL_MODE6_MASK GPIO_P_MODEL_MODEx_MASK(6) +#define GPIO_P_MODEL_MODE6(mode) GPIO_P_MODEL_MODEx(6, mode) + +#define GPIO_P_MODEL_MODE7_MASK GPIO_P_MODEL_MODEx_MASK(7) +#define GPIO_P_MODEL_MODE7(mode) GPIO_P_MODEL_MODEx(7, mode) + +#define GPIO_P_MODEH(port) MMIO32((port) + 0x08) +#define GPIO_PA_MODEH GPIO_P_MODEH(GPIO_PA) +#define GPIO_PB_MODEH GPIO_P_MODEH(GPIO_PB) +#define GPIO_PC_MODEH GPIO_P_MODEH(GPIO_PC) +#define GPIO_PD_MODEH GPIO_P_MODEH(GPIO_PD) +#define GPIO_PE_MODEH GPIO_P_MODEH(GPIO_PE) + +/* note: (x - 8) is because for MODEH, MODE8 refers to offset 0 */ +#define GPIO_P_MODEH_MODEx_MASK(x) GPIO_P_MODE_MODEx_MASK((x) - 8) +#define GPIO_P_MODEH_MODEx(x, mode) GPIO_P_MODE_MODEx((x) - 8, mode) + +#define GPIO_P_MODEH_MODE8_MASK GPIO_P_MODEH_MODEx_MASK(8) +#define GPIO_P_MODEH_MODE8(mode) GPIO_P_MODEH_MODEx(8, mode) + +#define GPIO_P_MODEH_MODE9_MASK GPIO_P_MODEH_MODEx_MASK(9) +#define GPIO_P_MODEH_MODE9(mode) GPIO_P_MODEH_MODEx(9, mode) + +#define GPIO_P_MODEH_MODE10_MASK GPIO_P_MODEH_MODEx_MASK(10) +#define GPIO_P_MODEH_MODE10(mode) GPIO_P_MODEH_MODEx(10, mode) + +#define GPIO_P_MODEH_MODE11_MASK GPIO_P_MODEH_MODEx_MASK(11) +#define GPIO_P_MODEH_MODE11(mode) GPIO_P_MODEH_MODEx(11, mode) + +#define GPIO_P_MODEH_MODE12_MASK GPIO_P_MODEH_MODEx_MASK(12) +#define GPIO_P_MODEH_MODE12(mode) GPIO_P_MODEH_MODEx(12, mode) + +#define GPIO_P_MODEH_MODE13_MASK GPIO_P_MODEH_MODEx_MASK(13) +#define GPIO_P_MODEH_MODE13(mode) GPIO_P_MODEH_MODEx(13, mode) + +#define GPIO_P_MODEH_MODE14_MASK GPIO_P_MODEH_MODEx_MASK(14) +#define GPIO_P_MODEH_MODE14(mode) GPIO_P_MODEH_MODEx(14, mode) + +#define GPIO_P_MODEH_MODE15_MASK GPIO_P_MODEH_MODEx_MASK(15) +#define GPIO_P_MODEH_MODE15(mode) GPIO_P_MODEH_MODEx(15, mode) + +#define GPIO_P_DOUT(port) MMIO32((port) + 0x0C) +#define GPIO_PA_DOUT GPIO_P_DOUT(GPIO_PA) +#define GPIO_PB_DOUT GPIO_P_DOUT(GPIO_PB) +#define GPIO_PC_DOUT GPIO_P_DOUT(GPIO_PC) +#define GPIO_PD_DOUT GPIO_P_DOUT(GPIO_PD) +#define GPIO_PE_DOUT GPIO_P_DOUT(GPIO_PE) + +#define GPIO_P_DOUTSET(port) MMIO32((port) + 0x10) +#define GPIO_PA_DOUTSET GPIO_P_DOUTSET(GPIO_PA) +#define GPIO_PB_DOUTSET GPIO_P_DOUTSET(GPIO_PB) +#define GPIO_PC_DOUTSET GPIO_P_DOUTSET(GPIO_PC) +#define GPIO_PD_DOUTSET GPIO_P_DOUTSET(GPIO_PD) +#define GPIO_PE_DOUTSET GPIO_P_DOUTSET(GPIO_PE) + +#define GPIO_P_DOUTCLR(port) MMIO32((port) + 0x14) +#define GPIO_PA_DOUTCLR GPIO_P_DOUTCLR(GPIO_PA) +#define GPIO_PB_DOUTCLR GPIO_P_DOUTCLR(GPIO_PB) +#define GPIO_PC_DOUTCLR GPIO_P_DOUTCLR(GPIO_PC) +#define GPIO_PD_DOUTCLR GPIO_P_DOUTCLR(GPIO_PD) +#define GPIO_PE_DOUTCLR GPIO_P_DOUTCLR(GPIO_PE) + +#define GPIO_P_DOUTTGL(port) MMIO32((port) + 0x18) +#define GPIO_PA_DOUTTGL GPIO_P_DOUTTGL(GPIO_PA) +#define GPIO_PB_DOUTTGL GPIO_P_DOUTTGL(GPIO_PB) +#define GPIO_PC_DOUTTGL GPIO_P_DOUTTGL(GPIO_PC) +#define GPIO_PD_DOUTTGL GPIO_P_DOUTTGL(GPIO_PD) +#define GPIO_PE_DOUTTGL GPIO_P_DOUTTGL(GPIO_PE) + +#define GPIO_P_DIN(port) MMIO32((port) + 0x1C) +#define GPIO_PA_DIN GPIO_P_DIN(GPIO_PA) +#define GPIO_PB_DIN GPIO_P_DIN(GPIO_PB) +#define GPIO_PC_DIN GPIO_P_DIN(GPIO_PC) +#define GPIO_PD_DIN GPIO_P_DIN(GPIO_PD) +#define GPIO_PE_DIN GPIO_P_DIN(GPIO_PE) + +#define GPIO_P_PINLOCKN(port) MMIO32((port) + 0x20) +#define GPIO_PA_PINLOCKN GPIO_P_PINLOCKN(GPIO_PA) +#define GPIO_PB_PINLOCKN GPIO_P_PINLOCKN(GPIO_PB) +#define GPIO_PC_PINLOCKN GPIO_P_PINLOCKN(GPIO_PC) +#define GPIO_PD_PINLOCKN GPIO_P_PINLOCKN(GPIO_PD) +#define GPIO_PE_PINLOCKN GPIO_P_PINLOCKN(GPIO_PE) + +#define GPIO_EXTIPSELL MMIO32(GPIO_BASE + 0x100) +#define GPIO_EXTIPSELH MMIO32(GPIO_BASE + 0x104) +#define GPIO_EXTIRISE MMIO32(GPIO_BASE + 0x108) +#define GPIO_EXTIFALL MMIO32(GPIO_BASE + 0x10C) +#define GPIO_IEN MMIO32(GPIO_BASE + 0x110) +#define GPIO_IF MMIO32(GPIO_BASE + 0x114) +#define GPIO_IFS MMIO32(GPIO_BASE + 0x118) +#define GPIO_IFC MMIO32(GPIO_BASE + 0x11C) +#define GPIO_ROUTE MMIO32(GPIO_BASE + 0x120) +#define GPIO_INSENSE MMIO32(GPIO_BASE + 0x124) +#define GPIO_LOCK MMIO32(GPIO_BASE + 0x128) +#define GPIO_CTRL MMIO32(GPIO_BASE + 0x12C) +#define GPIO_CMD MMIO32(GPIO_BASE + 0x130) +#define GPIO_EM4WUEN MMIO32(GPIO_BASE + 0x134) +#define GPIO_EM4WUPOL MMIO32(GPIO_BASE + 0x138) +#define GPIO_EM4WUCAUSE MMIO32(GPIO_BASE + 0x13C) + +/* mask is performed so that can be used with L and H */ +#define GPIO_EXTIPSEL_MASK(n) (0x7 << ((n) & 0xF)) +#define GPIO_EXTIPSEL_PORTMASK(n, v) ((v) << ((n) & 0xF)) +#define GPIO_EXTIPSEL_PORTA 0x0 +#define GPIO_EXTIPSEL_PORTB 0x1 +#define GPIO_EXTIPSEL_PORTC 0x2 +#define GPIO_EXTIPSEL_PORTD 0x3 +#define GPIO_EXTIPSEL_PORTE 0x4 +#define GPIO_EXTIPSEL_PORTF 0x5 + +#define GPIO_ROUTE_SWCLKPEN (1 << 0) +#define GPIO_ROUTE_SWDIOPEN (1 << 1) +#define GPIO_ROUTE_SWOPEN (1 << 3) + +#define GPIO_ROUTE_SWLOCATION_SHIFT (8) +#define GPIO_ROUTE_SWLOCATION_MASK (0x3 << GPIO_ROUTE_SWLOCATION_SHIFT) +#define GPIO_ROUTE_SWLOCATION(v) \ + (((v) << GPIO_ROUTE_SWLOCATION_SHIFT) & GPIO_ROUTE_SWLOCATION_MASK) + +#define GPIO_ROUTE_TCLKPEN (1 << 12) +#define GPIO_ROUTE_TD0PEN (1 << 13) +#define GPIO_ROUTE_TD1PEN (1 << 14) +#define GPIO_ROUTE_TD2PEN (1 << 15) +#define GPIO_ROUTE_TD3PEN (1 << 16) + +#define GPIO_ROUTE_ETMLOCATION_SHIFT (24) +#define GPIO_ROUTE_ETMLOCATION_MASK (0x3 << GPIO_ROUTE_ETMLOCATION_SHIFT) +#define GPIO_ROUTE_ETMLOCATION(v) \ + (((v) << GPIO_ROUTE_ETMLOCATION_SHIFT) & GPIO_ROUTE_ETMLOCATION_MASK) +#define GPIO_ROUTE_ETMLOCATION_LOCx(x) GPIO_ROUTE_ETMLOCATION(x) +#define GPIO_ROUTE_ETMLOCATION_LOC0 0 +#define GPIO_ROUTE_ETMLOCATION_LOC1 1 +#define GPIO_ROUTE_ETMLOCATION_LOC2 2 +#define GPIO_ROUTE_ETMLOCATION_LOC3 3 + +#define GPIO_INSENSE_INT (1 << 0) +#define GPIO_INSENSE_PRS (1 << 1) + +#define GPIO_LOCK_LOCKKEY_SHIFT (0) +#define GPIO_LOCK_LOCKKEY_MASK (0xFFFF << GPIO_LOCK_LOCKKEY_SHIFT) +#define GPIO_LOCK_LOCKKEY_UNLOCKED (0x0000 << GPIO_LOCK_LOCKKEY_SHIFT) +#define GPIO_LOCK_LOCKKEY_LOCKED (0x0001 << GPIO_LOCK_LOCKKEY_SHIFT) +#define GPIO_LOCK_LOCKKEY_LOCK (0x0000 << GPIO_LOCK_LOCKKEY_SHIFT) +#define GPIO_LOCK_LOCKKEY_UNLOCK (0xA534 << GPIO_LOCK_LOCKKEY_SHIFT) + +#define GPIO_CTRL_EM4RET (1 << 0) + +#define GPIO_CMD_EM4WUCLR (1 << 0) + +#define GPIO_EM4WUEN_EM4WUEN_A0 (1 << 0) +#define GPIO_EM4WUEN_EM4WUEN_A6 (1 << 1) +#define GPIO_EM4WUEN_EM4WUEN_C9 (1 << 2) +#define GPIO_EM4WUEN_EM4WUEN_F1 (1 << 3) +#define GPIO_EM4WUEN_EM4WUEN_F2 (1 << 4) +#define GPIO_EM4WUEN_EM4WUEN_E13 (1 << 5) + +#define GPIO_EM4WUPOL_EM4WUPOL_A0 (1 << 0) +#define GPIO_EM4WUPOL_EM4WUPOL_A6 (1 << 1) +#define GPIO_EM4WUPOL_EM4WUPOL_C9 (1 << 2) +#define GPIO_EM4WUPOL_EM4WUPOL_F1 (1 << 3) +#define GPIO_EM4WUPOL_EM4WUPOL_F2 (1 << 4) +#define GPIO_EM4WUPOL_EM4WUPOL_E13 (1 << 5) + +#define GPIO0 (1 << 0) +#define GPIO1 (1 << 1) +#define GPIO2 (1 << 2) +#define GPIO3 (1 << 3) +#define GPIO4 (1 << 4) +#define GPIO5 (1 << 5) +#define GPIO6 (1 << 6) +#define GPIO7 (1 << 7) +#define GPIO8 (1 << 8) +#define GPIO9 (1 << 9) +#define GPIO10 (1 << 10) +#define GPIO11 (1 << 11) +#define GPIO12 (1 << 12) +#define GPIO13 (1 << 13) +#define GPIO14 (1 << 14) +#define GPIO15 (1 << 15) +#define GPIO_ALL (0xFFFF) + +/* These are the acceptable mode values. + * (+ readable counterparts) + * do not confuse GPIO_MODE_* for GPIO_P_MODE_MODEx. + */ +enum gpio_mode { + GPIO_MODE_DISABLE = 0, + GPIO_MODE_INPUT, + GPIO_MODE_INPUT_PULL, + GPIO_MODE_INPUT_PULL_FILTER, + GPIO_MODE_PUSH_PULL, + GPIO_MODE_PUSH_PULL_DRIVE, + GPIO_MODE_WIRED_OR, + GPIO_MODE_WIRED_OR_PULL_DOWN, + GPIO_MODE_WIRED_AND, + GPIO_MODE_WIRED_AND_FILTER, + GPIO_MODE_WIRED_AND_PULLUP, + GPIO_MODE_WIRED_AND_PULLUP_FILTER, + GPIO_MODE_WIRED_AND_DRIVE, + GPIO_MODE_WIRED_AND_DRIVE_FILTER, + GPIO_MODE_WIRED_AND_DRIVE_PULLUP, + GPIO_MODE_WIRED_AND_DRIVE_PULLUP_FILTER +}; + +/* for readability. */ +enum gpio_drive_strength { + GPIO_STRENGTH_STANDARD = 0, + GPIO_STRENGTH_LOWEST, + GPIO_STRENGTH_HIGH, + GPIO_STRENGTH_LOW +}; + +/* for readability */ +#define GPIOA GPIO_PA +#define GPIOB GPIO_PB +#define GPIOC GPIO_PC +#define GPIOD GPIO_PD +#define GPIOE GPIO_PE +#define GPIOF GPIO_PF + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void gpio_enable_lock(void); +void gpio_disable_lock(void); +bool gpio_get_lock_flag(void); + +void gpio_set_drive_strength(uint32_t gpio_port, + enum gpio_drive_strength driver_stength); +void gpio_mode_setup(uint32_t gpio_port, enum gpio_mode mode, uint16_t gpios); + +void gpio_set(uint32_t gpio_port, uint16_t gpios); +void gpio_clear(uint32_t gpio_port, uint16_t gpios); +uint16_t gpio_get(uint32_t gpio_port, uint16_t gpios); +void gpio_toggle(uint32_t gpio_port, uint16_t gpios); +uint16_t gpio_port_read(uint32_t gpio_port); +void gpio_port_write(uint32_t gpio_port, uint16_t data); + +void gpio_port_config_lock(uint32_t gpio_port, uint16_t gpios); + +END_DECLS + +#endif + diff --git a/include/libopencm3/efm32/common/i2c_common.h b/include/libopencm3/efm32/common/i2c_common.h new file mode 100644 index 00000000..92f9d737 --- /dev/null +++ b/include/libopencm3/efm32/common/i2c_common.h @@ -0,0 +1,269 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2015 Kuldeep Singh Dhaka + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_EFM32_I2C_H +#define LIBOPENCM3_EFM32_I2C_H + +#include +#include + +#define I2C_CTRL(base) MMIO32((base) + 0x000) +#define I2C_CMD(base) MMIO32((base) + 0x004) +#define I2C_STATE(base) MMIO32((base) + 0x008) +#define I2C_STATUS(base) MMIO32((base) + 0x00C) +#define I2C_CLKDIV(base) MMIO32((base) + 0x010) +#define I2C_SADDR(base) MMIO32((base) + 0x014) +#define I2C_SADDRMASK(base) MMIO32((base) + 0x018) +#define I2C_RXDATA(base) MMIO32((base) + 0x01C) +#define I2C_RXDATAP(base) MMIO32((base) + 0x020) +#define I2C_TXDATA(base) MMIO32((base) + 0x024) +#define I2C_IF(base) MMIO32((base) + 0x028) +#define I2C_IFS(base) MMIO32((base) + 0x02C) +#define I2C_IFC(base) MMIO32((base) + 0x030) +#define I2C_IEN(base) MMIO32((base) + 0x034) +#define I2C_ROUTE(base) MMIO32((base) + 0x038) + +/* I2C_CTRL */ +#define I2C_CTRL_CLTO_SHIFT (16) +#define I2C_CTRL_CLTO_MASK (0x7 << I2C_CTRL_CLTO_SHIFT) +#define I2C_CTRL_CLTO(v) \ + (((v) << I2C_CTRL_CLTO_SHIFT) & I2C_CTRL_CLTO_MASK) +#define I2C_CTRL_CLTO_OFF 0 +#define I2C_CTRL_CLTO_40PCC 1 +#define I2C_CTRL_CLTO_80PCC 2 +#define I2C_CTRL_CLTO_160PCC 3 +#define I2C_CTRL_CLTO_320PPC 4 +#define I2C_CTRL_CLTO_1024PPC 5 + +#define I2C_CTRL_GIBITO (1 << 15) + +#define I2C_CTRL_BTO_SHIFT (12) +#define I2C_CTRL_BTO_MASK (0x3 << I2C_CTRL_BTO_SHIFT) +#define I2C_CTRL_BTO(v) \ + (((v) << I2C_CTRL_BTO_SHIFT) & I2C_CTRL_BTO_MASK) +#define I2C_CTRL_BTO_OFF 0 +#define I2C_CTRL_BTO_40PCC 1 +#define I2C_CTRL_BTO_80PCC 2 +#define I2C_CTRL_BTO_160PCC 3 + +#define I2C_CTRL_CLHR_SHIFT (12) +#define I2C_CTRL_CLHR_MASK (0x3 << I2C_CTRL_CLHR_SHIFT) +#define I2C_CTRL_CLHR(v) \ + (((v) << I2C_CTRL_CLHR_SHIFT) & I2C_CTRL_CLHR_MASK) +#define I2C_CTRL_CLHR_STANDARD 0 +#define I2C_CTRL_CLHR_ASYMMETRIC 1 +#define I2C_CTRL_CLHR_FAST 2 + +#define I2C_CTRL_GCAMEN (1 << 6) +#define I2C_CTRL_ARBDIS (1 << 5) +#define I2C_CTRL_AUTOSN (1 << 4) +#define I2C_CTRL_AUTOSE (1 << 3) +#define I2C_CTRL_AUTOACK (1 << 2) +#define I2C_CTRL_SLAVE (1 << 1) +#define I2C_CTRL_EN (1 << 0) + +/* I2C_CMD */ +#define I2C_CMD_CLEARPC (1 << 7) +#define I2C_CMD_CLEARTX (1 << 6) +#define I2C_CMD_ABORT (1 << 5) +#define I2C_CMD_CONT (1 << 4) +#define I2C_CMD_NACK (1 << 3) +#define I2C_CMD_ACK (1 << 2) +#define I2C_CMD_STOP (1 << 1) +#define I2C_CMD_START (1 << 0) + +/* I2C_STATE */ +#define I2C_STATE_STATE_SHIFT (5) +#define I2C_STATE_STATE_MASK (0x7 << I2C_STATE_STATE_SHIFT) +#define I2C_STATE_STATE(v) \ + (((v) << I2C_STATE_STATE_SHIFT) & I2C_STATE_STATE_MASK) +#define I2C_STATE_STATE_IDLE 0 +#define I2C_STATE_STATE_WAIT 1 +#define I2C_STATE_STATE_START 2 +#define I2C_STATE_STATE_ADDR 3 +#define I2C_STATE_STATE_ADDRACK 4 +#define I2C_STATE_STATE_DATA 5 +#define I2C_STATE_STATE_DATAACK 6 + +#define I2C_STATE_BUSHOLD (1 << 4) +#define I2C_STATE_NACKED (1 << 3) +#define I2C_STATE_TRANSMITTER (1 << 2) +#define I2C_STATE_MASTER (1 << 1) +#define I2C_STATE_BUSY (1 << 0) + +/* I2C_STATUS */ +#define I2C_STATUS_RXDATAV (1 << 8) +#define I2C_STATUS_TXBL (1 << 7) +#define I2C_STATUS_TXC (1 << 6) +#define I2C_STATUS_PABORT (1 << 5) +#define I2C_STATUS_PCONT (1 << 4) +#define I2C_STATUS_PNACK (1 << 3) +#define I2C_STATUS_PACK (1 << 2) +#define I2C_STATUS_PSTOP (1 << 1) +#define I2C_STATUS_PSTART (1 << 0) + +/* I2C_CLKDIV */ +#define I2C_CLKDIV_DIV_SHIFT (0) +#define I2C_CLKDIV_DIV_MASK (0xFF << I2C_CLKDIV_DIV_SHIFT) +#define I2C_CLKDIV_DIV(v) \ + (((v) << I2C_CLKDIV_DIV_SHIFT) & I2C_CLKDIV_DIV_MASK) + +/* I2C_SADDR */ +#define I2C_SADDR_ADDR_SHIFT (0) +#define I2C_SADDR_ADDR_MASK (0xFF << I2C_SADDR_ADDR_SHIFT) +#define I2C_SADDR_ADDR(v) \ + (((v) << I2C_SADDR_ADDR_SHIFT) & I2C_SADDR_ADDR_MASK) + +/* I2C_SADDRMASK */ +#define I2C_SADDRMASK_MASK_SHIFT (0) +#define I2C_SADDRMASK_MASK_MASK (0xFF << I2C_SADDRMASK_MASK_SHIFT) +#define I2C_SADDRMASK_MASK(v) \ + (((v) << I2C_SADDRMASK_MASK_SHIFT) & I2C_SADDRMASK_MASK_MASK) + +/* I2C_IF */ +#define I2C_IF_SSTOP (1 << 16) +#define I2C_IF_CLTO (1 << 15) +#define I2C_IF_BITO (1 << 14) +#define I2C_IF_RXUF (1 << 13) +#define I2C_IF_TXOF (1 << 12) +#define I2C_IF_BUSHOLD (1 << 11) +#define I2C_IF_BUSERR (1 << 10) +#define I2C_IF_ARBLOST (1 << 9) +#define I2C_IF_MSTOP (1 << 8) +#define I2C_IF_NACK (1 << 7) +#define I2C_IF_ACK (1 << 6) +#define I2C_IF_RXDATAV (1 << 5) +#define I2C_IF_TXBL (1 << 4) +#define I2C_IF_TXC (1 << 3) +#define I2C_IF_ADDR (1 << 2) +#define I2C_IF_RSTART (1 << 1) +#define I2C_IF_START (1 << 0) + +/* I2C_IFS */ +#define I2C_IFS_SSTOP (1 << 16) +#define I2C_IFS_CLTO (1 << 15) +#define I2C_IFS_BITO (1 << 14) +#define I2C_IFS_RXUF (1 << 13) +#define I2C_IFS_TXOF (1 << 12) +#define I2C_IFS_BUSHOLD (1 << 11) +#define I2C_IFS_BUSERR (1 << 10) +#define I2C_IFS_ARBLOST (1 << 9) +#define I2C_IFS_MSTOP (1 << 8) +#define I2C_IFS_NACK (1 << 7) +#define I2C_IFS_ACK (1 << 6) +#define I2C_IFS_RXDATAV (1 << 5) +#define I2C_IFS_TXBL (1 << 4) +#define I2C_IFS_TXC (1 << 3) +#define I2C_IFS_ADDR (1 << 2) +#define I2C_IFS_RSTART (1 << 1) +#define I2C_IFS_START (1 << 0) + +/* I2C_IFC */ +#define I2C_IFC_SSTOP (1 << 16) +#define I2C_IFC_CLTO (1 << 15) +#define I2C_IFC_BITO (1 << 14) +#define I2C_IFC_RXUF (1 << 13) +#define I2C_IFC_TXOF (1 << 12) +#define I2C_IFC_BUSHOLD (1 << 11) +#define I2C_IFC_BUSERR (1 << 10) +#define I2C_IFC_ARBLOST (1 << 9) +#define I2C_IFC_MSTOP (1 << 8) +#define I2C_IFC_NACK (1 << 7) +#define I2C_IFC_ACK (1 << 6) +#define I2C_IFC_RXDATAV (1 << 5) +#define I2C_IFC_TXBL (1 << 4) +#define I2C_IFC_TXC (1 << 3) +#define I2C_IFC_ADDR (1 << 2) +#define I2C_IFC_RSTART (1 << 1) +#define I2C_IFC_START (1 << 0) + +/* I2C_IEN */ +#define I2C_IEN_SSTOP (1 << 16) +#define I2C_IEN_CLTO (1 << 15) +#define I2C_IEN_BITO (1 << 14) +#define I2C_IEN_RXUF (1 << 13) +#define I2C_IEN_TXOF (1 << 12) +#define I2C_IEN_BUSHOLD (1 << 11) +#define I2C_IEN_BUSERR (1 << 10) +#define I2C_IEN_ARBLOST (1 << 9) +#define I2C_IEN_MSTOP (1 << 8) +#define I2C_IEN_NACK (1 << 7) +#define I2C_IEN_ACK (1 << 6) +#define I2C_IEN_RXDATAV (1 << 5) +#define I2C_IEN_TXBL (1 << 4) +#define I2C_IEN_TXC (1 << 3) +#define I2C_IEN_ADDR (1 << 2) +#define I2C_IEN_RSTART (1 << 1) +#define I2C_IEN_START (1 << 0) + +/* I2C_ROUTE */ +#define I2C_ROUTE_LOCATION_SHIFT (8) +#define I2C_ROUTE_LOCATION_MASK (0x7 << I2C_ROUTE_LOCATION_SHIFT) +#define I2C_ROUTE_LOCATION(v) \ + (((v) << I2C_ROUTE_LOCATION_SHIFT) & I2C_ROUTE_LOCATION_MASK) +#define I2C_ROUTE_LOCATION_LOCx(x) I2C_ROUTE_LOCATION(x) +#define I2C_ROUTE_LOCATION_LOC0 0 +#define I2C_ROUTE_LOCATION_LOC1 1 +#define I2C_ROUTE_LOCATION_LOC2 2 +#define I2C_ROUTE_LOCATION_LOC3 3 +#define I2C_ROUTE_LOCATION_LOC4 4 +#define I2C_ROUTE_LOCATION_LOC5 5 +#define I2C_ROUTE_LOCATION_LOC6 6 + +#define I2C_ROUTE_SCLPEN (1 << 1) +#define I2C_ROUTE_SDAPEN (1 << 0) + +/* I2C0 */ +#define I2C0 I2C0_BASE +#define I2C0_CTRL I2C_CTRL(base) +#define I2C0_CMD I2C_CMD(base) +#define I2C0_STATE I2C_STATE(base) +#define I2C0_STATUS I2C_STATUS(base) +#define I2C0_CLKDIV I2C_CLKDIV(base) +#define I2C0_SADDR I2C_SADDR(base) +#define I2C0_SADDRMASK I2C_SADDRMASK(base) +#define I2C0_RXDATA I2C_RXDATA(base) +#define I2C0_RXDATAP I2C_RXDATAP(base) +#define I2C0_TXDATA I2C_TXDATA(base) +#define I2C0_IF I2C_IF(base) +#define I2C0_IFS I2C_IFS(base) +#define I2C0_IFC I2C_IFC(base) +#define I2C0_IEN I2C_IEN(base) +#define I2C0_ROUTE I2C_ROUTE(base) + +/* I2C1 */ +#define I2C1 I2C1_BASE +#define I2C1_CTRL I2C_CTRL(base) +#define I2C1_CMD I2C_CMD(base) +#define I2C1_STATE I2C_STATE(base) +#define I2C1_STATUS I2C_STATUS(base) +#define I2C1_CLKDIV I2C_CLKDIV(base) +#define I2C1_SADDR I2C_SADDR(base) +#define I2C1_SADDRMASK I2C_SADDRMASK(base) +#define I2C1_RXDATA I2C_RXDATA(base) +#define I2C1_RXDATAP I2C_RXDATAP(base) +#define I2C1_TXDATA I2C_TXDATA(base) +#define I2C1_IF I2C_IF(base) +#define I2C1_IFS I2C_IFS(base) +#define I2C1_IFC I2C_IFC(base) +#define I2C1_IEN I2C_IEN(base) +#define I2C1_ROUTE I2C_ROUTE(base) + +#endif + diff --git a/include/libopencm3/efm32/common/letimer_common.h b/include/libopencm3/efm32/common/letimer_common.h new file mode 100644 index 00000000..40c2f9ff --- /dev/null +++ b/include/libopencm3/efm32/common/letimer_common.h @@ -0,0 +1,165 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2015 Kuldeep Singh Dhaka + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_EFM32_LETIMER_H +#define LIBOPENCM3_EFM32_LETIMER_H + +#include +#include + +#define LETIMER_CTRL(base) ((base) + 0x000) +#define LETIMER_CMD(base) ((base) + 0x004) +#define LETIMER_STATUS(base) ((base) + 0x008) +#define LETIMER_CNT(base) ((base) + 0x00C) +#define LETIMER_COMP0(base) ((base) + 0x010) +#define LETIMER_COMP1(base) ((base) + 0x014) +#define LETIMER_REP0(base) ((base) + 0x018) +#define LETIMER_REP1(base) ((base) + 0x01C) +#define LETIMER_IF(base) ((base) + 0x020) +#define LETIMER_IFS(base) ((base) + 0x024) +#define LETIMER_IFC(base) ((base) + 0x028) +#define LETIMER_IEN(base) ((base) + 0x02C) +#define LETIMER_FREEZE(base) ((base) + 0x030) +#define LETIMER_SYNCBUSY(base) ((base) + 0x034) +#define LETIMER_ROUTE(base) ((base) + 0x040) + +/* LETIMER_CTRL */ +#define LETIMER_CTRL_DEBUG (1 << 12) +#define LETIMER_CTRL_RTCC1TEN (1 << 11) +#define LETIMER_CTRL_RTCC0TEN (1 << 10) +#define LETIMER_CTRL_COMP0TOP (1 << 9) +#define LETIMER_CTRL_BUFTOP (1 << 8) +#define LETIMER_CTRL_OPOL1 (1 << 7) +#define LETIMER_CTRL_OPOL0 (1 << 6) + +#define LETIMER_CTRL_UFOA1_SHIFT (4) +#define LETIMER_CTRL_UFOA1_MASK (0x3 << LETIMER_CTRL_UFOA1_SHIFT) +#define LETIMER_CTRL_UFOA1(v) \ + (((v) << LETIMER_CTRL_UFOA1_SHIFT) & LETIMER_CTRL_UFOA1_MASK) +#define LETIMER_CTRL_UFOA1_NONE 0 +#define LETIMER_CTRL_UFOA1_TOGGLE 1 +#define LETIMER_CTRL_UFOA1_PULSE 2 +#define LETIMER_CTRL_UFOA1_PWM 3 + +#define LETIMER_CTRL_UFOA0_SHIFT (2) +#define LETIMER_CTRL_UFOA0_MASK (0x3 << LETIMER_CTRL_UFOA0_SHIFT) +#define LETIMER_CTRL_UFOA0(v) \ + (((v) << LETIMER_CTRL_UFOA0_SHIFT) & LETIMER_CTRL_UFOA0_MASK) +#define LETIMER_CTRL_UFOA0_NONE 0 +#define LETIMER_CTRL_UFOA0_TOGGLE 1 +#define LETIMER_CTRL_UFOA0_PULSE 2 +#define LETIMER_CTRL_UFOA0_PWM 3 + +#define LETIMER_CTRL_REPMODE_SHIFT (2) +#define LETIMER_CTRL_REPMODE_MASK (0x3 << LETIMER_CTRL_REPMODE_SHIFT) +#define LETIMER_CTRL_REPMODE(v) \ + (((v) << LETIMER_CTRL_REPMODE_SHIFT) & LETIMER_CTRL_REPMODE_MASK) +#define LETIMER_CTRL_REPMODE_FREE 0 +#define LETIMER_CTRL_REPMODE_ONESHOT 1 +#define LETIMER_CTRL_REPMODE_BUFFERED 2 +#define LETIMER_CTRL_REPMODE_DOUBLE 3 +#define LETIMER_CTRL_REPMODE_ONE_SHOT LETIMER_CTRL_REPMODE_ONESHOT + +/* LETIMER_CMD */ +#define LETIMER_CMD_CTO1 (1 << 4) +#define LETIMER_CMD_CTO0 (1 << 3) +#define LETIMER_CMD_CLEAR (1 << 2) +#define LETIMER_CMD_STOP (1 << 1) +#define LETIMER_CMD_START (1 << 0) + +/* LETIMER_STATUS */ +#define LETIMER_STATUS_RUNNING (1 << 0) + +/* LETIMER_IF */ +#define LETIMER_IF_REP1 (1 << 4) +#define LETIMER_IF_REP0 (1 << 3) +#define LETIMER_IF_UF (1 << 2) +#define LETIMER_IF_COMP1 (1 << 1) +#define LETIMER_IF_COMP0 (1 << 0) + +/* LETIMER_IFS */ +#define LETIMER_IFS_REP1 (1 << 4) +#define LETIMER_IFS_REP0 (1 << 3) +#define LETIMER_IFS_UF (1 << 2) +#define LETIMER_IFS_COMP1 (1 << 1) +#define LETIMER_IFS_COMP0 (1 << 0) + +/* LETIMER_IFC */ +#define LETIMER_IFC_REP1 (1 << 4) +#define LETIMER_IFC_REP0 (1 << 3) +#define LETIMER_IFC_UF (1 << 2) +#define LETIMER_IFC_COMP1 (1 << 1) +#define LETIMER_IFC_COMP0 (1 << 0) + +/* LETIMER_IFE */ +#define LETIMER_IFE_REP1 (1 << 4) +#define LETIMER_IFE_REP0 (1 << 3) +#define LETIMER_IFE_UF (1 << 2) +#define LETIMER_IFE_COMP1 (1 << 1) +#define LETIMER_IFE_COMP0 (1 << 0) + +/* LETIMER_FREEZE */ +#define LETIMER_FREEZE_REGFREEZE (1 << 0) + +/* LETIMER_SYNCBUSY */ +#define LETIMER_SYNCBUSY_REP1 (1 << 5) +#define LETIMER_SYNCBUSY_REP0 (1 << 4) +#define LETIMER_SYNCBUSY_COMP1 (1 << 3) +#define LETIMER_SYNCBUSY_COMP0 (1 << 2) +#define LETIMER_SYNCBUSY_CMD (1 << 1) +#define LETIMER_SYNCBUSY_CTRL (1 << 0) + +/* LETIMER_ROUTE */ +#define LETIMER_ROUTE_LOCATION_SHIFT (8) +#define LETIMER_ROUTE_LOCATION_MASK (0x7 << LETIMER_ROUTE_LOCATION_SHIFT) +#define LETIMER_ROUTE_LOCATION(v) \ + (((v) << LETIMER_ROUTE_LOCATION_SHIFT) & LETIMER_ROUTE_LOCATION_MASK) +#define LETIMER_ROUTE_LOCATION_LOCx(x) LETIMER_ROUTE_LOCATION(x) +#define LETIMER_ROUTE_LOCATION_LOC0 0 +#define LETIMER_ROUTE_LOCATION_LOC1 1 +#define LETIMER_ROUTE_LOCATION_LOC2 2 +#define LETIMER_ROUTE_LOCATION_LOC3 3 +#define LETIMER_ROUTE_LOCATION_LOC4 4 +#define LETIMER_ROUTE_LOCATION_LOC5 5 +#define LETIMER_ROUTE_LOCATION_LOC6 6 +#define LETIMER_ROUTE_LOCATION_LOC7 7 + +#define LETIMER_ROUTE_OUT1PEN (1 << 1) +#define LETIMER_ROUTE_OUT0PEN (1 << 0) + +/* LETIMER0 */ +#define LETIMER0 LETIMER0_BASE +#define LETIMER0_CTRL LETIMER_CTRL(LETIMER0) +#define LETIMER0_CMD LETIMER_CMD(LETIMER0) +#define LETIMER0_STATUS LETIMER_STATUS(LETIMER0) +#define LETIMER0_CNT LETIMER_CNT(LETIMER0) +#define LETIMER0_COMP0 LETIMER_COMP0(LETIMER0) +#define LETIMER0_COMP1 LETIMER_COMP1(LETIMER0) +#define LETIMER0_REP0 LETIMER_REP0(LETIMER0) +#define LETIMER0_REP1 LETIMER_REP1(LETIMER0) +#define LETIMER0_IF LETIMER_IF(LETIMER0) +#define LETIMER0_IFS LETIMER_IFS(LETIMER0) +#define LETIMER0_IFC LETIMER_IFC(LETIMER0) +#define LETIMER0_IEN LETIMER_IEN(LETIMER0) +#define LETIMER0_FREEZE LETIMER_FREEZE(LETIMER0) +#define LETIMER0_SYNCBUSY LETIMER_SYNCBUSY(LETIMER0) +#define LETIMER0_ROUTE LETIMER_ROUTE(LETIMER0) + +#endif + diff --git a/include/libopencm3/efm32/common/msc_common.h b/include/libopencm3/efm32/common/msc_common.h new file mode 100644 index 00000000..0dd7a782 --- /dev/null +++ b/include/libopencm3/efm32/common/msc_common.h @@ -0,0 +1,154 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2015 Kuldeep Singh Dhaka + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_EFM32_MSC_H +#define LIBOPENCM3_EFM32_MSC_H + +#include +#include + +#define MSC_CTRL MMIO32(MSC_BASE + 0x000) +#define MSC_READCTRL MMIO32(MSC_BASE + 0x004) +#define MSC_WRITECTRL MMIO32(MSC_BASE + 0x008) +#define MSC_WRITECMD MMIO32(MSC_BASE + 0x00C) +#define MSC_ADDRB MMIO32(MSC_BASE + 0x010) +#define MSC_WDATA MMIO32(MSC_BASE + 0x018) +#define MSC_STATUS MMIO32(MSC_BASE + 0x01C) +#define MSC_IF MMIO32(MSC_BASE + 0x02C) +#define MSC_IFS MMIO32(MSC_BASE + 0x030) +#define MSC_IFC MMIO32(MSC_BASE + 0x034) +#define MSC_IEN MMIO32(MSC_BASE + 0x038) +#define MSC_LOCK MMIO32(MSC_BASE + 0x03C) +#define MSC_CMD MMIO32(MSC_BASE + 0x040) +#define MSC_CACHEHITS MMIO32(MSC_BASE + 0x044) +#define MSC_CACHEMISSES MMIO32(MSC_BASE + 0x048) +#define MSC_TIMEBASE MMIO32(MSC_BASE + 0x050) +#define MSC_MASSLOCK MMIO32(MSC_BASE + 0x054) + +/* MSC_CTRL */ +#define MSC_CTRL_BUSFAULT (1 << 0) + +/* MSC_READCTRL */ +#define MSC_READCTRL_BUSSTRATEGY_SHIFT (16) +#define MSC_READCTRL_BUSSTRATEGY_MASK \ + (0x3 << MSC_READCTRL_BUSSTRATEGY_SHIFT) +#define MSC_READCTRL_BUSSTRATEGY(v) \ + (((v) << MSC_READCTRL_BUSSTRATEGY_SHIFT) & \ + MSC_READCTRL_BUSSTRATEGY_MASK) + +#define MSC_READCTRL_BUSSTRATEGY_CPU MSC_READCTRL_BUSSTRATEGY(0) +#define MSC_READCTRL_BUSSTRATEGY_DMA MSC_READCTRL_BUSSTRATEGY(1) +#define MSC_READCTRL_BUSSTRATEGY_DMAEM1 MSC_READCTRL_BUSSTRATEGY(2) +#define MSC_READCTRL_BUSSTRATEGY_NONE MSC_READCTRL_BUSSTRATEGY(3) + +#define MSC_READCTRL_RAMCEN (1 << 7) +#define MSC_READCTRL_EBICDIS (1 << 6) +#define MSC_READCTRL_ICCDIS (1 << 5) +#define MSC_READCTRL_AIDIS (1 << 4) +#define MSC_READCTRL_IFCDIS (1 << 3) + +#define MSC_READCTRL_MODE_SHIFT (0) +#define MSC_READCTRL_MODE_MASK (0x7 << MSC_READCTRL_MODE_SHIFT) +#define MSC_READCTRL_MODE(v) \ + (((v) << MSC_READCTRL_MODE_SHIFT) & MSC_READCTRL_MODE_MASK) +#define MSC_READCTRL_MODE_WS0 0 +#define MSC_READCTRL_MODE_WS1 1 +#define MSC_READCTRL_MODE_WS0SCBTP 2 +#define MSC_READCTRL_MODE_WS1SCBTP 3 +#define MSC_READCTRL_MODE_WS2 4 +#define MSC_READCTRL_MODE_WS2SCBTP 5 + +/* MSC_WRITECTRL */ +#define MSC_WRITECTRL_IRQERASEABORT (1 << 1) +#define MSC_WRITECTRL_WREN (1 << 0) + +/* MSC_WRITECMD */ +#define MSC_WRITECMD_CLEARWDATA (1 << 12) +#define MSC_WRITECMD_ERASEMAIN0 (1 << 8) +#define MSC_WRITECMD_ERASEABORT (1 << 5) +#define MSC_WRITECMD_WRITETRIG (1 << 4) +#define MSC_WRITECMD_WRITEONCE (1 << 3) +#define MSC_WRITECMD_WRITEEND (1 << 2) +#define MSC_WRITECMD_ERASEPAGE (1 << 1) +#define MSC_WRITECMD_LADDRIM (1 << 0) + +/* MSC_STATUS */ +#define MSC_STATUS_PCRUNNING (1 << 6) +#define MSC_STATUS_ERASEABORTED (1 << 5) +#define MSC_STATUS_WORDTIMEOUT (1 << 4) +#define MSC_STATUS_WDATAREADY (1 << 3) +#define MSC_STATUS_INVADDR (1 << 2) +#define MSC_STATUS_LOCKED (1 << 1) +#define MSC_STATUS_BUSY (1 << 0) + +/* MSC_IF */ +#define MSC_IF_CMOF (1 << 3) +#define MSC_IF_CHOF (1 << 2) +#define MSC_IF_WRITE (1 << 1) +#define MSC_IF_ERASE (1 << 0) + +/* MSC_IFS */ +#define MSC_IFS_CMOF (1 << 3) +#define MSC_IFS_CHOF (1 << 2) +#define MSC_IFS_WRITE (1 << 1) +#define MSC_IFS_ERASE (1 << 0) + +/* MSC_IFC */ +#define MSC_IFC_CMOF (1 << 3) +#define MSC_IFC_CHOF (1 << 2) +#define MSC_IFC_WRITE (1 << 1) +#define MSC_IFC_ERASE (1 << 0) + +/* MSC_*IEN */ +#define MSC_IEN_CMOF (1 << 3) +#define MSC_IEN_CHOF (1 << 2) +#define MSC_IEN_WRITE (1 << 1) +#define MSC_IEN_ERASE (1 << 0) + +/* MSC_LOCK */ +#define MSC_LOCK_LOCKKEY_SHIFT (0) +#define MSC_LOCK_LOCKKEY(v) ((v) << MSC_LOCK_LOCKKEY_SHIFT) +#define MSC_LOCK_LOCKKEY_UNLOCKED MSC_LOCK_LOCKKEY(0) +#define MSC_LOCK_LOCKKEY_LOCKED MSC_LOCK_LOCKKEY(1) +#define MSC_LOCK_LOCKKEY_LOCK MSC_LOCK_LOCKKEY(0) +#define MSC_LOCK_LOCKKEY_UNLOCK MSC_LOCK_LOCKKEY(0x1B71) + +/* MSC_CMD */ +#define MSC_CMD_STOPPC (1 << 2) +#define MSC_CMD_STARTPC (1 << 1) +#define MSC_CMD_INVCACHE (1 << 0) + +/* MSC_TIMEBASE */ +#define MSC_TIMEBASE_PERIOD (1 << 16) + +#define MSC_TIMEBASE_BASE_SHIFT (0) +#define MSC_TIMEBASE_BASE_MASK (0x3F << MSC_TIMEBASE_BASE_SHIFT) +#define MSC_TIMEBASE_BASE(v) \ + (((v) << MSC_TIMEBASE_BASE_SHIFT) & MSC_TIMEBASE_BASE_MASK) + +/* MSC_MASSLOCK */ +#define MSC_MASSLOCK_LOCKKEY_SHIFT (0) +#define MSC_MASSLOCK_LOCKKEY(v) ((v) << MSC_MASSLOCK_LOCKKEY_SHIFT) +#define MSC_MASSLOCK_LOCKKEY_UNLOCKED MSC_MASSLOCK_LOCKKEY(0) +#define MSC_MASSLOCK_LOCKKEY_LOCKED MSC_MASSLOCK_LOCKKEY(1) +#define MSC_MASSLOCK_LOCKKEY_LOCK MSC_MASSLOCK_LOCKKEY(0) +#define MSC_MASSLOCK_LOCKKEY_UNLOCK MSC_MASSLOCK_LOCKKEY(0x631A) + +#endif + diff --git a/include/libopencm3/efm32/common/opamp_common.h b/include/libopencm3/efm32/common/opamp_common.h new file mode 100644 index 00000000..29829098 --- /dev/null +++ b/include/libopencm3/efm32/common/opamp_common.h @@ -0,0 +1,21 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2015 Kuldeep Singh Dhaka + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* OpAmp register are in dac.h */ +#include diff --git a/include/libopencm3/efm32/common/prs_common.h b/include/libopencm3/efm32/common/prs_common.h new file mode 100644 index 00000000..82fde156 --- /dev/null +++ b/include/libopencm3/efm32/common/prs_common.h @@ -0,0 +1,363 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2015 Kuldeep Singh Dhaka + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_EFM32_PRS_H +#define LIBOPENCM3_EFM32_PRS_H + +#include +#include + +#define PRS_SWPULSE MMIO32(PRS_BASE + 0x000) +#define PRS_SWLEVEL MMIO32(PRS_BASE + 0x004) +#define PRS_ROUTE MMIO32(PRS_BASE + 0x008) +#define PRS_CHx_CTRL(x) MMIO32(PRS_BASE + 0x010 + (0x004 * (x))) +#define PRS_CH0_CTRL PRS_CHx_CTRL(0) +#define PRS_CH1_CTRL PRS_CHx_CTRL(1) +#define PRS_CH2_CTRL PRS_CHx_CTRL(2) +#define PRS_CH3_CTRL PRS_CHx_CTRL(3) +#define PRS_CH4_CTRL PRS_CHx_CTRL(4) +#define PRS_CH5_CTRL PRS_CHx_CTRL(5) +#define PRS_CH6_CTRL PRS_CHx_CTRL(6) +#define PRS_CH7_CTRL PRS_CHx_CTRL(71) +#define PRS_CH8_CTRL PRS_CHx_CTRL(8) +#define PRS_CH9_CTRL PRS_CHx_CTRL(9) +#define PRS_CH10_CTRL PRS_CHx_CTRL(10) +#define PRS_CH11_CTRL PRS_CHx_CTRL(11) + +/* PRS_SWPULSE */ +#define PRS_SWPULSE_CHxPULSE(x) (1 << (x)) +#define PRS_SWPULSE_CH0PULSE PRS_SWPULSE_CHxPULSE(0) +#define PRS_SWPULSE_CH1PULSE PRS_SWPULSE_CHxPULSE(1) +#define PRS_SWPULSE_CH2PULSE PRS_SWPULSE_CHxPULSE(2) +#define PRS_SWPULSE_CH3PULSE PRS_SWPULSE_CHxPULSE(3) +#define PRS_SWPULSE_CH4PULSE PRS_SWPULSE_CHxPULSE(4) +#define PRS_SWPULSE_CH5PULSE PRS_SWPULSE_CHxPULSE(5) +#define PRS_SWPULSE_CH6PULSE PRS_SWPULSE_CHxPULSE(6) +#define PRS_SWPULSE_CH7PULSE PRS_SWPULSE_CHxPULSE(7) +#define PRS_SWPULSE_CH8PULSE PRS_SWPULSE_CHxPULSE(8) +#define PRS_SWPULSE_CH9PULSE PRS_SWPULSE_CHxPULSE(9) +#define PRS_SWPULSE_CH10PULSE PRS_SWPULSE_CHxPULSE(10) +#define PRS_SWPULSE_CH11PULSE PRS_SWPULSE_CHxPULSE(11) + +/* PRS_SWLEVEL */ +#define PRS_SWLEVEL_CHxLEVEL(x) (1 << (x)) +#define PRS_SWLEVEL_CH0LEVEL PRS_SWLEVEL_CHxLEVEL(0) +#define PRS_SWLEVEL_CH1LEVEL PRS_SWLEVEL_CHxLEVEL(1) +#define PRS_SWLEVEL_CH2LEVEL PRS_SWLEVEL_CHxLEVEL(2) +#define PRS_SWLEVEL_CH3LEVEL PRS_SWLEVEL_CHxLEVEL(3) +#define PRS_SWLEVEL_CH4LEVEL PRS_SWLEVEL_CHxLEVEL(4) +#define PRS_SWLEVEL_CH5LEVEL PRS_SWLEVEL_CHxLEVEL(5) +#define PRS_SWLEVEL_CH6LEVEL PRS_SWLEVEL_CHxLEVEL(6) +#define PRS_SWLEVEL_CH7LEVEL PRS_SWLEVEL_CHxLEVEL(7) +#define PRS_SWLEVEL_CH8LEVEL PRS_SWLEVEL_CHxLEVEL(8) +#define PRS_SWLEVEL_CH9LEVEL PRS_SWLEVEL_CHxLEVEL(9) +#define PRS_SWLEVEL_CH10LEVEL PRS_SWLEVEL_CHxLEVEL(10) +#define PRS_SWLEVEL_CH11LEVEL PRS_SWLEVEL_CHxLEVEL(11) + +/* PRS_ROUTE */ +#define PRS_ROUTE_LOCATION_SHIFT (8) +#define PRS_ROUTE_LOCATION_MASK (0x7 << PRS_ROUTE_LOCATION_SHIFT) +#define PRS_ROUTE_LOCATION(v) \ + (((v) << PRS_ROUTE_LOCATION_SHIFT) & PRS_ROUTE_LOCATION_MASK) +#define PRS_ROUTE_LOCATION_LOCx(x) PRS_ROUTE_LOCATION(x) +#define PRS_ROUTE_LOCATION_LOC0 0 +#define PRS_ROUTE_LOCATION_LOC1 1 + +#define PRS_ROUTE_CHxPEN(x) (1 << (x)) +#define PRS_ROUTE_CH3PEN PRS_ROUTE_CHxPEN(3) +#define PRS_ROUTE_CH2PEN PRS_ROUTE_CHxPEN(2) +#define PRS_ROUTE_CH1PEN PRS_ROUTE_CHxPEN(1) +#define PRS_ROUTE_CH0PEN PRS_ROUTE_CHxPEN(0) + +/* PRS_CHx_CTRL */ +#define PRS_CH_CTRL_ASYNC (1 << 28) + +#define PRS_CH_CTRL_EDSEL_SHIFT (24) +#define PRS_CH_CTRL_EDSEL_MASK (0x3 << PRS_CH_CTRL_EDSEL_SHIFT) +#define PRS_CH_CTRL_EDSEL_OFF (0 << PRS_CH_CTRL_EDSEL_SHIFT) +#define PRS_CH_CTRL_EDSEL_POSEDGE (1 << PRS_CH_CTRL_EDSEL_SHIFT) +#define PRS_CH_CTRL_EDSEL_NEGEDGE (2 << PRS_CH_CTRL_EDSEL_SHIFT) +#define PRS_CH_CTRL_EDSEL_BOTHEDGES (3 << PRS_CH_CTRL_EDSEL_SHIFT) + +#define PRS_CH_CTRL_SOURCESEL_SHIFT (16) +#define PRS_CH_CTRL_SOURCESEL_MASK (0x3F << PRS_CH_CTRL_SOURCESEL_SHIFT) +#define PRS_CH_CTRL_SOURCESEL(v) \ + (((v) << PRS_CH_CTRL_SOURCESEL_SHIFT) & PRS_CH_CTRL_SOURCESEL_MASK) +#define PRS_CH_CTRL_SOURCESEL_NONE 0b000000 +#define PRS_CH_CTRL_SOURCESEL_VCMP 0b000001 +#define PRS_CH_CTRL_SOURCESEL_ACMP0 0b000010 +#define PRS_CH_CTRL_SOURCESEL_ACMP1 0b000011 +#define PRS_CH_CTRL_SOURCESEL_DAC0 0b000110 +#define PRS_CH_CTRL_SOURCESEL_ADC0 0b001000 +#define PRS_CH_CTRL_SOURCESEL_USART0 0b010000 +#define PRS_CH_CTRL_SOURCESEL_USART1 0b010001 +#define PRS_CH_CTRL_SOURCESEL_USART2 0b010010 +#define PRS_CH_CTRL_SOURCESEL_TIMER0 0b011100 +#define PRS_CH_CTRL_SOURCESEL_TIMER1 0b011101 +#define PRS_CH_CTRL_SOURCESEL_TIMER2 0b011110 +#define PRS_CH_CTRL_SOURCESEL_TIMER3 0b011111 +#define PRS_CH_CTRL_SOURCESEL_USB 0b100100 +#define PRS_CH_CTRL_SOURCESEL_RTC 0b101000 +#define PRS_CH_CTRL_SOURCESEL_UART0 0b101001 +#define PRS_CH_CTRL_SOURCESEL_UART1 0b101010 +#define PRS_CH_CTRL_SOURCESEL_GPIOL 0b110000 +#define PRS_CH_CTRL_SOURCESEL_GPIOH 0b110001 +#define PRS_CH_CTRL_SOURCESEL_LETIMER0 0b110100 +#define PRS_CH_CTRL_SOURCESEL_BURTC 0b110111 +#define PRS_CH_CTRL_SOURCESEL_LESENSEL 0b111001 +#define PRS_CH_CTRL_SOURCESEL_LESENSEH 0b111010 +#define PRS_CH_CTRL_SOURCESEL_LESENSED 0b111011 + +#define PRS_CH_CTRL_SIGSEL_SHIFT (0) +#define PRS_CH_CTRL_SIGSEL_MASK (0x7 << PRS_CH_CTRL_SIGSEL_SHIFT) +#define PRS_CH_CTRL_SIGSEL(v) \ + (((v) << PRS_CH_CTRL_SIGSEL_SHIFT) & PRS_CH_CTRL_SIGSEL_MASK) +#define PRS_CH_CTRL_SIGSEL_OFF 0 +#define PRS_CH_CTRL_SIGSEL_VCMPOUT 0 +#define PRS_CH_CTRL_SIGSEL_ACMP0OUT 0 +#define PRS_CH_CTRL_SIGSEL_ACMP1OUT 0 +#define PRS_CH_CTRL_SIGSEL_DAC0CH0 0 +#define PRS_CH_CTRL_SIGSEL_DAC0CH1 1 +#define PRS_CH_CTRL_SIGSEL_ADCSINGLE 0 +#define PRS_CH_CTRL_SIGSEL_ADCSCAN 1 +#define PRS_CH_CTRL_SIGSEL_USART0IRTX 0 +#define PRS_CH_CTRL_SIGSEL_USART0TXC 1 +#define PRS_CH_CTRL_SIGSEL_USART0RXDATA 2 +#define PRS_CH_CTRL_SIGSEL_USART1TXC 1 +#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV 2 +#define PRS_CH_CTRL_SIGSEL_USART2TXC 1 +#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV 2 +#define PRS_CH_CTRL_SIGSEL_TIMER0UF 0 +#define PRS_CH_CTRL_SIGSEL_TIMER0OF 1 +#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 2 +#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 3 +#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 4 +#define PRS_CH_CTRL_SIGSEL_TIMER1UF 0 +#define PRS_CH_CTRL_SIGSEL_TIMER1OF 1 +#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 2 +#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 3 +#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 4 +#define PRS_CH_CTRL_SIGSEL_TIMER2UF 0 +#define PRS_CH_CTRL_SIGSEL_TIMER2OF 1 +#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 2 +#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 3 +#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 4 +#define PRS_CH_CTRL_SIGSEL_TIMER3UF 0 +#define PRS_CH_CTRL_SIGSEL_TIMER3OF 1 +#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 2 +#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 3 +#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 4 +#define PRS_CH_CTRL_SIGSEL_USBSOF 0 +#define PRS_CH_CTRL_SIGSEL_USBSOFSR 1 +#define PRS_CH_CTRL_SIGSEL_RTCOF 0 +#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 1 +#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 2 +#define PRS_CH_CTRL_SIGSEL_UART0TXC 1 +#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV 2 +#define PRS_CH_CTRL_SIGSEL_UART1TXC 1 +#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV 2 +#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 0 +#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 1 +#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 2 +#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 3 +#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 4 +#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 5 +#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 6 +#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 7 +#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 0 +#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 1 +#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 2 +#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 3 +#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 4 +#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 5 +#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 6 +#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 7 +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0 +#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 1 +#define PRS_CH_CTRL_SIGSEL_BURTCOF 0 +#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 1 +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0 +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 1 +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 2 +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 3 +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 4 +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 5 +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 6 +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 7 +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0 +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 1 +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 2 +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 3 +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 4 +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 5 +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 6 +#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 7 +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0 +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 1 +#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 2 + +/* generic of above */ +#define PRS_CH_CTRL_SIGSEL_VCMP_OUT 0 +#define PRS_CH_CTRL_SIGSEL_ACMP_OUT 0 +#define PRS_CH_CTRL_SIGSEL_DAC_CHx(x) PRS_CH_CTRL_SIGSEL(x) +#define PRS_CH_CTRL_SIGSEL_DAC_CH0 0 +#define PRS_CH_CTRL_SIGSEL_DAC_CH1 1 +#define PRS_CH_CTRL_SIGSEL_ADC_SINGLE 0 +#define PRS_CH_CTRL_SIGSEL_ADC_SCAN 1 +#define PRS_CH_CTRL_SIGSEL_USART_IRTX 0 +#define PRS_CH_CTRL_SIGSEL_USART_TXC 1 +#define PRS_CH_CTRL_SIGSEL_USART_RXDATAV 2 +#define PRS_CH_CTRL_SIGSEL_TIMER_UF 0 +#define PRS_CH_CTRL_SIGSEL_TIMER_OF 1 +#define PRS_CH_CTRL_SIGSEL_TIMER_CCx(x) PRS_CH_CTRL_SIGSEL((x) + 2) +#define PRS_CH_CTRL_SIGSEL_TIMER_CC0 PRS_CH_CTRL_SIGSEL_TIMER_CCx(0) +#define PRS_CH_CTRL_SIGSEL_TIMER_CC1 PRS_CH_CTRL_SIGSEL_TIMER_CCx(1) +#define PRS_CH_CTRL_SIGSEL_TIMER_CC2 PRS_CH_CTRL_SIGSEL_TIMER_CCx(2) +#define PRS_CH_CTRL_SIGSEL_USB_SOF 0 +#define PRS_CH_CTRL_SIGSEL_USB_SOFSR 1 +#define PRS_CH_CTRL_SIGSEL_RTC_OF 0 +#define PRS_CH_CTRL_SIGSEL_RTC_COMPx(x) PRS_CH_CTRL_SIGSEL((x) + 1) +#define PRS_CH_CTRL_SIGSEL_RTC_COMP0 PRS_CH_CTRL_SIGSEL_RTC_COMPx(0) +#define PRS_CH_CTRL_SIGSEL_RTC_COMP1 PRS_CH_CTRL_SIGSEL_RTC_COMPx(1) +#define PRS_CH_CTRL_SIGSEL_UART_TXC 1 +#define PRS_CH_CTRL_SIGSEL_UART_RXDATAV 2 +#define PRS_CH_CTRL_SIGSEL_GPIOL_PINx(x) PRS_CH_CTRL_SIGSEL(x) +#define PRS_CH_CTRL_SIGSEL_GPIO_PIN0 \ + 0 +#define PRS_CH_CTRL_SIGSEL_GPIO_PIN1 \ + 1 +#define PRS_CH_CTRL_SIGSEL_GPIO_PIN2 \ + 2 +#define PRS_CH_CTRL_SIGSEL_GPIO_PIN3 \ + 3 +#define PRS_CH_CTRL_SIGSEL_GPIO_PIN4 \ + 4 +#define PRS_CH_CTRL_SIGSEL_GPIO_PIN5 \ + 5 +#define PRS_CH_CTRL_SIGSEL_GPIO_PIN6 \ + 6 +#define PRS_CH_CTRL_SIGSEL_GPIO_PIN7 \ + 7 +#define PRS_CH_CTRL_SIGSEL_GPIOH_PINx(x) PRS_CH_CTRL_SIGSEL((x) - 8) +#define PRS_CH_CTRL_SIGSEL_GPIO_PIN8 \ + PRS_CH_CTRL_SIGSEL_GPIOH_PINx(8) +#define PRS_CH_CTRL_SIGSEL_GPIO_PIN9 \ + PRS_CH_CTRL_SIGSEL_GPIOH_PINx(9) +#define PRS_CH_CTRL_SIGSEL_GPIO_PIN10 \ + PRS_CH_CTRL_SIGSEL_GPIOH_PINx(10) +#define PRS_CH_CTRL_SIGSEL_GPIO_PIN11 \ + PRS_CH_CTRL_SIGSEL_GPIOH_PINx(11) +#define PRS_CH_CTRL_SIGSEL_GPIO_PIN12 \ + PRS_CH_CTRL_SIGSEL_GPIOH_PINx(12) +#define PRS_CH_CTRL_SIGSEL_GPIO_PIN13 \ + PRS_CH_CTRL_SIGSEL_GPIOH_PINx(13) +#define PRS_CH_CTRL_SIGSEL_GPIO_PIN14 \ + PRS_CH_CTRL_SIGSEL_GPIOH_PINx(14) +#define PRS_CH_CTRL_SIGSEL_GPIO_PIN15 \ + PRS_CH_CTRL_SIGSEL_GPIOH_PINx(15) +#define PRS_CH_CTRL_SIGSEL_LETIMER_CHx(x) PRS_CH_CTRL_SIGSEL(x) +#define PRS_CH_CTRL_SIGSEL_LETIMER_CH0 \ + 0 +#define PRS_CH_CTRL_SIGSEL_LETIMER_CH1 \ + 1 +#define PRS_CH_CTRL_SIGSEL_BURTC_OF 0 +#define PRS_CH_CTRL_SIGSEL_BURTC_COMP0 1 +#define PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(x) PRS_CH_CTRL_SIGSEL(x) +#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES0 \ + 0 +#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES1 \ + 1 +#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES2 \ + 2 +#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES3 \ + 3 +#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES4 \ + 4 +#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES5 \ + 5 +#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES6 \ + 6 +#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES7 \ + 7 +#define PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(x) \ + PRS_CH_CTRL_SIGSEL((x) - 8) +#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES8 \ + PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(8) +#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES9 \ + PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(9) +#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES10 \ + PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(10) +#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES11 \ + PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(11) +#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES12 \ + PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(12) +#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES13 \ + PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(13) +#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES14 \ + PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(14) +#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES15 \ + PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(15) +#define PRS_CH_CTRL_SIGSEL_LESENSED_DECx(x) PRS_CH_CTRL_SIGSEL(x) +#define PRS_CH_CTRL_SIGSEL_LESENSE_DEC0 \ + 0 +#define PRS_CH_CTRL_SIGSEL_LESENSE_DEC1 \ + 1 +#define PRS_CH_CTRL_SIGSEL_LESENSE_DEC2 \ + 2 + +/** @defgroup prs_ch PRS Channel Number +@ingroup prs_defines + +@{*/ +enum prs_ch { + PRS_CH0 = 0, + PRS_CH1, + PRS_CH2, + PRS_CH3, + PRS_CH4, + PRS_CH5, + PRS_CH6, + PRS_CH7, + PRS_CH8, + PRS_CH9, + PRS_CH10, + PRS_CH11 +}; +/**@}*/ + +BEGIN_DECLS + +void prs_enable_gpio_output(enum prs_ch ch); +void prs_disable_gpio_output(enum prs_ch ch); +void prs_set_output_loc(uint32_t loc); + +void prs_software_pulse(enum prs_ch ch); +void prs_software_level_high(enum prs_ch ch); +void prs_software_level_low(enum prs_ch ch); + +void prs_enable_async(enum prs_ch ch); +void prs_disable_async(enum prs_ch ch); +void prs_set_edge(enum prs_ch ch, uint32_t edge); +void prs_set_source(enum prs_ch ch, uint32_t source); +void prs_set_signal(enum prs_ch ch, uint32_t sig); + +END_DECLS + +#endif + diff --git a/include/libopencm3/efm32/common/rmu_common.h b/include/libopencm3/efm32/common/rmu_common.h new file mode 100644 index 00000000..4a7e721a --- /dev/null +++ b/include/libopencm3/efm32/common/rmu_common.h @@ -0,0 +1,56 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2015 Kuldeep Singh Dhaka + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_EFM32_RMU_H +#define LIBOPENCM3_EFM32_RMU_H + +#include +#include + +#define RMU_CTRL MMIO32(RMU_BASE + 0x00) +#define RMU_RSTCAUSE MMIO32(RMU_BASE + 0x04) +#define RMU_CMD MMIO32(RMU_BASE + 0x08) + +/* RMU_CTRL */ +#define RMU_CTRL_BURSTEN (1 << 1) +#define RMU_CTRL_LOCKUPRDIS (1 << 0) + +/* RMU_RSTCAUSE */ +#define RMU_RSTCAUSE_BUMODERST (1 << 15) +#define RMU_RSTCAUSE_BUBODREG (1 << 14) +#define RMU_RSTCAUSE_BUBODUNREG (1 << 13) +#define RMU_RSTCAUSE_BUBODBUVIN (1 << 12) +#define RMU_RSTCAUSE_BUBODVDDDREG (1 << 11) +#define RMU_RSTCAUSE_BODAVDD1 (1 << 10) +#define RMU_RSTCAUSE_BODAVDD0 (1 << 9) +#define RMU_RSTCAUSE_EM4WURST (1 << 8) +#define RMU_RSTCAUSE_EM4RST (1 << 7) +#define RMU_RSTCAUSE_SYSREQRST (1 << 6) +#define RMU_RSTCAUSE_LOCKUPRST (1 << 5) +#define RMU_RSTCAUSE_WDOGRST (1 << 4) +#define RMU_RSTCAUSE_EXTRST (1 << 3) +#define RMU_RSTCAUSE_BODREGRST (1 << 2) +#define RMU_RSTCAUSE_BODUNREGRST (1 << 1) +#define RMU_RSTCAUSE_PORST (1 << 0) + +/* RMU_CMD */ +#define RMU_CMD_RCCLR (1 << 0) + +#endif + diff --git a/include/libopencm3/efm32/common/rtc_common.h b/include/libopencm3/efm32/common/rtc_common.h new file mode 100644 index 00000000..ad50bcbd --- /dev/null +++ b/include/libopencm3/efm32/common/rtc_common.h @@ -0,0 +1,71 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2015 Kuldeep Singh Dhaka + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_EFM32_RTC_H +#define LIBOPENCM3_EFM32_RTC_H + +#include +#include + +#define RTC_CTRL (RTC_BASE + 0x000) +#define RTC_CNT (RTC_BASE + 0x004) +#define RTC_COMP0 (RTC_BASE + 0x008) +#define RTC_COMP1 (RTC_BASE + 0x00C) +#define RTC_IF (RTC_BASE + 0x010) +#define RTC_IFS (RTC_BASE + 0x014) +#define RTC_IFC (RTC_BASE + 0x018) +#define RTC_IEN (RTC_BASE + 0x01C) +#define RTC_FREEZE (RTC_BASE + 0x020) +#define RTC_SYNCBUSY (RTC_BASE + 0x024) + +/* RTC_CTRL */ +#define RTC_CTRL_COMP0TOP (1 << 2) +#define RTC_CTRL_DEBUGRUN (1 << 1) +#define RTC_CTRL_EN (1 << 0) + +/* RTC_IF */ +#define RTC_IF_COMP1 (1 << 2) +#define RTC_IF_COMP0 (1 << 1) +#define RTC_IF_OF (1 << 0) + +/* RTC_IFS */ +#define RTC_IFS_COMP1 (1 << 2) +#define RTC_IFS_COMP0 (1 << 1) +#define RTC_IFS_OF (1 << 0) + +/* RTC_IFC */ +#define RTC_IFC_COMP1 (1 << 2) +#define RTC_IFC_COMP0 (1 << 1) +#define RTC_IFC_OF (1 << 0) + +/* RTC_IFE */ +#define RTC_IFE_COMP1 (1 << 2) +#define RTC_IFE_COMP0 (1 << 1) +#define RTC_IFE_OF (1 << 0) + +/* RTC_FREEZE */ +#define RTC_FREEZE_REGFREEZE (1 << 0) + +/* RTC_SYNCBUSY */ +#define RTC_SYNCBUSY_COMP1 (1 << 2) +#define RTC_SYNCBUSY_COMP0 (1 << 1) +#define RTC_SYNCBUSY_CTRL (1 << 0) + +#endif + diff --git a/include/libopencm3/efm32/common/timer_common_hglg.h b/include/libopencm3/efm32/common/timer_common.h similarity index 73% rename from include/libopencm3/efm32/common/timer_common_hglg.h rename to include/libopencm3/efm32/common/timer_common.h index 3eaedccc..4b05d128 100644 --- a/include/libopencm3/efm32/common/timer_common_hglg.h +++ b/include/libopencm3/efm32/common/timer_common.h @@ -17,11 +17,8 @@ * along with this library. If not, see . */ -/** @cond */ -#if defined(LIBOPENCM3_TIMER_H) -/** @endcond */ -#ifndef LIBOPENCM3_EFM32_TIMER_COMMON_HGLG_H -#define LIBOPENCM3_EFM32_TIMER_COMMON_HGLG_H +#ifndef LIBOPENCM3_EFM32_TIMER_H +#define LIBOPENCM3_EFM32_TIMER_H #include #include @@ -74,26 +71,26 @@ #define TIMER_CTRL_PRESC_MASK (0xF << TIMER_CTRL_PRESC_SHIFT) #define TIMER_CTRL_PRESC(v) \ (((v) << TIMER_CTRL_PRESC_SHIFT) & TIMER_CTRL_PRESC_MASK) -#define TIMER_CTRL_PRESC_DIV1 TIMER_CTRL_PRESC(0) -#define TIMER_CTRL_PRESC_DIV2 TIMER_CTRL_PRESC(1) -#define TIMER_CTRL_PRESC_DIV4 TIMER_CTRL_PRESC(2) -#define TIMER_CTRL_PRESC_DIV8 TIMER_CTRL_PRESC(3) -#define TIMER_CTRL_PRESC_DIV16 TIMER_CTRL_PRESC(4) -#define TIMER_CTRL_PRESC_DIV32 TIMER_CTRL_PRESC(5) -#define TIMER_CTRL_PRESC_DIV64 TIMER_CTRL_PRESC(6) -#define TIMER_CTRL_PRESC_DIV128 TIMER_CTRL_PRESC(7) -#define TIMER_CTRL_PRESC_DIV256 TIMER_CTRL_PRESC(8) -#define TIMER_CTRL_PRESC_DIV512 TIMER_CTRL_PRESC(9) -#define TIMER_CTRL_PRESC_DIV1024 TIMER_CTRL_PRESC(10) +#define TIMER_CTRL_PRESC_DIV1 0 +#define TIMER_CTRL_PRESC_DIV2 1 +#define TIMER_CTRL_PRESC_DIV4 2 +#define TIMER_CTRL_PRESC_DIV8 3 +#define TIMER_CTRL_PRESC_DIV16 4 +#define TIMER_CTRL_PRESC_DIV32 5 +#define TIMER_CTRL_PRESC_DIV64 6 +#define TIMER_CTRL_PRESC_DIV128 7 +#define TIMER_CTRL_PRESC_DIV256 8 +#define TIMER_CTRL_PRESC_DIV512 9 +#define TIMER_CTRL_PRESC_DIV1024 10 #define TIMER_CTRL_PRESC_NODIV TIMER_CTRL_PRESC_DIV1 #define TIMER_CTRL_CLKSEL_SHIFT (16) #define TIMER_CTRL_CLKSEL_MASK (0x3 << TIMER_CTRL_CLKSEL_SHIFT) #define TIMER_CTRL_CLKSEL(v) \ (((v) << TIMER_CTRL_CLKSEL_SHIFT) & TIMER_CTRL_CLKSEL_MASK) -#define TIMER_CTRL_CLKSEL_PRESCHFPERCLK TIMER_CTRL_CLKSEL(0) -#define TIMER_CTRL_CLKSEL_CC1 TIMER_CTRL_CLKSEL(1) -#define TIMER_CTRL_CLKSEL_TIMEROUF TIMER_CTRL_CLKSEL(2) +#define TIMER_CTRL_CLKSEL_PRESCHFPERCLK 0 +#define TIMER_CTRL_CLKSEL_CC1 1 +#define TIMER_CTRL_CLKSEL_TIMEROUF 2 #define TIMER_CTRL_X2CNT (1 << 13) @@ -101,19 +98,19 @@ #define TIMER_CTRL_FALLA_MASK (0x3 << TIMER_CTRL_FALLA_SHIFT) #define TIMER_CTRL_FALLA(v) \ (((v) << TIMER_CTRL_FALLA_SHIFT) & TIMER_CTRL_FALLA_MASK) -#define TIMER_CTRL_FALLA_NONE TIMER_CTRL_FALLA(0) -#define TIMER_CTRL_FALLA_START TIMER_CTRL_FALLA(1) -#define TIMER_CTRL_FALLA_STOP TIMER_CTRL_FALLA(2) -#define TIMER_CTRL_FALLA_RELOADSTART TIMER_CTRL_FALLA(3) +#define TIMER_CTRL_FALLA_NONE 0 +#define TIMER_CTRL_FALLA_START 1 +#define TIMER_CTRL_FALLA_STOP 2 +#define TIMER_CTRL_FALLA_RELOADSTART 3 #define TIMER_CTRL_RISEA_SHIFT (8) #define TIMER_CTRL_RISEA_MASK (0x3 << TIMER_CTRL_RISEA_SHIFT) #define TIMER_CTRL_RISEA(v) \ (((v) << TIMER_CTRL_RISEA_SHIFT) & TIMER_CTRL_RISEA_MASK) -#define TIMER_CTRL_RISEA_NONE TIMER_CTRL_RISEA(0) -#define TIMER_CTRL_RISEA_START TIMER_CTRL_RISEA(1) -#define TIMER_CTRL_RISEA_STOP TIMER_CTRL_RISEA(2) -#define TIMER_CTRL_RISEA_RELOADSTART TIMER_CTRL_RISEA(3) +#define TIMER_CTRL_RISEA_NONE 0 +#define TIMER_CTRL_RISEA_START 1 +#define TIMER_CTRL_RISEA_STOP 2 +#define TIMER_CTRL_RISEA_RELOADSTART 3 /* TIMER_CTRL_DMACLRACT bit is strangely documented. * set this bit, @@ -131,10 +128,10 @@ #define TIMER_CTRL_MODE_MASK (0x3 << TIMER_CTRL_MODE_SHIFT) #define TIMER_CTRL_MODE(v) \ (((v) << TIMER_CTRL_MODE_SHIFT) & TIMER_CTRL_MODE_MASK) -#define TIMER_CTRL_MODE_UP TIMER_CTRL_MODE(0) -#define TIMER_CTRL_MODE_DOWN TIMER_CTRL_MODE(1) -#define TIMER_CTRL_MODE_UPDOWN TIMER_CTRL_MODE(2) -#define TIMER_CTRL_MODE_QDEC TIMER_CTRL_MODE(3) +#define TIMER_CTRL_MODE_UP 0 +#define TIMER_CTRL_MODE_DOWN 1 +#define TIMER_CTRL_MODE_UPDOWN 2 +#define TIMER_CTRL_MODE_QDEC 3 /* TIMER_CMD */ #define TIMER_CMD_STOP (1 << 1) @@ -224,12 +221,12 @@ #define TIMER_ROUTE_LOCATION(v) \ (((v) << TIMER_ROUTE_LOCATION_SHIFT) & TIMER_ROUTE_LOCATION_MASK) #define TIMER_ROUTE_LOCATION_LOCx(x) TIMER_ROUTE_LOCATION(x) -#define TIMER_ROUTE_LOCATION_LOC0 TIMER_ROUTE_LOCATION_LOCx(0) -#define TIMER_ROUTE_LOCATION_LOC1 TIMER_ROUTE_LOCATION_LOCx(1) -#define TIMER_ROUTE_LOCATION_LOC2 TIMER_ROUTE_LOCATION_LOCx(2) -#define TIMER_ROUTE_LOCATION_LOC3 TIMER_ROUTE_LOCATION_LOCx(3) -#define TIMER_ROUTE_LOCATION_LOC4 TIMER_ROUTE_LOCATION_LOCx(4) -#define TIMER_ROUTE_LOCATION_LOC5 TIMER_ROUTE_LOCATION_LOCx(5) +#define TIMER_ROUTE_LOCATION_LOC0 0 +#define TIMER_ROUTE_LOCATION_LOC1 1 +#define TIMER_ROUTE_LOCATION_LOC2 2 +#define TIMER_ROUTE_LOCATION_LOC3 3 +#define TIMER_ROUTE_LOCATION_LOC4 4 +#define TIMER_ROUTE_LOCATION_LOC5 5 #define TIMER_ROUTE_CDTIxPEN(x) (1 << (8 + (x))) #define TIMER_ROUTE_CDTI0PEN TIMER_ROUTE_CDTIxPEN(0) @@ -246,10 +243,10 @@ #define TIMER_CC_CTRL_ICEVCTRL_MASK (0x3 << TIMER_CC_CTRL_ICEVCTRL_SHIFT) #define TIMER_CC_CTRL_ICEVCTRL(v) \ (((v) << TIMER_CC_CTRL_ICEVCTRL_SHIFT) & TIMER_CC_CTRL_ICEVCTRL_MASK) -#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE TIMER_CC_CTRL_ICEVCTRL(0) -#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE TIMER_CC_CTRL_ICEVCTRL(1) -#define TIMER_CC_CTRL_ICEVCTRL_RISING TIMER_CC_CTRL_ICEVCTRL(2) -#define TIMER_CC_CTRL_ICEVCTRL_FALLING TIMER_CC_CTRL_ICEVCTRL(3) +#define TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE 0 +#define TIMER_CC_CTRL_ICEVCTRL_EVERYSECONDEDGE 1 +#define TIMER_CC_CTRL_ICEVCTRL_RISING 2 +#define TIMER_CC_CTRL_ICEVCTRL_FALLING 3 #define TIMER_CC_CTRL_ICEVCTRL_EVERY_EDGE \ TIMER_CC_CTRL_ICEVCTRL_EVERYEDGE @@ -260,40 +257,59 @@ #define TIMER_CC_CTRL_ICEDGE_MASK (0x3 << TIMER_CC_CTRL_ICEDGE_SHIFT) #define TIMER_CC_CTRL_ICEDGE(v) \ (((v) << TIMER_CC_CTRL_ICEDGE_SHIFT) & TIMER_CC_CTRL_ICEDGE_MASK) -#define TIMER_CC_CTRL_ICEDGE_RISING TIMER_CC_CTRL_ICEDGE(0) -#define TIMER_CC_CTRL_ICEDGE_FALLING TIMER_CC_CTRL_ICEDGE(1) -#define TIMER_CC_CTRL_ICEDGE_BOTH TIMER_CC_CTRL_ICEDGE(2) -#define TIMER_CC_CTRL_ICEDGE_NONE TIMER_CC_CTRL_ICEDGE(3) +#define TIMER_CC_CTRL_ICEDGE_RISING 0 +#define TIMER_CC_CTRL_ICEDGE_FALLING 1 +#define TIMER_CC_CTRL_ICEDGE_BOTH 2 +#define TIMER_CC_CTRL_ICEDGE_NONE 3 #define TIMER_CC_CTRL_FILT (1 << 21) -#define TIMER_CC_CTRL_INSEL (1 << 20) +#define TIMER_CC_CTRL_INSEL (1 << 21) + + +#define TIMER_CC_CTRL_PRSSEL_SHIFT (16) +#define TIMER_CC_CTRL_PRSSEL_MASK (0xF << TIMER_CC_CTRL_PRSSEL_SHIFT) +#define TIMER_CC_CTRL_PRSSEL(v) \ + (((v) << TIMER_CC_CTRL_PRSSEL_SHIFT) & TIMER_CC_CTRL_PRSSEL_MASK) +#define TIMER_CC_CTRL_PRSSEL_PRSCHx(x) TIMER_CC_CTRL_PRSSEL(x) +#define TIMER_CC_CTRL_PRSSEL_PRSCH0 0 +#define TIMER_CC_CTRL_PRSSEL_PRSCH1 1 +#define TIMER_CC_CTRL_PRSSEL_PRSCH2 2 +#define TIMER_CC_CTRL_PRSSEL_PRSCH3 3 +#define TIMER_CC_CTRL_PRSSEL_PRSCH4 4 +#define TIMER_CC_CTRL_PRSSEL_PRSCH5 5 +#define TIMER_CC_CTRL_PRSSEL_PRSCH6 6 +#define TIMER_CC_CTRL_PRSSEL_PRSCH7 7 +#define TIMER_CC_CTRL_PRSSEL_PRSCH8 8 +#define TIMER_CC_CTRL_PRSSEL_PRSCH9 9 +#define TIMER_CC_CTRL_PRSSEL_PRSCH10 10 +#define TIMER_CC_CTRL_PRSSEL_PRSCH11 11 #define TIMER_CC_CTRL_CUFOA_SHIFT (12) #define TIMER_CC_CTRL_CUFOA_MASK (0x3 << TIMER_CC_CTRL_CUFOA_SHIFT) #define TIMER_CC_CTRL_CUFOA(v) \ (((v) << TIMER_CC_CTRL_CUFOA_SHIFT) & TIMER_CC_CTRL_CUFOA_MASK) -#define TIMER_CC_CTRL_CUFOA_NONE TIMER_CC_CTRL_CUFOA(0) -#define TIMER_CC_CTRL_CUFOA_TOGGLE TIMER_CC_CTRL_CUFOA(1) -#define TIMER_CC_CTRL_CUFOA_CLEAR TIMER_CC_CTRL_CUFOA(2) -#define TIMER_CC_CTRL_CUFOA_SET TIMER_CC_CTRL_CUFOA(3) +#define TIMER_CC_CTRL_CUFOA_NONE 0 +#define TIMER_CC_CTRL_CUFOA_TOGGLE 1 +#define TIMER_CC_CTRL_CUFOA_CLEAR 2 +#define TIMER_CC_CTRL_CUFOA_SET 3 #define TIMER_CC_CTRL_COFOA_SHIFT (10) #define TIMER_CC_CTRL_COFOA_MASK (0x3 << TIMER_CC_CTRL_COFOA_SHIFT) #define TIMER_CC_CTRL_COFOA(v) \ (((v) << TIMER_CC_CTRL_COFOA_SHIFT) & TIMER_CC_CTRL_COFOA_MASK) -#define TIMER_CC_CTRL_COFOA_NONE TIMER_CC_CTRL_COFOA(0) -#define TIMER_CC_CTRL_COFOA_TOGGLE TIMER_CC_CTRL_COFOA(1) -#define TIMER_CC_CTRL_COFOA_CLEAR TIMER_CC_CTRL_COFOA(2) -#define TIMER_CC_CTRL_COFOA_SET TIMER_CC_CTRL_COFOA(3) +#define TIMER_CC_CTRL_COFOA_NONE 0 +#define TIMER_CC_CTRL_COFOA_TOGGLE 1 +#define TIMER_CC_CTRL_COFOA_CLEAR 2 +#define TIMER_CC_CTRL_COFOA_SET 3 #define TIMER_CC_CTRL_CMOA_SHIFT (8) #define TIMER_CC_CTRL_CMOA_MASK (0x3 << TIMER_CC_CTRL_CMOA_SHIFT) #define TIMER_CC_CTRL_CMOA(v) \ (((v) << TIMER_CC_CTRL_CMOA_SHIFT) & TIMER_CC_CTRL_CMOA_MASK) -#define TIMER_CC_CTRL_CMOA_NONE TIMER_CC_CTRL_CMOA(0) -#define TIMER_CC_CTRL_CMOA_TOGGLE TIMER_CC_CTRL_CMOA(1) -#define TIMER_CC_CTRL_CMOA_CLEAR TIMER_CC_CTRL_CMOA(2) -#define TIMER_CC_CTRL_CMOA_SET TIMER_CC_CTRL_CMOA(3) +#define TIMER_CC_CTRL_CMOA_NONE 0 +#define TIMER_CC_CTRL_CMOA_TOGGLE 1 +#define TIMER_CC_CTRL_CMOA_CLEAR 2 +#define TIMER_CC_CTRL_CMOA_SET 3 #define TIMER_CC_CTRL_COIST (1 << 4) #define TIMER_CC_CTRL_OUTINV (1 << 2) @@ -302,10 +318,10 @@ #define TIMER_CC_CTRL_MODE_MASK (0x3 << TIMER_CC_CTRL_MODE_SHIFT) #define TIMER_CC_CTRL_MODE(v) \ (((v) << TIMER_CC_CTRL_MODE_SHIFT) & TIMER_CC_CTRL_MODE_MASK) -#define TIMER_CC_CTRL_MODE_OFF TIMER_CC_CTRL_MODE(0) -#define TIMER_CC_CTRL_MODE_INPUTCAPTURE TIMER_CC_CTRL_MODE(1) -#define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE TIMER_CC_CTRL_MODE(2) -#define TIMER_CC_CTRL_MODE_PWM TIMER_CC_CTRL_MODE(3) +#define TIMER_CC_CTRL_MODE_OFF 0 +#define TIMER_CC_CTRL_MODE_INPUTCAPTURE 1 +#define TIMER_CC_CTRL_MODE_OUTPUTCOMPARE 2 +#define TIMER_CC_CTRL_MODE_PWM 3 #define TIMER_CC_CTRL_MODE_INPUT_CAPTURE \ TIMER_CC_CTRL_MODE_INPUTCAPTURE @@ -314,6 +330,25 @@ /* TIMER_DTCTRL */ #define TIMER_DTCTRL_DTPRSEN (1 << 24) + +#define TIMER_DTCTRL_DTPRSSEL_SHIFT (4) +#define TIMER_DTCTRL_DTPRSSEL_MASK (0xF << TIMER_DTCTRL_DTPRSSEL_SHIFT) +#define TIMER_DTCTRL_DTPRSSEL(v) \ + (((v) << TIMER_DTCTRL_DTPRSSEL_SHIFT) & TIMER_DTCTRL_DTPRSSEL_MASK) +#define TIMER_DTCTRL_DTPRSSEL_PRSCHx(x) TIMER_DTCTRL_DTPRSSEL(x) +#define TIMER_DTCTRL_DTPRSSEL_PRSCH0 0 +#define TIMER_DTCTRL_DTPRSSEL_PRSCH1 1 +#define TIMER_DTCTRL_DTPRSSEL_PRSCH2 2 +#define TIMER_DTCTRL_DTPRSSEL_PRSCH3 3 +#define TIMER_DTCTRL_DTPRSSEL_PRSCH4 4 +#define TIMER_DTCTRL_DTPRSSEL_PRSCH5 5 +#define TIMER_DTCTRL_DTPRSSEL_PRSCH6 6 +#define TIMER_DTCTRL_DTPRSSEL_PRSCH7 7 +#define TIMER_DTCTRL_DTPRSSEL_PRSCH8 8 +#define TIMER_DTCTRL_DTPRSSEL_PRSCH9 9 +#define TIMER_DTCTRL_DTPRSSEL_PRSCH10 10 +#define TIMER_DTCTRL_DTPRSSEL_PRSCH11 11 + #define TIMER_DTCTRL_DTCINV (1 << 3) #define TIMER_DTCTRL_DTIPOL (1 << 2) #define TIMER_DTCTRL_DTDAS (1 << 1) @@ -335,17 +370,17 @@ #define TIMER_DTTIME_DTPRESC_MASK (0xF << TIMER_DTTIME_DTPRESC_SHIFT) #define TIMER_DTTIME_DTPRESC(v) \ (((v) << TIMER_DTTIME_DTPRESC_SHIFT) & TIMER_DTTIME_DTPRESC_MASK) -#define TIMER_DTTIME_DTPRESC_DIV1 TIMER_DTTIME_DTPRESC(0) -#define TIMER_DTTIME_DTPRESC_DIV2 TIMER_DTTIME_DTPRESC(1) -#define TIMER_DTTIME_DTPRESC_DIV4 TIMER_DTTIME_DTPRESC(2) -#define TIMER_DTTIME_DTPRESC_DIV8 TIMER_DTTIME_DTPRESC(3) -#define TIMER_DTTIME_DTPRESC_DIV16 TIMER_DTTIME_DTPRESC(4) -#define TIMER_DTTIME_DTPRESC_DIV32 TIMER_DTTIME_DTPRESC(5) -#define TIMER_DTTIME_DTPRESC_DIV64 TIMER_DTTIME_DTPRESC(6) -#define TIMER_DTTIME_DTPRESC_DIV128 TIMER_DTTIME_DTPRESC(7) -#define TIMER_DTTIME_DTPRESC_DIV256 TIMER_DTTIME_DTPRESC(8) -#define TIMER_DTTIME_DTPRESC_DIV512 TIMER_DTTIME_DTPRESC(8) -#define TIMER_DTTIME_DTPRESC_DIV1024 TIMER_DTTIME_DTPRESC(10) +#define TIMER_DTTIME_DTPRESC_DIV1 0 +#define TIMER_DTTIME_DTPRESC_DIV2 1 +#define TIMER_DTTIME_DTPRESC_DIV4 2 +#define TIMER_DTTIME_DTPRESC_DIV8 3 +#define TIMER_DTTIME_DTPRESC_DIV16 4 +#define TIMER_DTTIME_DTPRESC_DIV32 5 +#define TIMER_DTTIME_DTPRESC_DIV64 6 +#define TIMER_DTTIME_DTPRESC_DIV128 7 +#define TIMER_DTTIME_DTPRESC_DIV256 8 +#define TIMER_DTTIME_DTPRESC_DIV512 8 +#define TIMER_DTTIME_DTPRESC_DIV1024 10 #define TIMER_DTTIME_DTPRESC_NODIV TIMER_DTTIME_DTPRESC_DIV1 /* TIMER_DTFC */ @@ -358,38 +393,38 @@ #define TIMER_DTFC_DTFA_MASK (0x3 << TIMER_DTFC_DTFA_SHIFT) #define TIMER_DTFC_DTFA(v) \ (((v) << TIMER_DTFC_DTFA_SHIFT) & TIMER_DTFC_DTFA_MASK) -#define TIMER_DTFC_DTFA_NONE TIMER_DTFC_DTFA(0) -#define TIMER_DTFC_DTFA_INACTIVE TIMER_DTFC_DTFA(1) -#define TIMER_DTFC_DTFA_CLEAR TIMER_DTFC_DTFA(2) -#define TIMER_DTFC_DTFA_TRISTATE TIMER_DTFC_DTFA(3) +#define TIMER_DTFC_DTFA_NONE 0 +#define TIMER_DTFC_DTFA_INACTIVE 1 +#define TIMER_DTFC_DTFA_CLEAR 2 +#define TIMER_DTFC_DTFA_TRISTATE 3 #define TIMER_DTFC_DTPRS1FSEL_SHIFT (8) #define TIMER_DTFC_DTPRS1FSEL_MASK (0x3 << TIMER_DTFC_DTPRS1FSEL_SHIFT) #define TIMER_DTFC_DTPRS1FSEL(v) \ (((v) << TIMER_DTFC_DTPRS1FSEL_SHIFT) & TIMER_DTFC_DTPRS1FSEL_MASK) #define TIMER_DTFC_DTPRS1FSEL_PRSCHx(x) TIMER_DTFC_DTPRS1FSEL(x) -#define TIMER_DTFC_DTPRS1FSEL_PRSCH0 TIMER_DTFC_DTPRS1FSEL_PRSCHx(0) -#define TIMER_DTFC_DTPRS1FSEL_PRSCH1 TIMER_DTFC_DTPRS1FSEL_PRSCHx(1) -#define TIMER_DTFC_DTPRS1FSEL_PRSCH2 TIMER_DTFC_DTPRS1FSEL_PRSCHx(2) -#define TIMER_DTFC_DTPRS1FSEL_PRSCH3 TIMER_DTFC_DTPRS1FSEL_PRSCHx(3) -#define TIMER_DTFC_DTPRS1FSEL_PRSCH4 TIMER_DTFC_DTPRS1FSEL_PRSCHx(4) -#define TIMER_DTFC_DTPRS1FSEL_PRSCH5 TIMER_DTFC_DTPRS1FSEL_PRSCHx(5) -#define TIMER_DTFC_DTPRS1FSEL_PRSCH6 TIMER_DTFC_DTPRS1FSEL_PRSCHx(6) -#define TIMER_DTFC_DTPRS1FSEL_PRSCH7 TIMER_DTFC_DTPRS1FSEL_PRSCHx(7) +#define TIMER_DTFC_DTPRS1FSEL_PRSCH0 0 +#define TIMER_DTFC_DTPRS1FSEL_PRSCH1 1 +#define TIMER_DTFC_DTPRS1FSEL_PRSCH2 2 +#define TIMER_DTFC_DTPRS1FSEL_PRSCH3 3 +#define TIMER_DTFC_DTPRS1FSEL_PRSCH4 4 +#define TIMER_DTFC_DTPRS1FSEL_PRSCH5 5 +#define TIMER_DTFC_DTPRS1FSEL_PRSCH6 6 +#define TIMER_DTFC_DTPRS1FSEL_PRSCH7 7 -#define TIMER_DTFC_DTPRS0FSEL_SHIFT (0) +#define TIMER_DTFC_DTPRS0FSEL_SHIFT (8) #define TIMER_DTFC_DTPRS0FSEL_MASK (0x3 << TIMER_DTFC_DTPRS0FSEL_SHIFT) #define TIMER_DTFC_DTPRS0FSEL(v) \ (((v) << TIMER_DTFC_DTPRS0FSEL_SHIFT) & TIMER_DTFC_DTPRS0FSEL_MASK) #define TIMER_DTFC_DTPRS0FSEL_PRSCHx(x) TIMER_DTFC_DTPRS0FSEL(x) -#define TIMER_DTFC_DTPRS0FSEL_PRSCH0 TIMER_DTFC_DTPRS0FSEL_PRSCHx(0) -#define TIMER_DTFC_DTPRS0FSEL_PRSCH1 TIMER_DTFC_DTPRS0FSEL_PRSCHx(1) -#define TIMER_DTFC_DTPRS0FSEL_PRSCH2 TIMER_DTFC_DTPRS0FSEL_PRSCHx(2) -#define TIMER_DTFC_DTPRS0FSEL_PRSCH3 TIMER_DTFC_DTPRS0FSEL_PRSCHx(3) -#define TIMER_DTFC_DTPRS0FSEL_PRSCH4 TIMER_DTFC_DTPRS0FSEL_PRSCHx(4) -#define TIMER_DTFC_DTPRS0FSEL_PRSCH5 TIMER_DTFC_DTPRS0FSEL_PRSCHx(5) -#define TIMER_DTFC_DTPRS0FSEL_PRSCH6 TIMER_DTFC_DTPRS0FSEL_PRSCHx(6) -#define TIMER_DTFC_DTPRS0FSEL_PRSCH7 TIMER_DTFC_DTPRS0FSEL_PRSCHx(7) +#define TIMER_DTFC_DTPRS0FSEL_PRSCH0 0 +#define TIMER_DTFC_DTPRS0FSEL_PRSCH1 1 +#define TIMER_DTFC_DTPRS0FSEL_PRSCH2 2 +#define TIMER_DTFC_DTPRS0FSEL_PRSCH3 3 +#define TIMER_DTFC_DTPRS0FSEL_PRSCH4 4 +#define TIMER_DTFC_DTPRS0FSEL_PRSCH5 5 +#define TIMER_DTFC_DTPRS0FSEL_PRSCH6 6 +#define TIMER_DTFC_DTPRS0FSEL_PRSCH7 7 /* TIMER_DTOGEN */ #define TIMER_DTOGEN_DTOGCDTI2EN (1 << 5) @@ -514,6 +549,35 @@ #define TIMER2_CC2_CCVP TIMER_CC2_CCVP(TIMER2) #define TIMER2_CC2_CCVB TIMER_CC2_CCVB(TIMER2) +/* TIMER3 */ +#define TIMER3 TIMER3_BASE +#define TIMER3_CTRL TIMER_CTRL(TIMER3) +#define TIMER3_CMD TIMER_CMD(TIMER3) +#define TIMER3_STATUS TIMER_STATUS(TIMER3) +#define TIMER3_IEN TIMER_IEN(TIMER3) +#define TIMER3_IF TIMER_IF(TIMER3) +#define TIMER3_IFS TIMER_IFS(TIMER3) +#define TIMER3_IFC TIMER_IFC(TIMER3) +#define TIMER3_TOP TIMER_TOP(TIMER3) +#define TIMER3_TOPB TIMER_TOPB(TIMER3) +#define TIMER3_CNT TIMER_CNT(TIMER3) +#define TIMER3_ROUTE TIMER_ROUTE(TIMER3) + +#define TIMER3_CC0_CTRL TIMER_CC0_CTRL(TIMER3) +#define TIMER3_CC0_CCV TIMER_CC0_CCV(TIMER3) +#define TIMER3_CC0_CCVP TIMER_CC0_CCVP(TIMER3) +#define TIMER3_CC0_CCVB TIMER_CC0_CCVB(TIMER3) + +#define TIMER3_CC1_CTRL TIMER_CC1_CTRL(TIMER3) +#define TIMER3_CC1_CCV TIMER_CC1_CCV(TIMER3) +#define TIMER3_CC1_CCVP TIMER_CC1_CCVP(TIMER3) +#define TIMER3_CC1_CCVB TIMER_CC1_CCVB(TIMER3) + +#define TIMER3_CC2_CTRL TIMER_CC2_CTRL(TIMER3) +#define TIMER3_CC2_CCV TIMER_CC2_CCV(TIMER3) +#define TIMER3_CC2_CCVP TIMER_CC2_CCVP(TIMER3) +#define TIMER3_CC2_CCVB TIMER_CC2_CCVB(TIMER3) + /** @defgroup timer_ch Timer Channel Number @ingroup timer_defines @@ -543,8 +607,4 @@ void timer_set_top(uint32_t timer, uint32_t top); END_DECLS #endif -/** @cond */ -#else -#warning "timer_common_hglg.h should not be included explicitly, only via timer.h" -#endif -/** @endcond */ + diff --git a/include/libopencm3/efm32/common/uart_common.h b/include/libopencm3/efm32/common/uart_common.h new file mode 100644 index 00000000..b69617ba --- /dev/null +++ b/include/libopencm3/efm32/common/uart_common.h @@ -0,0 +1,100 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2015 Kuldeep Singh Dhaka + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_EFM32_UART_H +#define LIBOPENCM3_EFM32_UART_H + +/** + * USART and UART registers are equivalent except [in UART registers]: + * + * USART_CTRL: SYNC, CSMA, SMSDELAY, SSSEARLY, CSINV, CPOL and CPHA [1] + * USART_STATUS: MASTEREN [1] + * [1] Synchronous operation not available. + * USART_CTRL: MSBF (transmission LSB first only) + * USART_CTRL: AUTOCS (chip-select not available) + * USART_CTRL: SCMODE (SmartCard mode not available) + * USART_FRAME: DATABITS (limited framsize. 8-9 databits only) + * USART_IRCTRL: IREN (IrDA not available) + * (except DATABITS, all the above are 0) + * + * full text: (p495, "d0183_Rev1.10" EFM32LG-RM) + * - "18.3 Functional Description", + * - "18.4 Register Description" + * - "18.5 Register Map" + * + * use USART macro's to manipulate UART registers. + */ +#include +#include + +/* UART0 */ +#define UART0 UART0_BASE +#define UART0_CTRL USART_CTRL(UART0) +#define UART0_FRAME USART_FRAME(UART0) +#define UART0_TRIGCTRL USART_TRIGCTRL(UART0) +#define UART0_CMD USART_CMD(UART0) +#define UART0_STATUS USART_STATUS(UART0) +#define UART0_CLKDIV USART_CLKDIV(UART0) +#define UART0_RXDATAX USART_RXDATAX(UART0) +#define UART0_RXDATA USART_RXDATA(UART0) +#define UART0_RXDOUBLEX USART_RXDOUBLEX(UART0) +#define UART0_RXDOUBLE USART_RXDOUBLE(UART0) +#define UART0_RXDATAXP USART_RXDATAXP(UART0) +#define UART0_RXDOUBLEXP USART_RXDOUBLEXP(UART0) +#define UART0_TXDATAX USART_TXDATAX(UART0) +#define UART0_TXDATA USART_TXDATA(UART0) +#define UART0_TXDOUBLEX USART_TXDOUBLEX(UART0) +#define UART0_TXDOUBLE USART_TXDOUBLE(UART0) +#define UART0_IF USART_IF(UART0) +#define UART0_IFS USART_IFS(UART0) +#define UART0_IFC USART_IFC(UART0) +#define UART0_IEN USART_IEN(UART0) +#define UART0_IRCTRL USART_IRCTRL(UART0) +#define UART0_ROUTE USART_ROUTE(UART0) +#define UART0_INPUT USART_INPUT(UART0) +#define UART0_I2SCTRL USART_I2SCTRL(UART0) + +/* UART1 */ +#define UART1 UART1_BASE +#define UART1_CTRL USART_CTRL(UART1) +#define UART1_FRAME USART_FRAME(UART1) +#define UART1_TRIGCTRL USART_TRIGCTRL(UART1) +#define UART1_CMD USART_CMD(UART1) +#define UART1_STATUS USART_STATUS(UART1) +#define UART1_CLKDIV USART_CLKDIV(UART1) +#define UART1_RXDATAX USART_RXDATAX(UART1) +#define UART1_RXDATA USART_RXDATA(UART1) +#define UART1_RXDOUBLEX USART_RXDOUBLEX(UART1) +#define UART1_RXDOUBLE USART_RXDOUBLE(UART1) +#define UART1_RXDATAXP USART_RXDATAXP(UART1) +#define UART1_RXDOUBLEXP USART_RXDOUBLEXP(UART1) +#define UART1_TXDATAX USART_TXDATAX(UART1) +#define UART1_TXDATA USART_TXDATA(UART1) +#define UART1_TXDOUBLEX USART_TXDOUBLEX(UART1) +#define UART1_TXDOUBLE USART_TXDOUBLE(UART1) +#define UART1_IF USART_IF(UART1) +#define UART1_IFS USART_IFS(UART1) +#define UART1_IFC USART_IFC(UART1) +#define UART1_IEN USART_IEN(UART1) +#define UART1_IRCTRL USART_IRCTRL(UART1) +#define UART1_ROUTE USART_ROUTE(UART1) +#define UART1_INPUT USART_INPUT(UART1) +#define UART1_I2SCTRL USART_I2SCTRL(UART1) + +#endif diff --git a/include/libopencm3/efm32/common/usart_common.h b/include/libopencm3/efm32/common/usart_common.h new file mode 100644 index 00000000..b3b3f54b --- /dev/null +++ b/include/libopencm3/efm32/common/usart_common.h @@ -0,0 +1,512 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2015 Kuldeep Singh Dhaka + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_EFM32_USART_H +#define LIBOPENCM3_EFM32_USART_H + +#include +#include + +#define USART_CTRL(base) MMIO32((base) + 0x000) +#define USART_FRAME(base) MMIO32((base) + 0x004) +#define USART_TRIGCTRL(base) MMIO32((base) + 0x008) +#define USART_CMD(base) MMIO32((base) + 0x00C) +#define USART_STATUS(base) MMIO32((base) + 0x010) +#define USART_CLKDIV(base) MMIO32((base) + 0x014) +#define USART_RXDATAX(base) MMIO32((base) + 0x018) +#define USART_RXDATA(base) MMIO32((base) + 0x01C) +#define USART_RXDOUBLEX(base) MMIO32((base) + 0x020) +#define USART_RXDOUBLE(base) MMIO32((base) + 0x024) +#define USART_RXDATAXP(base) MMIO32((base) + 0x028) +#define USART_RXDOUBLEXP(base) MMIO32((base) + 0x02C) +#define USART_TXDATAX(base) MMIO32((base) + 0x030) +#define USART_TXDATA(base) MMIO32((base) + 0x034) +#define USART_TXDOUBLEX(base) MMIO32((base) + 0x038) +#define USART_TXDOUBLE(base) MMIO32((base) + 0x03C) +#define USART_IF(base) MMIO32((base) + 0x040) +#define USART_IFS(base) MMIO32((base) + 0x044) +#define USART_IFC(base) MMIO32((base) + 0x048) +#define USART_IEN(base) MMIO32((base) + 0x04C) +#define USART_IRCTRL(base) MMIO32((base) + 0x050) +#define USART_ROUTE(base) MMIO32((base) + 0x054) +#define USART_INPUT(base) MMIO32((base) + 0x058) +#define USART_I2SCTRL(base) MMIO32((base) + 0x05C) + +/* USART_CTRL */ +#define USART_CTRL_SMSDELAY (1 << 31) +#define USART_CTRL_MVDIS (1 << 30) +#define USART_CTRL_AUTOTX (1 << 29) +#define USART_CTRL_BYTESWAP (1 << 28) + +#define USART_CTRL_TXDELAY_SHIFT (26) +#define USART_CTRL_TXDELAY_MASK (0x3 << USART_CTRL_TXDELAY_SHIFT) +#define USART_CTRL_TXDELAY(v) \ + (((v) << USART_CTRL_TXDELAY_SHIFT) & USART_CTRL_TXDELAY_MASK) +#define USART_CTRL_TXDELAY_NONE 0 +#define USART_CTRL_TXDELAY_SINGLE 1 +#define USART_CTRL_TXDELAY_DOUBLE 2 +#define USART_CTRL_TXDELAY_TRIPLE 3 + +#define USART_CTRL_SSSEARLY (1 << 25) +#define USART_CTRL_ERRSTX (1 << 24) +#define USART_CTRL_ERRSRX (1 << 23) +#define USART_CTRL_ERRSDMA (1 << 22) +#define USART_CTRL_BIT8DV (1 << 21) +#define USART_CTRL_SKIPPERRF (1 << 20) +#define USART_CTRL_SCRETRANS (1 << 19) +#define USART_CTRL_SCMODE (1 << 18) +#define USART_CTRL_AUTOTRI (1 << 17) +#define USART_CTRL_AUTOCS (1 << 16) +#define USART_CTRL_CSINV (1 << 15) +#define USART_CTRL_TXINV (1 << 14) +#define USART_CTRL_RXINV (1 << 13) +#define USART_CTRL_TXBIL (1 << 12) +#define USART_CTRL_CSMA (1 << 11) +#define USART_CTRL_MSBF (1 << 10) +#define USART_CTRL_CLKPHA (1 << 9) +#define USART_CTRL_CLKPOL (1 << 8) + +#define USART_CTRL_OVS_SHIFT (5) +#define USART_CTRL_OVS_MASK (0x3 << USART_CTRL_OVS_SHIFT) +#define USART_CTRL_OVS(v) \ + (((v) << USART_CTRL_OVS_SHIFT) & USART_CTRL_OVS_MASK) +#define USART_CTRL_OVS_X16 0 +#define USART_CTRL_OVS_X8 1 +#define USART_CTRL_OVS_X6 2 +#define USART_CTRL_OVS_X4 3 + +#define USART_CTRL_MPAB (1 << 4) +#define USART_CTRL_MPM (1 << 3) +#define USART_CTRL_CCEN (1 << 2) +#define USART_CTRL_LOOPBK (1 << 1) +#define USART_CTRL_SYNC (1 << 0) + +/* USART_FRAME */ + +#define USART_FRAME_STOPBITS_SHIFT (12) +#define USART_FRAME_STOPBITS_MASK (0x3 << USART_FRAME_STOPBITS_SHIFT) +#define USART_FRAME_STOPBITS(v) \ + (((v) << USART_FRAME_STOPBITS_SHIFT) & USART_FRAME_STOPBITS_MASK) +#define USART_FRAME_STOPBITS_HALF 0 +#define USART_FRAME_STOPBITS_ONE 1 +#define USART_FRAME_STOPBITS_ONEANDAHALF 2 +#define USART_FRAME_STOPBITS_ONE_AND_A_HALF \ + USART_FRAME_STOPBITS_ONEANDAHALF +#define USART_FRAME_STOPBITS_TWO 3 + +#define USART_FRAME_PARITY_SHIFT (8) +#define USART_FRAME_PARITY_MASK (0x3 << USART_FRAME_PARITY_SHIFT) +#define USART_FRAME_PARITY(v) \ + (((v) << USART_FRAME_PARITY_SHIFT) & USART_FRAME_PARITY_MASK) +#define USART_FRAME_PARITY_NONE 0 +#define USART_FRAME_PARITY_EVEN 2 +#define USART_FRAME_PARITY_ODD 3 + +#define USART_FRAME_DATABITS_SHIFT (0) +#define USART_FRAME_DATABITS_MASK (0xF << USART_FRAME_DATABITS_SHIFT) +#define USART_FRAME_DATABITS(v) \ + (((v) << USART_FRAME_DATABITS_SHIFT) & USART_FRAME_DATABITS_MASK) +#define USART_FRAME_DATABITS_FOUR 1 +#define USART_FRAME_DATABITS_FIVE 2 +#define USART_FRAME_DATABITS_SIX 3 +#define USART_FRAME_DATABITS_SEVEN 4 +#define USART_FRAME_DATABITS_EIGHT 5 +#define USART_FRAME_DATABITS_NINE 6 +#define USART_FRAME_DATABITS_TEN 7 +#define USART_FRAME_DATABITS_ELEVEN 8 +#define USART_FRAME_DATABITS_TWELVE 9 +#define USART_FRAME_DATABITS_THIRTEEN 10 +#define USART_FRAME_DATABITS_FOURTEEN 11 +#define USART_FRAME_DATABITS_FIFTEEN 12 +#define USART_FRAME_DATABITS_SIXTEEN 13 + +/* USART_TRIGCTRL */ +#define USART_TRIGCTRL_AUTOTXTEN (1 << 6) +#define USART_TRIGCTRL_TXTEN (1 << 5) +#define USART_TRIGCTRL_RXTEN (1 << 4) + +#define USART_TRIGCTRL_TSEL_SHIFT (8) +#define USART_TRIGCTRL_TSEL_MASK (0x3 << USART_TRIGCTRL_TSEL_SHIFT) +#define USART_TRIGCTRL_TSEL_PRSCHx(v) \ + (((v) << USART_TRIGCTRL_TSEL_SHIFT) & USART_TRIGCTRL_TSEL_MASK) +#define USART_TRIGCTRL_TSEL_PRSCH0 0 +#define USART_TRIGCTRL_TSEL_PRSCH1 1 +#define USART_TRIGCTRL_TSEL_PRSCH2 2 +#define USART_TRIGCTRL_TSEL_PRSCH3 3 +#define USART_TRIGCTRL_TSEL_PRSCH4 4 +#define USART_TRIGCTRL_TSEL_PRSCH5 5 +#define USART_TRIGCTRL_TSEL_PRSCH6 6 +#define USART_TRIGCTRL_TSEL_PRSCH7 7 + +/* USART_CMD */ +#define USART_CMD_CLEARRX (1 << 11) +#define USART_CMD_CLEARTX (1 << 10) +#define USART_CMD_TXTRIDIS (1 << 9) +#define USART_CMD_TXTRIEN (1 << 8) +#define USART_CMD_RXBLOCKDIS (1 << 7) +#define USART_CMD_RXBLOCKEN (1 << 6) +#define USART_CMD_MASTERDIS (1 << 5) +#define USART_CMD_MASTEREN (1 << 4) +#define USART_CMD_TXDIS (1 << 3) +#define USART_CMD_TXEN (1 << 2) +#define USART_CMD_RXDIS (1 << 1) +#define USART_CMD_RXEN (1 << 0) + +/* USART_STATUS */ +#define USART_STATUS_RXFULLRIGHT (1 << 12) +#define USART_STATUS_RXDATAVRIGHT (1 << 11) +#define USART_STATUS_TXBSRIGHT (1 << 10) +#define USART_STATUS_TXBDRIGHT (1 << 9) +#define USART_STATUS_RXFULL (1 << 8) +#define USART_STATUS_RXDATAV (1 << 7) +#define USART_STATUS_TXBL (1 << 6) +#define USART_STATUS_TXC (1 << 5) +#define USART_STATUS_TXTRI (1 << 4) +#define USART_STATUS_RXBLOCK (1 << 3) +#define USART_STATUS_MASTER (1 << 2) +#define USART_STATUS_TXENS (1 << 1) +#define USART_STATUS_RXENS (1 << 0) + +/* USART_CLKDIV */ +#define USART_CLKDIV_DIV_SHIFT (6) +#define USART_CLKDIV_DIV_MASK (0x7FFF << USART_CLKDIV_DIV_SHIFT) +#define USART_CLKDIV_DIV(v) \ + (((v) << USART_CLKDIV_DIV_SHIFT) & USART_CLKDIV_DIV_MASK) + +/* USART_RXDATAX */ +#define USART_RXDATAX_FERR (1 << 15) +#define USART_RXDATAX_PERR (1 << 14) + +#define USART_RXDATAX_RXDATA_SHIFT (0) +#define USART_RXDATAX_RXDATA_MASK (0x1FF << USART_RXDATAX_RXDATA_SHIFT) + +/* USART_RXDOUBLEX */ +#define USART_RXDOUBLEX_FERR1 (1 << 31) +#define USART_RXDOUBLEX_PERR1 (1 << 30) + +#define USART_RXDOUBLEX_RXDATA1_SHIFT (16) +#define USART_RXDOUBLEX_RXDATA1_MASK \ + (0x1FF << USART_RXDOUBLEX_RXDATA1_SHIFT) + +#define USART_RXDOUBLEX_FERR0 (1 << 15) +#define USART_RXDOUBLEX_PERR0 (1 << 14) + +#define USART_RXDOUBLEX_RXDATA0_SHIFT (0) +#define USART_RXDOUBLEX_RXDATA0_MASK \ + (0x1FF << USART_RXDOUBLEX_RXDATA1_SHIFT) + +/* USART_RXDOUBLE */ +#define USART_RXDOUBLE_RXDATA1_SHIFT (8) +#define USART_RXDOUBLE_RXDATA1_MASK (0xFF << USART_RXDOUBLE_RXDATA1_SHIFT) + +#define USART_RXDOUBLE_RXDATA0_SHIFT (0) +#define USART_RXDOUBLE_RXDATA0_MASK (0xFF << USART_RXDOUBLE_RXDATA0_SHIFT) + +/* USART_RXDATAXP */ +#define USART_RXDATAXP_FERRP (1 << 15) +#define USART_RXDATAXP_PERRP (1 << 14) + +#define USART_RXDATAXP_RXDATAP_SHIFT (0) +#define USART_RXDATAXP_RXDATAP_MASK (0x1FF << USART_RXDATAXP_RXDATAP_SHIFT) + +/* USART_RXDOUBLEXP */ +#define USART_RXDOUBLEXP_FERR1 (1 << 31) +#define USART_RXDOUBLEXP_PERR1 (1 << 30) + +#define USART_RXDOUBLEXP_RXDATA1_SHIFT (16) +#define USART_RXDOUBLEXP_RXDATA1_MASK \ + (0x1FF << USART_RXDOUBLEXP_RXDATA1_SHIFT) + +#define USART_RXDOUBLEXP_FERR0 (1 << 15) +#define USART_RXDOUBLEXP_PERR0 (1 << 14) + +#define USART_RXDOUBLEXP_RXDATA0_SHIFT (0) +#define USART_RXDOUBLEXP_RXDATA0_MASK \ + (0x1FF << USART_RXDOUBLEXP_RXDATA1_SHIFT) + +/* USART_TXDATAX */ +#define USART_TXDATAX_RXENAT (1 << 15) +#define USART_TXDATAX_TXDISAT (1 << 14) +#define USART_TXDATAX_TXBREAK (1 << 13) +#define USART_TXDATAX_TXTRIAT (1 << 12) +#define USART_TXDATAX_UBRXAT (1 << 11) + +#define USART_TXDATAX_TXDATAX_SHIFT (0) +#define USART_TXDATAX_TXDATAX_MASK (0x1FF << USART_TXDATAX_TXDATAX_SHIFT) + +/* USART_TXDOUBLEX */ +#define USART_TXDOUBLEX_RXENAT1 (1 << 31) +#define USART_TXDOUBLEX_TXDISAT1 (1 << 30) +#define USART_TXDOUBLEX_TXBREAK1 (1 << 29) +#define USART_TXDOUBLEX_TXTRIAT1 (1 << 28) +#define USART_TXDOUBLEX_UBRXAT1 (1 << 27) + +#define USART_TXDOUBLEX_TXDATA1_SHIFT (16) +#define USART_TXDOUBLEX_TXDATA1_MASK \ + (0x1FF << USART_TXDOUBLEX_TXDATA1_SHIFT) + +#define USART_TXDOUBLEX_RXENAT0 (1 << 15) +#define USART_TXDOUBLEX_TXDISAT0 (1 << 14) +#define USART_TXDOUBLEX_TXBREAK0 (1 << 13) +#define USART_TXDOUBLEX_TXTRIAT0 (1 << 12) +#define USART_TXDOUBLEX_UBRXAT0 (1 << 11) + +#define USART_TXDOUBLEX_TXDATA0_SHIFT (0) +#define USART_TXDOUBLEX_TXDATA0_MASK \ + (0x1FF << USART_TXDOUBLEX_TXDATA0_SHIFT) + +/* USART_TXDOUBLE */ +#define USART_TXDOUBLE_TXDATA1_SHIFT (8) +#define USART_TXDOUBLE_TXDATA1_MASK (0xFF << USART_TXDOUBLE_TXDATA1_SHIFT) + +#define USART_TXDOUBLE_TXDATA0_SHIFT (0) +#define USART_TXDOUBLE_TXDATA0_MASK (0xFF << USART_TXDOUBLE_TXDATA0_SHIFT) + +/* USART_IF */ +#define USART_IF_CCF (1 << 12) +#define USART_IF_SSM (1 << 11) +#define USART_IF_MPAF (1 << 10) +#define USART_IF_FERR (1 << 9) +#define USART_IF_PERR (1 << 8) +#define USART_IF_TXUF (1 << 7) +#define USART_IF_TXOF (1 << 6) +#define USART_IF_RXUF (1 << 5) +#define USART_IF_RXOF (1 << 4) +#define USART_IF_RXFULL (1 << 3) +#define USART_IF_RXDATAV (1 << 2) +#define USART_IF_TXBL (1 << 1) +#define USART_IF_TXC (1 << 0) + +/* USART_IFS */ +#define USART_IFS_CCF (1 << 12) +#define USART_IFS_SSM (1 << 11) +#define USART_IFS_MPAF (1 << 10) +#define USART_IFS_FERR (1 << 9) +#define USART_IFS_PERR (1 << 8) +#define USART_IFS_TXUF (1 << 7) +#define USART_IFS_TXOF (1 << 6) +#define USART_IFS_RXUF (1 << 5) +#define USART_IFS_RXOF (1 << 4) +#define USART_IFS_RXFULL (1 << 3) +#define USART_IFS_RXDATAV (1 << 2) +#define USART_IFS_TXBL (1 << 1) +#define USART_IFS_TXC (1 << 0) + +/* USART_IFC */ +#define USART_IFC_CCF (1 << 12) +#define USART_IFC_SSM (1 << 11) +#define USART_IFC_MPAF (1 << 10) +#define USART_IFC_FERR (1 << 9) +#define USART_IFC_PERR (1 << 8) +#define USART_IFC_TXUF (1 << 7) +#define USART_IFC_TXOF (1 << 6) +#define USART_IFC_RXUF (1 << 5) +#define USART_IFC_RXOF (1 << 4) +#define USART_IFC_RXFULL (1 << 3) +#define USART_IFC_RXDATAV (1 << 2) +#define USART_IFC_TXBL (1 << 1) +#define USART_IFC_TXC (1 << 0) + +/* USART_IEN */ +#define USART_IEN_CCF (1 << 12) +#define USART_IEN_SSM (1 << 11) +#define USART_IEN_MPAF (1 << 10) +#define USART_IEN_FERR (1 << 9) +#define USART_IEN_PERR (1 << 8) +#define USART_IEN_TXUF (1 << 7) +#define USART_IEN_TXOF (1 << 6) +#define USART_IEN_RXUF (1 << 5) +#define USART_IEN_RXOF (1 << 4) +#define USART_IEN_RXFULL (1 << 3) +#define USART_IEN_RXDATAV (1 << 2) +#define USART_IEN_TXBL (1 << 1) +#define USART_IEN_TXC (1 << 0) + +/* USART_IRCTRL */ +#define USART_IRCTRL_IRPRSEN (1 << 7) + +#define USART_IRCTRL_IRPRSSEL_SHIFT (4) +#define USART_IRCTRL_IRPRSSEL_MASK (0x7 << USART_IRCTRL_IRPRSSEL_SHIFT) +#define USART_IRCTRL_IRPRSSEL(v) \ + (((v) << USART_IRCTRL_IRPRSSEL_SHIFT) & USART_IRCTRL_IRPRSSEL_MASK) +#define USART_IRCTRL_IRPRSSEL_PRSCHx(x) USART_IRCTRL_IRPRSSEL(x) +#define USART_IRCTRL_IRPRSSEL_PRSCH0 0 +#define USART_IRCTRL_IRPRSSEL_PRSCH1 1 +#define USART_IRCTRL_IRPRSSEL_PRSCH2 2 +#define USART_IRCTRL_IRPRSSEL_PRSCH3 3 +#define USART_IRCTRL_IRPRSSEL_PRSCH4 4 +#define USART_IRCTRL_IRPRSSEL_PRSCH5 5 +#define USART_IRCTRL_IRPRSSEL_PRSCH6 6 +#define USART_IRCTRL_IRPRSSEL_PRSCH7 7 + +#define USART_IRCTRL_IRFILT (1 << 3) + +#define USART_IRCTRL_IRPW_SHIFT (1) +#define USART_IRCTRL_IRPW_MASK (0x3 << USART_IRCTRL_IRPW_SHIFT) +#define USART_IRCTRL_IRPW(v) \ + (((v) << USART_IRCTRL_IRPW_SHIFT) & USART_IRCTRL_IRPW_MASK) +#define USART_IRCTRL_IRPW_ONE 0 +#define USART_IRCTRL_IRPW_TWO 1 +#define USART_IRCTRL_IRPW_THREE 2 +#define USART_IRCTRL_IRPW_FOUR 3 + +#define USART_IRCTRL_IREN (1 << 0) + +/* USART_ROUTE */ +#define USART_ROUTE_LOCATION_SHIFT (8) +#define USART_ROUTE_LOCATION_MASK (0x7 << USART_ROUTE_LOCATION_SHIFT) +#define USART_ROUTE_LOCATION(v) \ + (((v) << USART_ROUTE_LOCATION_SHIFT) & USART_ROUTE_LOCATION_MASK) +#define USART_ROUTE_LOCATION_LOCx(x) USART_ROUTE_LOCATION(x) +#define USART_ROUTE_LOCATION_LOC0 0 +#define USART_ROUTE_LOCATION_LOC1 1 +#define USART_ROUTE_LOCATION_LOC2 2 +#define USART_ROUTE_LOCATION_LOC3 3 +#define USART_ROUTE_LOCATION_LOC4 4 +#define USART_ROUTE_LOCATION_LOC5 5 + +#define USART_ROUTE_CLKPEN (1 << 3) +#define USART_ROUTE_CSPEN (1 << 2) +#define USART_ROUTE_TXPEN (1 << 1) +#define USART_ROUTE_RXPEN (1 << 0) + +/* USART_INPUT */ +#define USART_INPUT_RXPRS (1 << 4) + +#define USART_INPUT_RXPRSSEL_SHIFT (0) +#define USART_INPUT_RXPRSSEL_MASK (0xF << USART_INPUT_RXPRSSEL_SHIFT) +#define USART_INPUT_RXPRSSEL(v) \ + (((v) << USART_INPUT_RXPRSSEL_SHIFT) & USART_INPUT_RXPRSSEL_MASK) +#define USART_INPUT_RXPRSSEL_PRSCHx(x) USART_INPUT_RXPRSSEL(x) +#define USART_INPUT_RXPRSSEL_PRSCH0 0 +#define USART_INPUT_RXPRSSEL_PRSCH1 1 +#define USART_INPUT_RXPRSSEL_PRSCH2 2 +#define USART_INPUT_RXPRSSEL_PRSCH3 3 +#define USART_INPUT_RXPRSSEL_PRSCH4 4 +#define USART_INPUT_RXPRSSEL_PRSCH5 5 +#define USART_INPUT_RXPRSSEL_PRSCH6 6 +#define USART_INPUT_RXPRSSEL_PRSCH7 7 +#define USART_INPUT_RXPRSSEL_PRSCH8 8 +#define USART_INPUT_RXPRSSEL_PRSCH9 9 +#define USART_INPUT_RXPRSSEL_PRSCH10 10 +#define USART_INPUT_RXPRSSEL_PRSCH11 11 + +/* USART_I2SCTRL */ +#define USART_I2SCTRL_FORMAT_SHIFT (8) +#define USART_I2SCTRL_FORMAT_MASK (0x7 << USART_I2SCTRL_FORMAT_SHIFT) +#define USART_I2SCTRL_FORMAT(v) \ + (((v) << USART_I2SCTRL_FORMAT_SHIFT) & USART_I2SCTRL_FORMAT_MASK) +#define USART_I2SCTRL_FORMAT_W32D32 0 +#define USART_I2SCTRL_FORMAT_W32D24M 1 +#define USART_I2SCTRL_FORMAT_W32D24 2 +#define USART_I2SCTRL_FORMAT_W32D16 3 +#define USART_I2SCTRL_FORMAT_W32D8 4 +#define USART_I2SCTRL_FORMAT_W16D16 5 +#define USART_I2SCTRL_FORMAT_W16D8 6 +#define USART_I2SCTRL_FORMAT_W8D8 7 + +#define USART_I2SCTRL_DELAY (1 << 4) +#define USART_I2SCTRL_DMASPLIT (1 << 3) +#define USART_I2SCTRL_JUSTIFY (1 << 2) +#define USART_I2SCTRL_MONO (1 << 1) +#define USART_I2SCTRL_EN (1 << 0) + +/* USART0 */ +#define USART0 USART0_BASE +#define USART0_CTRL USART_CTRL(USART0) +#define USART0_FRAME USART_FRAME(USART0) +#define USART0_TRIGCTRL USART_TRIGCTRL(USART0) +#define USART0_CMD USART_CMD(USART0) +#define USART0_STATUS USART_STATUS(USART0) +#define USART0_CLKDIV USART_CLKDIV(USART0) +#define USART0_RXDATAX USART_RXDATAX(USART0) +#define USART0_RXDATA USART_RXDATA(USART0) +#define USART0_RXDOUBLEX USART_RXDOUBLEX(USART0) +#define USART0_RXDOUBLE USART_RXDOUBLE(USART0) +#define USART0_RXDATAXP USART_RXDATAXP(USART0) +#define USART0_RXDOUBLEXP USART_RXDOUBLEXP(USART0) +#define USART0_TXDATAX USART_TXDATAX(USART0) +#define USART0_TXDATA USART_TXDATA(USART0) +#define USART0_TXDOUBLEX USART_TXDOUBLEX(USART0) +#define USART0_TXDOUBLE USART_TXDOUBLE(USART0) +#define USART0_IF USART_IF(USART0) +#define USART0_IFS USART_IFS(USART0) +#define USART0_IFC USART_IFC(USART0) +#define USART0_IEN USART_IEN(USART0) +#define USART0_IRCTRL USART_IRCTRL(USART0) +#define USART0_ROUTE USART_ROUTE(USART0) +#define USART0_INPUT USART_INPUT(USART0) +#define USART0_I2SCTRL USART_I2SCTRL(USART0) + +/* USART1 */ +#define USART1 USART1_BASE +#define USART1_CTRL USART_CTRL(USART1) +#define USART1_FRAME USART_FRAME(USART1) +#define USART1_TRIGCTRL USART_TRIGCTRL(USART1) +#define USART1_CMD USART_CMD(USART1) +#define USART1_STATUS USART_STATUS(USART1) +#define USART1_CLKDIV USART_CLKDIV(USART1) +#define USART1_RXDATAX USART_RXDATAX(USART1) +#define USART1_RXDATA USART_RXDATA(USART1) +#define USART1_RXDOUBLEX USART_RXDOUBLEX(USART1) +#define USART1_RXDOUBLE USART_RXDOUBLE(USART1) +#define USART1_RXDATAXP USART_RXDATAXP(USART1) +#define USART1_RXDOUBLEXP USART_RXDOUBLEXP(USART1) +#define USART1_TXDATAX USART_TXDATAX(USART1) +#define USART1_TXDATA USART_TXDATA(USART1) +#define USART1_TXDOUBLEX USART_TXDOUBLEX(USART1) +#define USART1_TXDOUBLE USART_TXDOUBLE(USART1) +#define USART1_IF USART_IF(USART1) +#define USART1_IFS USART_IFS(USART1) +#define USART1_IFC USART_IFC(USART1) +#define USART1_IEN USART_IEN(USART1) +#define USART1_IRCTRL USART_IRCTRL(USART1) +#define USART1_ROUTE USART_ROUTE(USART1) +#define USART1_INPUT USART_INPUT(USART1) +#define USART1_I2SCTRL USART_I2SCTRL(USART1) + +/* USART2 */ +#define USART2 USART2_BASE +#define USART2_CTRL USART_CTRL(USART2) +#define USART2_FRAME USART_FRAME(USART2) +#define USART2_TRIGCTRL USART_TRIGCTRL(USART2) +#define USART2_CMD USART_CMD(USART2) +#define USART2_STATUS USART_STATUS(USART2) +#define USART2_CLKDIV USART_CLKDIV(USART2) +#define USART2_RXDATAX USART_RXDATAX(USART2) +#define USART2_RXDATA USART_RXDATA(USART2) +#define USART2_RXDOUBLEX USART_RXDOUBLEX(USART2) +#define USART2_RXDOUBLE USART_RXDOUBLE(USART2) +#define USART2_RXDATAXP USART_RXDATAXP(USART2) +#define USART2_RXDOUBLEXP USART_RXDOUBLEXP(USART2) +#define USART2_TXDATAX USART_TXDATAX(USART2) +#define USART2_TXDATA USART_TXDATA(USART2) +#define USART2_TXDOUBLEX USART_TXDOUBLEX(USART2) +#define USART2_TXDOUBLE USART_TXDOUBLE(USART2) +#define USART2_IF USART_IF(USART2) +#define USART2_IFS USART_IFS(USART2) +#define USART2_IFC USART_IFC(USART2) +#define USART2_IEN USART_IEN(USART2) +#define USART2_IRCTRL USART_IRCTRL(USART2) +#define USART2_ROUTE USART_ROUTE(USART2) +#define USART2_INPUT USART_INPUT(USART2) +#define USART2_I2SCTRL USART_I2SCTRL(USART2) + +#endif + diff --git a/include/libopencm3/efm32/common/usb_common.h b/include/libopencm3/efm32/common/usb_common.h new file mode 100644 index 00000000..891edbfb --- /dev/null +++ b/include/libopencm3/efm32/common/usb_common.h @@ -0,0 +1,369 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2015 Kuldeep Singh Dhaka + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_EFM32_USB_H +#define LIBOPENCM3_EFM32_USB_H + +#include +#include + +#define USB_CTRL MMIO32(USB_BASE + 0x000) +#define USB_STATUS MMIO32(USB_BASE + 0x004) +#define USB_IF MMIO32(USB_BASE + 0x008) +#define USB_IFS MMIO32(USB_BASE + 0x00C) +#define USB_IFC MMIO32(USB_BASE + 0x010) +#define USB_IEN MMIO32(USB_BASE + 0x014) +#define USB_ROUTE MMIO32(USB_BASE + 0x018) + +/* USB_CTRL */ +#define USB_CTRL_DMPUAP (1 << 1) + +/* USB_ROUTE */ +#define USB_ROUTE_DMPUPEN (1 << 2) +#define USB_ROUTE_VBUSENPEN (1 << 1) +#define USB_ROUTE_PHYPEN (1 << 0) + +/* Core Global Control and Status Registers */ +#define USB_OTG_BASE (USB_BASE + 0x3C000) +#define USB_GOTGCTL MMIO32(USB_OTG_BASE + 0x000) +#define USB_GOTGINT MMIO32(USB_OTG_BASE + 0x004) +#define USB_GAHBCFG MMIO32(USB_OTG_BASE + 0x008) +#define USB_GUSBCFG MMIO32(USB_OTG_BASE + 0x00C) +#define USB_GRSTCTL MMIO32(USB_OTG_BASE + 0x010) +#define USB_GINTSTS MMIO32(USB_OTG_BASE + 0x014) +#define USB_GINTMSK MMIO32(USB_OTG_BASE + 0x018) +#define USB_GRXSTSR MMIO32(USB_OTG_BASE + 0x01C) +#define USB_GRXSTSP MMIO32(USB_OTG_BASE + 0x020) +#define USB_GRXFSIZ MMIO32(USB_OTG_BASE + 0x024) +#define USB_GNPTXFSIZ MMIO32(USB_OTG_BASE + 0x028) +#define USB_GNPTXSTS MMIO32(USB_OTG_BASE + 0x02C) +#define USB_GDFIFOCFG MMIO32(USB_OTG_BASE + 0x05C) +#define USB_HPTXFSIZ MMIO32(USB_OTG_BASE + 0x100) +#define USB_DIEPTXF(x) \ + MMIO32(USB_OTG_BASE + 0x104 + (4 * ((x) - 1))) + +/* Host-mode Control and Status Registers */ +#define USB_HCFG MMIO32(USB_OTG_BASE + 0x400) +#define USB_HFIR MMIO32(USB_OTG_BASE + 0x404) +#define USB_HFNUM MMIO32(USB_OTG_BASE + 0x408) +#define USB_HPTXSTS MMIO32(USB_OTG_BASE + 0x410) +#define USB_HAINT MMIO32(USB_OTG_BASE + 0x414) +#define USB_HAINTMSK MMIO32(USB_OTG_BASE + 0x418) +#define USB_HPRT MMIO32(USB_OTG_BASE + 0x440) +#define USB_HCx_CHAR(x) \ + MMIO32(USB_OTG_BASE + 0x500 + ((x) * 0x20)) +#define USB_HCx_INT(x) \ + MMIO32(USB_OTG_BASE + 0x508 + ((x) * 0x20)) +#define USB_HCx_INTMSK(x) \ + MMIO32(USB_OTG_BASE + 0x50C + ((x) * 0x20)) +#define USB_HCx_TSIZ(x) \ + MMIO32(USB_OTG_BASE + 0x510 + ((x) * 0x20)) +#define USB_HCx_DMAADDR(x) \ + MMIO32(USB_OTG_BASE + 0x514 + ((x) * 0x20)) + +/* Device-mode Control and Status Registers */ +#define USB_DCFG MMIO32(USB_OTG_BASE + 0x800) +#define USB_DCTL MMIO32(USB_OTG_BASE + 0x804) +#define USB_DSTS MMIO32(USB_OTG_BASE + 0x808) +#define USB_DIEPMSK MMIO32(USB_OTG_BASE + 0x810) +#define USB_DOEPMSK MMIO32(USB_OTG_BASE + 0x814) +#define USB_DAINT MMIO32(USB_OTG_BASE + 0x818) +#define USB_DAINTMSK MMIO32(USB_OTG_BASE + 0x81C) +#define USB_DVBUSDIS MMIO32(USB_OTG_BASE + 0x828) +#define USB_DVBUSPULSE MMIO32(USB_OTG_BASE + 0x82C) +#define USB_DIEPEMPMSK MMIO32(USB_OTG_BASE + 0x834) + +#define USB_DIEPx_CTL(x) \ + MMIO32(USB_OTG_BASE + 0x900 + ((x) * 0x20)) +#define USB_DIEPx_INT(x) \ + MMIO32(USB_OTG_BASE + 0x908 + ((x) * 0x20)) +#define USB_DIEPx_TSIZ(x) \ + MMIO32(USB_OTG_BASE + 0x910 + ((x) * 0x20)) +#define USB_DIEP0CTL USB_DIEPx_CTL(0) +#define USB_DIEP0TSIZ USB_DIEPx_TSIZ(0) +#define USB_DIEP0INT USB_DIEPx_INT(0) + +#define USB_DOEPx_CTL(x) \ + MMIO32(USB_OTG_BASE + 0xB00 + ((x) * 0x20)) +#define USB_DOEPx_INT(x) \ + MMIO32(USB_OTG_BASE + 0xB08 + ((x) * 0x20)) +#define USB_DOEPx_TSIZ(x) \ + MMIO32(USB_OTG_BASE + 0xB10 + ((x) * 0x20)) +#define USB_DOEP0CTL USB_DOEPx_CTL(0) +#define USB_DOEP0TSIZ USB_DOEPx_TSIZ(0) +#define USB_DOEP0INT USB_DOEPx_INT(0) + +/* Power and clock gating control and status register */ +#define USB_PCGCCTL MMIO32(USB_OTG_BASE + 0xE00) + +/* Data FIFO */ +#define USB_FIFOxD(x) \ + (&MMIO32(USB_OTG_BASE + (((x) + 1) << 12))) + +/* Global CSRs */ +/* USB control registers (OTG_HS_GOTGCTL) */ +#define USB_GOTGCTL_BSVLD (1 << 19) +#define USB_GOTGCTL_ASVLD (1 << 18) +#define USB_GOTGCTL_DBCT (1 << 17) +#define USB_GOTGCTL_CIDSTS (1 << 16) +#define USB_GOTGCTL_DHNPEN (1 << 11) +#define USB_GOTGCTL_HSHNPEN (1 << 10) +#define USB_GOTGCTL_HNPRQ (1 << 9) +#define USB_GOTGCTL_HNGSCS (1 << 8) +#define USB_GOTGCTL_SRQ (1 << 1) +#define USB_GOTGCTL_SRQSCS (1 << 0) + +/* AHB configuration register (USB_GAHBCFG) */ +#define USB_GAHBCFG_GLBLINTRMSK 0x0001 +#define USB_GAHBCFG_TXFELVL 0x0080 +#define USB_GAHBCFG_PTXFELVL 0x0100 + +/* USB configuration register (USB_GUSBCFG) */ +#define USB_GUSBCFG_TOCAL 0x00000003 +#define USB_GUSBCFG_SRPCAP 0x00000100 +#define USB_GUSBCFG_HNPCAP 0x00000200 +#define USB_GUSBCFG_TRDT_MASK (0xf << 10) +#define USB_GUSBCFG_TRDT_16BIT (0x5 << 10) +#define USB_GUSBCFG_TRDT_8BIT (0x9 << 10) +#define USB_GUSBCFG_NPTXRWEN 0x00004000 +#define USB_GUSBCFG_FHMOD 0x20000000 +#define USB_GUSBCFG_FDMOD 0x40000000 +#define USB_GUSBCFG_CTXPKT 0x80000000 +#define USB_GUSBCFG_PHYSEL (1 << 7) + +/* reset register (USB_GRSTCTL) */ +#define USB_GRSTCTL_AHBIDL (1 << 31) +/* Bits 30:11 - Reserved */ +#define USB_GRSTCTL_TXFNUM_MASK (0x1f << 6) +#define USB_GRSTCTL_TXFFLSH (1 << 5) +#define USB_GRSTCTL_RXFFLSH (1 << 4) +/* Bit 3 - Reserved */ +#define USB_GRSTCTL_FCRST (1 << 2) +#define USB_GRSTCTL_HSRST (1 << 1) +#define USB_GRSTCTL_CSRST (1 << 0) + +/* interrupt status register (USB_GINTSTS) */ +#define USB_GINTSTS_WKUPINT (1 << 31) +#define USB_GINTSTS_SRQINT (1 << 30) +#define USB_GINTSTS_DISCINT (1 << 29) +#define USB_GINTSTS_CIDSCHG (1 << 28) +/* Bit 27 - Reserved */ +#define USB_GINTSTS_PTXFE (1 << 26) +#define USB_GINTSTS_HCINT (1 << 25) +#define USB_GINTSTS_HPRTINT (1 << 24) +/* Bits 23:22 - Reserved */ +#define USB_GINTSTS_IPXFR (1 << 21) +#define USB_GINTSTS_INCOMPISOOUT (1 << 21) +#define USB_GINTSTS_IISOIXFR (1 << 20) +#define USB_GINTSTS_OEPINT (1 << 19) +#define USB_GINTSTS_IEPINT (1 << 18) +/* Bits 17:16 - Reserved */ +#define USB_GINTSTS_EOPF (1 << 15) +#define USB_GINTSTS_ISOODRP (1 << 14) +#define USB_GINTSTS_ENUMDNE (1 << 13) +#define USB_GINTSTS_USBRST (1 << 12) +#define USB_GINTSTS_USBSUSP (1 << 11) +#define USB_GINTSTS_ESUSP (1 << 10) +/* Bits 9:8 - Reserved */ +#define USB_GINTSTS_GONAKEFF (1 << 7) +#define USB_GINTSTS_GINAKEFF (1 << 6) +#define USB_GINTSTS_NPTXFE (1 << 5) +#define USB_GINTSTS_RXFLVL (1 << 4) +#define USB_GINTSTS_SOF (1 << 3) +#define USB_GINTSTS_OTGINT (1 << 2) +#define USB_GINTSTS_MMIS (1 << 1) +#define USB_GINTSTS_CMOD (1 << 0) + +/* interrupt mask register (USB_GINTMSK) */ +#define USB_GINTMSK_MMISM 0x00000002 +#define USB_GINTMSK_OTGINT 0x00000004 +#define USB_GINTMSK_SOFM 0x00000008 +#define USB_GINTMSK_RXFLVLM 0x00000010 +#define USB_GINTMSK_NPTXFEM 0x00000020 +#define USB_GINTMSK_GINAKEFFM 0x00000040 +#define USB_GINTMSK_GONAKEFFM 0x00000080 +#define USB_GINTMSK_ESUSPM 0x00000400 +#define USB_GINTMSK_USBSUSPM 0x00000800 +#define USB_GINTMSK_USBRST 0x00001000 +#define USB_GINTMSK_ENUMDNEM 0x00002000 +#define USB_GINTMSK_ISOODRPM 0x00004000 +#define USB_GINTMSK_EOPFM 0x00008000 +#define USB_GINTMSK_EPMISM 0x00020000 +#define USB_GINTMSK_IEPINT 0x00040000 +#define USB_GINTMSK_OEPINT 0x00080000 +#define USB_GINTMSK_IISOIXFRM 0x00100000 +#define USB_GINTMSK_IISOOXFRM 0x00200000 +#define USB_GINTMSK_IPXFRM 0x00200000 +#define USB_GINTMSK_PRTIM 0x01000000 +#define USB_GINTMSK_HCIM 0x02000000 +#define USB_GINTMSK_PTXFEM 0x04000000 +#define USB_GINTMSK_CIDSCHGM 0x10000000 +#define USB_GINTMSK_DISCINT 0x20000000 +#define USB_GINTMSK_SRQIM 0x40000000 +#define USB_GINTMSK_WUIM 0x80000000 + +/* Receive Status Pop Register (USB_GRXSTSP) */ +/* Bits 31:25 - Reserved */ +#define USB_GRXSTSP_FRMNUM_MASK (0xf << 21) +#define USB_GRXSTSP_PKTSTS_MASK (0xf << 17) +#define USB_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17) +#define USB_GRXSTSP_PKTSTS_OUT (0x2 << 17) +#define USB_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17) +#define USB_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17) +#define USB_GRXSTSP_PKTSTS_SETUP (0x6 << 17) +#define USB_GRXSTSP_DPID_MASK (0x3 << 15) +#define USB_GRXSTSP_DPID_DATA0 (0x0 << 15) +#define USB_GRXSTSP_DPID_DATA1 (0x2 << 15) +#define USB_GRXSTSP_DPID_DATA2 (0x1 << 15) +#define USB_GRXSTSP_DPID_MDATA (0x3 << 15) +#define USB_GRXSTSP_BCNT_MASK (0x7ff << 4) +#define USB_GRXSTSP_EPNUM_MASK (0xf << 0) + +/* general core configuration register (USB_GCCFG) */ +/* Bits 31:22 - Reserved */ +#define USB_GCCFG_NOVBUSSENS (1 << 21) +#define USB_GCCFG_SOFOUTEN (1 << 20) +#define USB_GCCFG_VBUSBSEN (1 << 19) +#define USB_GCCFG_VBUSASEN (1 << 18) +/* Bit 17 - Reserved */ +#define USB_GCCFG_PWRDWN (1 << 16) +/* Bits 15:0 - Reserved */ + + +/* Device-mode CSRs */ +/* device control register (USB_DCTL) */ +/* Bits 31:12 - Reserved */ +#define USB_DCTL_POPRGDNE (1 << 11) +#define USB_DCTL_CGONAK (1 << 10) +#define USB_DCTL_SGONAK (1 << 9) +#define USB_DCTL_SGINAK (1 << 8) +#define USB_DCTL_TCTL_MASK (7 << 4) +#define USB_DCTL_GONSTS (1 << 3) +#define USB_DCTL_GINSTS (1 << 2) +#define USB_DCTL_SDIS (1 << 1) +#define USB_DCTL_RWUSIG (1 << 0) + +/* device configuration register (USB_DCFG) */ +#define USB_DCFG_DSPD 0x0003 +#define USB_DCFG_NZLSOHSK 0x0004 +#define USB_DCFG_DAD 0x07F0 +#define USB_DCFG_PFIVL 0x1800 + +/* Device IN Endpoint Common Interrupt Mask Register (USB_DIEPMSK) */ +/* Bits 31:10 - Reserved */ +#define USB_DIEPMSK_BIM (1 << 9) +#define USB_DIEPMSK_TXFURM (1 << 8) +/* Bit 7 - Reserved */ +#define USB_DIEPMSK_INEPNEM (1 << 6) +#define USB_DIEPMSK_INEPNMM (1 << 5) +#define USB_DIEPMSK_ITTXFEMSK (1 << 4) +#define USB_DIEPMSK_TOM (1 << 3) +/* Bit 2 - Reserved */ +#define USB_DIEPMSK_EPDM (1 << 1) +#define USB_DIEPMSK_XFRCM (1 << 0) + +/* Device OUT Endpoint Common Interrupt Mask Register (USB_DOEPMSK) */ +/* Bits 31:10 - Reserved */ +#define USB_DOEPMSK_BOIM (1 << 9) +#define USB_DOEPMSK_OPEM (1 << 8) +/* Bit 7 - Reserved */ +#define USB_DOEPMSK_B2BSTUP (1 << 6) +/* Bit 5 - Reserved */ +#define USB_DOEPMSK_OTEPDM (1 << 4) +#define USB_DOEPMSK_STUPM (1 << 3) +/* Bit 2 - Reserved */ +#define USB_DOEPMSK_EPDM (1 << 1) +#define USB_DOEPMSK_XFRCM (1 << 0) + +/* Device Control IN Endpoint 0 Control Register (USB_DIEP0CTL) */ +#define USB_DIEP0CTL_EPENA (1 << 31) +#define USB_DIEP0CTL_EPDIS (1 << 30) +/* Bits 29:28 - Reserved */ +#define USB_DIEP0CTL_SD0PID (1 << 28) +#define USB_DIEP0CTL_SNAK (1 << 27) +#define USB_DIEP0CTL_CNAK (1 << 26) +#define USB_DIEP0CTL_TXFNUM_MASK (0xf << 22) +#define USB_DIEP0CTL_STALL (1 << 21) +/* Bit 20 - Reserved */ +#define USB_DIEP0CTL_EPTYP_MASK (0x3 << 18) +#define USB_DIEP0CTL_NAKSTS (1 << 17) +/* Bit 16 - Reserved */ +#define USB_DIEP0CTL_USBAEP (1 << 15) +/* Bits 14:2 - Reserved */ +#define USB_DIEP0CTL_MPSIZ_MASK (0x3 << 0) +#define USB_DIEP0CTL_MPSIZ_64 (0x0 << 0) +#define USB_DIEP0CTL_MPSIZ_32 (0x1 << 0) +#define USB_DIEP0CTL_MPSIZ_16 (0x2 << 0) +#define USB_DIEP0CTL_MPSIZ_8 (0x3 << 0) + +/* Device Control OUT Endpoint 0 Control Register (USB_DOEP0CTL) */ +#define USB_DOEP0CTL_EPENA (1 << 31) +#define USB_DOEP0CTL_EPDIS (1 << 30) +/* Bits 29:28 - Reserved */ +#define USB_DOEP0CTL_SD0PID (1 << 28) +#define USB_DOEP0CTL_SNAK (1 << 27) +#define USB_DOEP0CTL_CNAK (1 << 26) +/* Bits 25:22 - Reserved */ +#define USB_DOEP0CTL_STALL (1 << 21) +#define USB_DOEP0CTL_SNPM (1 << 20) +#define USB_DOEP0CTL_EPTYP_MASK (0x3 << 18) +#define USB_DOEP0CTL_NAKSTS (1 << 17) +/* Bit 16 - Reserved */ +#define USB_DOEP0CTL_USBAEP (1 << 15) +/* Bits 14:2 - Reserved */ +#define USB_DOEP0CTL_MPSIZ_MASK (0x3 << 0) +#define USB_DOEP0CTL_MPSIZ_64 (0x0 << 0) +#define USB_DOEP0CTL_MPSIZ_32 (0x1 << 0) +#define USB_DOEP0CTL_MPSIZ_16 (0x2 << 0) +#define USB_DOEP0CTL_MPSIZ_8 (0x3 << 0) + +/* Device IN Endpoint Interrupt Register (USB_DIEPINTx) */ +/* Bits 31:8 - Reserved */ +#define USB_DIEP_INT_TXFE (1 << 7) +#define USB_DIEP_INT_INEPNE (1 << 6) +/* Bit 5 - Reserved */ +#define USB_DIEP_INT_ITTXFE (1 << 4) +#define USB_DIEP_INT_TOC (1 << 3) +/* Bit 2 - Reserved */ +#define USB_DIEP_INT_EPDISD (1 << 1) +#define USB_DIEP_INT_XFRC (1 << 0) + +/* Device IN Endpoint Interrupt Register (USB_DOEPINTx) */ +/* Bits 31:7 - Reserved */ +#define USB_DOEP_INT_B2BSTUP (1 << 6) +/* Bit 5 - Reserved */ +#define USB_DOEP_INT_OTEPDIS (1 << 4) +#define USB_DOEP_INT_SETUP (1 << 3) +/* Bit 2 - Reserved */ +#define USB_DOEP_INT_EPDISD (1 << 1) +#define USB_DOEP_INT_XFRC (1 << 0) + +/* Device OUT Endpoint 0 Transfer Size Register (USB_DOEP0TSIZ) */ +/* Bit 31 - Reserved */ +#define USB_DIEP0TSIZ_STUPCNT_1 (0x1 << 29) +#define USB_DIEP0TSIZ_STUPCNT_2 (0x2 << 29) +#define USB_DIEP0TSIZ_STUPCNT_3 (0x3 << 29) +#define USB_DIEP0TSIZ_STUPCNT_MASK (0x3 << 29) +/* Bits 28:20 - Reserved */ +#define USB_DIEP0TSIZ_PKTCNT (1 << 19) +/* Bits 18:7 - Reserved */ +#define USB_DIEP0TSIZ_XFRSIZ_MASK (0x7f << 0) + +#endif + diff --git a/include/libopencm3/efm32/common/wdog_common.h b/include/libopencm3/efm32/common/wdog_common.h new file mode 100644 index 00000000..d4dad2da --- /dev/null +++ b/include/libopencm3/efm32/common/wdog_common.h @@ -0,0 +1,76 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2015 Kuldeep Singh Dhaka + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +#ifndef LIBOPENCM3_EFM32_WDOG_H +#define LIBOPENCM3_EFM32_WDOG_H + +#include +#include + +#define WDOG_CTRL MMIO32(WDOG_BASE + 0x000) +#define WDOG_CMD MMIO32(WDOG_BASE + 0x004) +#define WDOG_SYNCBUSY MMIO32(WDOG_BASE + 0x008) + +/* WDOG_CTRL */ +#define WDOG_CTRL_CLKSEL_SHIFT (12) +#define WDOG_CTRL_CLKSEL_MASK (0x3 << WDOG_CTRL_CLKSEL_SHIFT) +#define WDOG_CTRL_CLKSEL(v) \ + (((v) << WDOG_CTRL_CLKSEL_SHIFT) & WDOG_CTRL_CLKSEL_MASK) +#define WDOG_CTRL_CLKSEL_ULFRCO 0 +#define WDOG_CTRL_CLKSEL_LFRCO 1 +#define WDOG_CTRL_CLKSEL_LFXO 2 + +#define WDOG_CTRL_PERSEL_SHIFT (8) +#define WDOG_CTRL_PERSEL_MASK (0xF << WDOG_CTRL_PERSEL_SHIFT) +#define WDOG_CTRL_PERSEL(v) \ + (((v) << WDOG_CTRL_PERSEL_SHIFT) & WDOG_CTRL_PERSEL_MASK) +#define WDOG_CTRL_PERSEL_9CYCLES 0 +#define WDOG_CTRL_PERSEL_17CYCLES 1 +#define WDOG_CTRL_PERSEL_33CYCLES 2 +#define WDOG_CTRL_PERSEL_65CYCLES 3 +#define WDOG_CTRL_PERSEL_129CYCLES 4 +#define WDOG_CTRL_PERSEL_257CYCLES 5 +#define WDOG_CTRL_PERSEL_513CYCLES 6 +#define WDOG_CTRL_PERSEL_1KCYCLES 7 +#define WDOG_CTRL_PERSEL_2KCYCLES 8 +#define WDOG_CTRL_PERSEL_4KCYCLES 9 +#define WDOG_CTRL_PERSEL_8KCYCLES 10 +#define WDOG_CTRL_PERSEL_16KCYCLES 11 +#define WDOG_CTRL_PERSEL_32KCYCLES 12 +#define WDOG_CTRL_PERSEL_64KCYCLES 13 +#define WDOG_CTRL_PERSEL_128KCYCLES 14 +#define WDOG_CTRL_PERSEL_256KCYCLES 15 + +#define WDOG_CTRL_SWOSCBLOCK (1 << 6) +#define WDOG_CTRL_EM4BLOCK (1 << 5) +#define WDOG_CTRL_LOCK (1 << 4) +#define WDOG_CTRL_EM3RUN (1 << 3) +#define WDOG_CTRL_EM2RUN (1 << 2) +#define WDOG_CTRL_DEBUGRUN (1 << 1) +#define WDOG_CTRL_EN (1 << 0) + +/* WDOG_CMD */ +#define WDOG_CMD_CLEAR (1 << 0) + +/* WDOG_SYNCBUSY */ +#define WDOG_SYNCBUSY_CMD (1 << 1) +#define WDOG_SYNCBUSY_CTRL (1 << 0) + +#endif + diff --git a/include/libopencm3/efm32/hg/timer.h b/include/libopencm3/efm32/hg/timer.h index c5a3f446..647abe85 100644 --- a/include/libopencm3/efm32/hg/timer.h +++ b/include/libopencm3/efm32/hg/timer.h @@ -18,7 +18,7 @@ #ifndef LIBOPENCM3_TIMER_H #define LIBOPENCM3_TIMER_H -#include +#include /* efm32hg specific registers */ @@ -28,29 +28,4 @@ /* TIMER_CCx_CTRL */ #define TIMER_CC_CTRL_PRSCONF (1 << 28) -#define TIMER_CC_CTRL_PRSSEL_SHIFT (16) -#define TIMER_CC_CTRL_PRSSEL_MASK (0x7 << TIMER_CC_CTRL_PRSSEL_SHIFT) -#define TIMER_CC_CTRL_PRSSEL(v) \ - (((v) << TIMER_CC_CTRL_PRSSEL_SHIFT) & TIMER_CC_CTRL_PRSSEL_MASK) -#define TIMER_CC_CTRL_PRSSEL_PRSCHx(x) TIMER_CC_CTRL_PRSSEL(x) -#define TIMER_CC_CTRL_PRSSEL_PRSCH0 TIMER_CC_CTRL_PRSSEL_PRSCHx(0) -#define TIMER_CC_CTRL_PRSSEL_PRSCH1 TIMER_CC_CTRL_PRSSEL_PRSCHx(1) -#define TIMER_CC_CTRL_PRSSEL_PRSCH2 TIMER_CC_CTRL_PRSSEL_PRSCHx(2) -#define TIMER_CC_CTRL_PRSSEL_PRSCH3 TIMER_CC_CTRL_PRSSEL_PRSCHx(3) -#define TIMER_CC_CTRL_PRSSEL_PRSCH4 TIMER_CC_CTRL_PRSSEL_PRSCHx(4) -#define TIMER_CC_CTRL_PRSSEL_PRSCH5 TIMER_CC_CTRL_PRSSEL_PRSCHx(5) - -/* TIMER_DTCTRL */ -#define TIMER_DTCTRL_DTPRSSEL_SHIFT (4) -#define TIMER_DTCTRL_DTPRSSEL_MASK (0x7 << TIMER_DTCTRL_DTPRSSEL_SHIFT) -#define TIMER_DTCTRL_DTPRSSEL(v) \ - (((v) << TIMER_DTCTRL_DTPRSSEL_SHIFT) & TIMER_DTCTRL_DTPRSSEL_MASK) -#define TIMER_DTCTRL_DTPRSSEL_PRSCHx(x) TIMER_DTCTRL_DTPRSSEL(x) -#define TIMER_DTCTRL_DTPRSSEL_PRSCH0 TIMER_DTCTRL_DTPRSSEL_PRSCHx(0) -#define TIMER_DTCTRL_DTPRSSEL_PRSCH1 TIMER_DTCTRL_DTPRSSEL_PRSCHx(1) -#define TIMER_DTCTRL_DTPRSSEL_PRSCH2 TIMER_DTCTRL_DTPRSSEL_PRSCHx(2) -#define TIMER_DTCTRL_DTPRSSEL_PRSCH3 TIMER_DTCTRL_DTPRSSEL_PRSCHx(3) -#define TIMER_DTCTRL_DTPRSSEL_PRSCH4 TIMER_DTCTRL_DTPRSSEL_PRSCHx(4) -#define TIMER_DTCTRL_DTPRSSEL_PRSCH5 TIMER_DTCTRL_DTPRSSEL_PRSCHx(5) - #endif diff --git a/include/libopencm3/efm32/lg/acmp.h b/include/libopencm3/efm32/lg/acmp.h index 0e41ef9a..0df98c94 100644 --- a/include/libopencm3/efm32/lg/acmp.h +++ b/include/libopencm3/efm32/lg/acmp.h @@ -1,7 +1,7 @@ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2015 Kuldeep Singh Dhaka + * Copyright (C) 2016 Bob Miller * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -17,169 +17,9 @@ * along with this library. If not, see . */ -#ifndef LIBOPENCM3_EFM32_ACMP_H -#define LIBOPENCM3_EFM32_ACMP_H +#ifndef LIBOPENCM3_EFM32_LG_ACMP_H +#define LIBOPENCM3_EFM32_LG_ACMP_H -#include -#include - -#define ACMP_CTRL(base) ((base) + 0x000) -#define ACMP_INPUTSEL(base) ((base) + 0x004) -#define ACMP_STATUS(base) ((base) + 0x008) -#define ACMP_IEN(base) ((base) + 0x00C) -#define ACMP_IF(base) ((base) + 0x010) -#define ACMP_IFS(base) ((base) + 0x014) -#define ACMP_IFC(base) ((base) + 0x018) -#define ACMP_ROUTE(base) ((base) + 0x01C) - -/* ACMP_CTRL */ -#define ACMP_CTRL_FULLBIAS (1 << 31) -#define ACMP_CTRL_HALFBIAS (1 << 30) - -#define ACMP_CTRL_BIASPROG_SHIFT (24) -#define ACMP_CTRL_BIASPROG_MASK (0xF << ACMP_CTRL_BIASPROG_SHIFT) -#define ACMP_CTRL_BIASPROG(v) \ - (((v) << ACMP_CTRL_BIASPROG_SHIFT) & ACMP_CTRL_BIASPROG_MASK) - -#define ACMP_CTRL_IFALL (1 << 17) -#define ACMP_CTRL_IRISE (1 << 16) - -#define ACMP_CTRL_WARMTIME_SHIFT (8) -#define ACMP_CTRL_WARMTIME_MASK (0x7 << ACMP_CTRL_WARMTIME_SHIFT) -#define ACMP_CTRL_WARMTIME(v) \ - (((v) << ACMP_CTRL_WARMTIME_SHIFT) & ACMP_CTRL_WARMTIME_MASK) -#define ACMP_CTRL_WARMTIME_4CYCLES ACMP_CTRL_WARMTIME(0) -#define ACMP_CTRL_WARMTIME_8CYCLES ACMP_CTRL_WARMTIME(1) -#define ACMP_CTRL_WARMTIME_16CYCLES ACMP_CTRL_WARMTIME(2) -#define ACMP_CTRL_WARMTIME_32CYCLES ACMP_CTRL_WARMTIME(3) -#define ACMP_CTRL_WARMTIME_64CYCLES ACMP_CTRL_WARMTIME(4) -#define ACMP_CTRL_WARMTIME_128CYCLES ACMP_CTRL_WARMTIME(5) -#define ACMP_CTRL_WARMTIME_256CYCLES ACMP_CTRL_WARMTIME(6) -#define ACMP_CTRL_WARMTIME_512CYCLES ACMP_CTRL_WARMTIME(7) - -#define ACMP_CTRL_HYSTSEL_SHIFT (8) -#define ACMP_CTRL_HYSTSEL_MASK (0x7 << ACMP_CTRL_HYSTSEL_SHIFT) -#define ACMP_CTRL_HYSTSEL(v) \ - (((v) << ACMP_CTRL_HYSTSEL_SHIFT) & ACMP_CTRL_HYSTSEL_MASK) -#define ACMP_CTRL_HYSTSEL_HYSTx(x) ACMP_CTRL_HYSTSEL(x) -#define ACMP_CTRL_HYSTSEL_HYST0 ACMP_CTRL_HYSTSEL_HYSTx(0) -#define ACMP_CTRL_HYSTSEL_HYST1 ACMP_CTRL_HYSTSEL_HYSTx(1) -#define ACMP_CTRL_HYSTSEL_HYST2 ACMP_CTRL_HYSTSEL_HYSTx(2) -#define ACMP_CTRL_HYSTSEL_HYST3 ACMP_CTRL_HYSTSEL_HYSTx(3) -#define ACMP_CTRL_HYSTSEL_HYST4 ACMP_CTRL_HYSTSEL_HYSTx(4) -#define ACMP_CTRL_HYSTSEL_HYST5 ACMP_CTRL_HYSTSEL_HYSTx(5) -#define ACMP_CTRL_HYSTSEL_HYST6 ACMP_CTRL_HYSTSEL_HYSTx(6) -#define ACMP_CTRL_HYSTSEL_HYST7 ACMP_CTRL_HYSTSEL_HYSTx(7) - -#define ACMP_CTRL_GPIOINV (1 << 3) -#define ACMP_CTRL_INACTVAL (1 << 2) -#define ACMP_CTRL_MUXEN (1 << 1) -#define ACMP_CTRL_EN (1 << 0) - -/* ACMP_INPUTSEL */ -#define ACMP_INPUTSEL_CSRESSEL_SHIFT (28) -#define ACMP_INPUTSEL_CSRESSEL_MASK (0x3 << ACMP_INPUTSEL_CSRESSEL_SHIFT) -#define ACMP_INPUTSEL_CSRESSEL(v) \ - (((v) << ACMP_INPUTSEL_CSRESSEL_SHIFT) & ACMP_INPUTSEL_CSRESSEL_MASK) -#define ACMP_INPUTSEL_CSRESSEL_RESx(x) ACMP_INPUTSEL_CSRESSEL_RES(x) -#define ACMP_INPUTSEL_CSRESSEL_RES0 ACMP_INPUTSEL_CSRESSEL_RESx(0) -#define ACMP_INPUTSEL_CSRESSEL_RES1 ACMP_INPUTSEL_CSRESSEL_RESx(1) -#define ACMP_INPUTSEL_CSRESSEL_RES2 ACMP_INPUTSEL_CSRESSEL_RESx(2) -#define ACMP_INPUTSEL_CSRESSEL_RES3 ACMP_INPUTSEL_CSRESSEL_RESx(3) - -#define ACMP_INPUTSEL_CSRESEN (1 << 24) -#define ACMP_INPUTSEL_LPREF (1 << 16) - -#define ACMP_INPUTSEL_VDDLEVEL_SHIFT (8) -#define ACMP_INPUTSEL_VDDLEVEL_MASK (0x3F << ACMP_INPUTSEL_VDDLEVEL_SHIFT) -#define ACMP_INPUTSEL_VDDLEVEL(v) \ - (((v) << ACMP_INPUTSEL_VDDLEVEL_SHIFT) & ACMP_INPUTSEL_VDDLEVEL_MASK) - -#define ACMP_INPUTSEL_NEGSEL_SHIFT (8) -#define ACMP_INPUTSEL_NEGSEL_MASK (0x3F << ACMP_INPUTSEL_NEGSEL_SHIFT) -#define ACMP_INPUTSEL_NEGSEL(v) \ - (((v) << ACMP_INPUTSEL_NEGSEL_SHIFT) & ACMP_INPUTSEL_NEGSEL_MASK) -#define ACMP_INPUTSEL_NEGSEL_CHx(x) ACMP_INPUTSEL_NEGSEL(x) -#define ACMP_INPUTSEL_NEGSEL_CH0 ACMP_INPUTSEL_NEGSEL_CHx(0) -#define ACMP_INPUTSEL_NEGSEL_CH1 ACMP_INPUTSEL_NEGSEL_CHx(1) -#define ACMP_INPUTSEL_NEGSEL_CH2 ACMP_INPUTSEL_NEGSEL_CHx(2) -#define ACMP_INPUTSEL_NEGSEL_CH3 ACMP_INPUTSEL_NEGSEL_CHx(3) -#define ACMP_INPUTSEL_NEGSEL_CH4 ACMP_INPUTSEL_NEGSEL_CHx(4) -#define ACMP_INPUTSEL_NEGSEL_CH5 ACMP_INPUTSEL_NEGSEL_CHx(5) -#define ACMP_INPUTSEL_NEGSEL_CH6 ACMP_INPUTSEL_NEGSEL_CHx(6) -#define ACMP_INPUTSEL_NEGSEL_CH7 ACMP_INPUTSEL_NEGSEL_CHx(7) -#define ACMP_INPUTSEL_NEGSEL_1V25 ACMP_INPUTSEL_NEGSEL(8) -#define ACMP_INPUTSEL_NEGSEL_2V5 ACMP_INPUTSEL_NEGSEL(9) -#define ACMP_INPUTSEL_NEGSEL_VDD ACMP_INPUTSEL_NEGSEL(10) -#define ACMP_INPUTSEL_NEGSEL_CAPSENSE ACMP_INPUTSEL_NEGSEL(11) -#define ACMP_INPUTSEL_NEGSEL_DAC0CH0 ACMP_INPUTSEL_NEGSEL(12) -#define ACMP_INPUTSEL_NEGSEL_DAC0CH1 ACMP_INPUTSEL_NEGSEL(13) - -#define ACMP_INPUTSEL_POSSEL_SHIFT (0) -#define ACMP_INPUTSEL_POSSEL_MASK (0x7 << ACMP_INPUTSEL_POSSEL_SHIFT) -#define ACMP_INPUTSEL_POSSEL(v) \ - (((v) << ACMP_INPUTSEL_LPOSSELL_SHIFT) & ACMP_INPUTSEL_LPOSSELL_MASK) -#define ACMP_INPUTSEL_POSSEL_CHx(x) ACMP_INPUTSEL_POSSEL(x) -#define ACMP_INPUTSEL_POSSEL_CH0 ACMP_INPUTSEL_POSSEL_CHx(0) -#define ACMP_INPUTSEL_POSSEL_CH1 ACMP_INPUTSEL_POSSEL_CHx(1) -#define ACMP_INPUTSEL_POSSEL_CH2 ACMP_INPUTSEL_POSSEL_CHx(2) -#define ACMP_INPUTSEL_POSSEL_CH3 ACMP_INPUTSEL_POSSEL_CHx(3) -#define ACMP_INPUTSEL_POSSEL_CH4 ACMP_INPUTSEL_POSSEL_CHx(4) -#define ACMP_INPUTSEL_POSSEL_CH5 ACMP_INPUTSEL_POSSEL_CHx(5) -#define ACMP_INPUTSEL_POSSEL_CH6 ACMP_INPUTSEL_POSSEL_CHx(6) -#define ACMP_INPUTSEL_POSSEL_CH7 ACMP_INPUTSEL_POSSEL_CHx(7) - -/* ACMP_STATUS */ -#define ACMP_STATUS_ACMPOUT (1 << 1) -#define ACMP_STATUS_ACMPACT (1 << 0) - -/* ACMP_IEN */ -#define ACMP_IEN_WARMUP (1 << 1) -#define ACMP_IEN_EDGE (1 << 0) - -/* ACMP_IF */ -#define ACMP_IF_WARMUP (1 << 1) -#define ACMP_IF_EDGE (1 << 0) - -/* ACMP_IFS */ -#define ACMP_IFS_WARMUP (1 << 1) -#define ACMP_IFS_EDGE (1 << 0) - -/* ACMP_IFC */ -#define ACMP_IFC_WARMUP (1 << 1) -#define ACMP_IFC_EDGE (1 << 0) - -/* ACMP_ROUTE */ -#define ACMP_ROUTE_LOCATION_SHIFT (8) -#define ACMP_ROUTE_LOCATION_MASK (0x7 << ACMP_ROUTE_LOCATION_SHIFT) -#define ACMP_ROUTE_LOCATION(v) \ - (((v) << ACMP_ROUTE_LOCATION_SHIFT) & ACMP_ROUTE_LOCATION_MASK) -#define ACMP_ROUTE_LOCATION_LOCx(x) ACMP_ROUTE_LOCATION(x) -#define ACMP_ROUTE_LOCATION_LOC0 ACMP_ROUTE_LOCATIONx(0) -#define ACMP_ROUTE_LOCATION_LOC1 ACMP_ROUTE_LOCATIONx(1) -#define ACMP_ROUTE_LOCATION_LOC2 ACMP_ROUTE_LOCATIONx(2) - -#define ACMP_ROUTE_ACMPPEN (1 << 0) - -#define ACMP0 ACMP0_BASE -#define ACMP0_CTRL ACMP_CTRL(ACMP0) -#define ACMP0_INPUTSEL ACMP_INPUTSEL(ACMP0) -#define ACMP0_STATUS ACMP_STATUS(ACMP0) -#define ACMP0_IEN ACMP_IEN(ACMP0) -#define ACMP0_IF ACMP_IF(ACMP0) -#define ACMP0_IFS ACMP_IFS(ACMP0) -#define ACMP0_IFC ACMP_IFC(ACMP0) -#define ACMP0_ROUTE ACMP_ROUTE(ACMP0) - -#define ACMP1 ACMP1_BASE -#define ACMP1_CTRL ACMP_CTRL(ACMP1) -#define ACMP1_INPUTSEL ACMP_INPUTSEL(ACMP1) -#define ACMP1_STATUS ACMP_STATUS(ACMP1) -#define ACMP1_IEN ACMP_IEN(ACMP1) -#define ACMP1_IF ACMP_IF(ACMP1) -#define ACMP1_IFS ACMP_IFS(ACMP1) -#define ACMP1_IFC ACMP_IFC(ACMP1) -#define ACMP1_ROUTE ACMP_ROUTE(ACMP1) +#include #endif - diff --git a/include/libopencm3/efm32/lg/adc.h b/include/libopencm3/efm32/lg/adc.h index a2988da1..5432ce64 100644 --- a/include/libopencm3/efm32/lg/adc.h +++ b/include/libopencm3/efm32/lg/adc.h @@ -1,7 +1,7 @@ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2015 Kuldeep Singh Dhaka + * Copyright (C) 2016 Bob Miller * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -17,441 +17,9 @@ * along with this library. If not, see . */ -#ifndef LIBOPENCM3_EFM32_ADC_H -#define LIBOPENCM3_EFM32_ADC_H +#ifndef LIBOPENCM3_EFM32_LG_ADC_H +#define LIBOPENCM3_EFM32_LG_ADC_H -#include -#include - -#define ADC_CTRL(base) MMIO32((base) + 0x000) -#define ADC_CMD(base) MMIO32((base) + 0x004) -#define ADC_STATUS(base) MMIO32((base) + 0x008) -#define ADC_SINGLECTRL(base) MMIO32((base) + 0x00C) -#define ADC_SCANCTRL(base) MMIO32((base) + 0x010) -#define ADC_IEN(base) MMIO32((base) + 0x014) -#define ADC_IF(base) MMIO32((base) + 0x018) -#define ADC_IFS(base) MMIO32((base) + 0x01C) -#define ADC_IFC(base) MMIO32((base) + 0x020) -#define ADC_SINGLEDATA(base) MMIO32((base) + 0x024) -#define ADC_SCANDATA(base) MMIO32((base) + 0x028) -#define ADC_SINGLEDATAP(base) MMIO32((base) + 0x02C) -#define ADC_SCANDATAP(base) MMIO32((base) + 0x030) -#define ADC_CAL(base) MMIO32((base) + 0x034) -#define ADC_BIASPROG(base) MMIO32((base) + 0x03C) - -/* ADC_CTRL */ -#define ADC_CTRL_OVERSEL_SHIFT (24) -#define ADC_CTRL_OVERSEL_MASK (0xF << ADC_CTRL_OVERSEL_SHIFT) -#define ADC_CTRL_OVERSEL(v) \ - (((v) << ADC_CTRL_OVERSEL_SHIFT) & ADC_CTRL_OVERSEL_MASK) -#define ADC_CTRL_OVERSEL_X2 ADC_CTRL_OVERSEL(0) -#define ADC_CTRL_OVERSEL_X4 ADC_CTRL_OVERSEL(1) -#define ADC_CTRL_OVERSEL_X8 ADC_CTRL_OVERSEL(2) -#define ADC_CTRL_OVERSEL_X16 ADC_CTRL_OVERSEL(3) -#define ADC_CTRL_OVERSEL_X32 ADC_CTRL_OVERSEL(4) -#define ADC_CTRL_OVERSEL_X64 ADC_CTRL_OVERSEL(5) -#define ADC_CTRL_OVERSEL_X128 ADC_CTRL_OVERSEL(6) -#define ADC_CTRL_OVERSEL_X256 ADC_CTRL_OVERSEL(7) -#define ADC_CTRL_OVERSEL_X512 ADC_CTRL_OVERSEL(8) -#define ADC_CTRL_OVERSEL_X1024 ADC_CTRL_OVERSEL(9) -#define ADC_CTRL_OVERSEL_X2048 ADC_CTRL_OVERSEL(10) -#define ADC_CTRL_OVERSEL_X4096 ADC_CTRL_OVERSEL(11) - -#define ADC_CTRL_TIMEBASE_SHIFT (16) -#define ADC_CTRL_TIMEBASE_MASK (0x3F << ADC_CTRL_TIMEBASE_SHIFT) -#define ADC_CTRL_TIMEBASE(v) \ - (((v) << ADC_CTRL_TIMEBASE_SHIFT) & ADC_CTRL_TIMEBASE_MASK) - -#define ADC_CTRL_PRESC_SHIFT (8) -#define ADC_CTRL_PRESC_MASK (0x3F << ADC_CTRL_PRESC_SHIFT) -#define ADC_CTRL_PRESC(v) \ - (((v) << ADC_CTRL_PRESC_SHIFT) & ADC_CTRL_PRESC_MASK) - -#define ADC_CTRL_LPFMODE_SHIFT (4) -#define ADC_CTRL_LPFMODE_MASK (0x3 << ADC_CTRL_LPFMODE_SHIFT) -#define ADC_CTRL_LPFMODE(v) \ - (((v) << ADC_CTRL_LPFMODE_SHIFT) & ADC_CTRL_LPFMODE_MASK) -#define ADC_CTRL_LPFMODE_BYPASS ADC_CTRL_LPFMODE(0) -#define ADC_CTRL_LPFMODE_DECAP ADC_CTRL_LPFMODE(1) -#define ADC_CTRL_LPFMODE_RCFILT ADC_CTRL_LPFMODE(2) - -#define ADC_CTRL_TAILGATE (1 << 3) - -#define ADC_CTRL_WARMUPMODE_SHIFT (0) -#define ADC_CTRL_WARMUPMODE_MASK (0x3 << ADC_CTRL_WARMUPMODE_SHIFT) -#define ADC_CTRL_WARMUPMODE(v) \ - (((v) << ADC_CTRL_WARMUPMODE_SHIFT) & ADC_CTRL_WARMUPMODE_MASK) -#define ADC_CTRL_WARMUPMODE_NORMAL ADC_CTRL_WARMUPMODE(0) -#define ADC_CTRL_WARMUPMODE_FASTBG ADC_CTRL_WARMUPMODE(1) -#define ADC_CTRL_WARMUPMODE_KEEPSCANREFWARM ADC_CTRL_WARMUPMODE(2) -#define ADC_CTRL_WARMUPMODE_KEEPADCWARM ADC_CTRL_WARMUPMODE(3) - -/* ADC_CMD */ -#define ADC_CMD_SCANSTOP (1 << 3) -#define ADC_CMD_SCANSTART (1 << 2) -#define ADC_CMD_SINGLESTOP (1 << 1) -#define ADC_CMD_SINGLESTART (1 << 0) - -/* ADC_STATUS */ -#define ADC_STATUS_SCANDATASRC_SHIFT (0) -#define ADC_STATUS_SCANDATASRC_MASK (0x7 << ADC_STATUS_SCANDATASRC_SHIFT) -#define ADC_STATUS_SCANDATASRC(v) \ - (((v) << ADC_STATUS_SCANDATASRC_SHIFT) & ADC_STATUS_SCANDATASRC_MASK) - -#define ADC_STATUS_SCANDV (1 << 17) -#define ADC_STATUS_SINGLEDV (1 << 16) -#define ADC_STATUS_WARM (1 << 12) -#define ADC_STATUS_SCANREFWARM (1 << 9) -#define ADC_STATUS_SINGLEREFWARM (1 << 8) -#define ADC_STATUS_SCANACT (1 << 1) -#define ADC_STATUS_SINGLEACT (1 << 0) - -/* ADC_SINGLECTRL */ -#define ADC_SINGLECTRL_PRSSEL_SHIFT (28) -#define ADC_SINGLECTRL_PRSSEL_MASK (0xF << ADC_SINGLECTRL_PRSSEL_SHIFT) -#define ADC_SINGLECTRL_PRSSEL(v) \ - (((v) << ADC_SINGLECTRL_PRSSEL_SHIFT) & ADC_SINGLECTRL_PRSSEL_MASK) -#define ADC_SINGLECTRL_PRSSEL_PRSCHx(x) ADC_SINGLECTRL_PRSSEL(x) -#define ADC_SINGLECTRL_PRSSEL_PRSCH0 ADC_SINGLECTRL_PRSSEL_PRSCHx(0) -#define ADC_SINGLECTRL_PRSSEL_PRSCH1 ADC_SINGLECTRL_PRSSEL_PRSCHx(1) -#define ADC_SINGLECTRL_PRSSEL_PRSCH2 ADC_SINGLECTRL_PRSSEL_PRSCHx(2) -#define ADC_SINGLECTRL_PRSSEL_PRSCH3 ADC_SINGLECTRL_PRSSEL_PRSCHx(3) -#define ADC_SINGLECTRL_PRSSEL_PRSCH4 ADC_SINGLECTRL_PRSSEL_PRSCHx(4) -#define ADC_SINGLECTRL_PRSSEL_PRSCH5 ADC_SINGLECTRL_PRSSEL_PRSCHx(5) -#define ADC_SINGLECTRL_PRSSEL_PRSCH6 ADC_SINGLECTRL_PRSSEL_PRSCHx(6) -#define ADC_SINGLECTRL_PRSSEL_PRSCH7 ADC_SINGLECTRL_PRSSEL_PRSCHx(7) -#define ADC_SINGLECTRL_PRSSEL_PRSCH8 ADC_SINGLECTRL_PRSSEL_PRSCHx(8) -#define ADC_SINGLECTRL_PRSSEL_PRSCH9 ADC_SINGLECTRL_PRSSEL_PRSCHx(9) -#define ADC_SINGLECTRL_PRSSEL_PRSCH10 ADC_SINGLECTRL_PRSSEL_PRSCHx(10) -#define ADC_SINGLECTRL_PRSSEL_PRSCH11 ADC_SINGLECTRL_PRSSEL_PRSCHx(11) - -#define ADC_SINGLECTRL_PRSEN (1 << 24) - -#define ADC_SINGLECTRL_AT_SHIFT (20) -#define ADC_SINGLECTRL_AT_MASK (0xF << ADC_SINGLECTRL_AT_SHIFT) -#define ADC_SINGLECTRL_AT(v) \ - (((v) << ADC_SINGLECTRL_AT_SHIFT) & ADC_SINGLECTRL_AT_MASK) -#define ADC_SINGLECTRL_AT_1CYCLE ADC_SINGLECTRL_AT(0x0) -#define ADC_SINGLECTRL_AT_2CYCLES ADC_SINGLECTRL_AT(0x1) -#define ADC_SINGLECTRL_AT_4CYCLES ADC_SINGLECTRL_AT(0x2) -#define ADC_SINGLECTRL_AT_8CYCLES ADC_SINGLECTRL_AT(0x3) -#define ADC_SINGLECTRL_AT_16CYCLES ADC_SINGLECTRL_AT(0x4) -#define ADC_SINGLECTRL_AT_32CYCLES ADC_SINGLECTRL_AT(0x5) -#define ADC_SINGLECTRL_AT_64CYCLES ADC_SINGLECTRL_AT(0x6) -#define ADC_SINGLECTRL_AT_128CYCLES ADC_SINGLECTRL_AT(0x7) -#define ADC_SINGLECTRL_AT_256CYCLES ADC_SINGLECTRL_AT(0x8) - -#define ADC_SINGLECTRL_REF_SHIFT (16) -#define ADC_SINGLECTRL_REF_MASK (0xF << ADC_SINGLECTRL_REF_SHIFT) -#define ADC_SINGLECTRL_REF(v) \ - (((v) << ADC_SINGLECTRL_REF_SHIFT) & ADC_SINGLECTRL_REF_MASK) -#define ADC_SINGLECTRL_REF_1V25 ADC_SINGLECTRL_REF(0) -#define ADC_SINGLECTRL_REF_2V5 ADC_SINGLECTRL_REF(1) -#define ADC_SINGLECTRL_REF_VDD ADC_SINGLECTRL_REF(2) -#define ADC_SINGLECTRL_REF_5VDIFF ADC_SINGLECTRL_REF(3) -#define ADC_SINGLECTRL_REF_EXTSINGLE ADC_SINGLECTRL_REF(4) -#define ADC_SINGLECTRL_REF_2XEXTDIFF ADC_SINGLECTRL_REF(5) -#define ADC_SINGLECTRL_REF_2XVDD ADC_SINGLECTRL_REF(6) - -#define ADC_SINGLECTRL_INPUTSEL_SHIFT (8) -#define ADC_SINGLECTRL_INPUTSEL_MASK (0xF << ADC_SINGLECTRL_INPUTSEL_SHIFT) -#define ADC_SINGLECTRL_INPUTSEL(v) \ - (((v) << ADC_SINGLECTRL_INPUTSEL_SHIFT) & ADC_SINGLECTRL_INPUTSEL_MASK) -/* DIFF=0 */ -#define ADC_SINGLECTRL_INPUTSEL_CHx(x) ADC_SINGLECTRL_INPUTSEL(x) -#define ADC_SINGLECTRL_INPUTSEL_CH0 ADC_SINGLECTRL_INPUTSEL_CHx(0) -#define ADC_SINGLECTRL_INPUTSEL_CH1 ADC_SINGLECTRL_INPUTSEL_CHx(1) -#define ADC_SINGLECTRL_INPUTSEL_CH2 ADC_SINGLECTRL_INPUTSEL_CHx(2) -#define ADC_SINGLECTRL_INPUTSEL_CH3 ADC_SINGLECTRL_INPUTSEL_CHx(3) -#define ADC_SINGLECTRL_INPUTSEL_CH4 ADC_SINGLECTRL_INPUTSEL_CHx(4) -#define ADC_SINGLECTRL_INPUTSEL_CH5 ADC_SINGLECTRL_INPUTSEL_CHx(5) -#define ADC_SINGLECTRL_INPUTSEL_CH6 ADC_SINGLECTRL_INPUTSEL_CHx(6) -#define ADC_SINGLECTRL_INPUTSEL_CH7 ADC_SINGLECTRL_INPUTSEL_CHx(7) -#define ADC_SINGLECTRL_INPUTSEL_TEMP ADC_SINGLECTRL_INPUTSEL(8) -#define ADC_SINGLECTRL_INPUTSEL_VDDDIV3 ADC_SINGLECTRL_INPUTSEL(9) -#define ADC_SINGLECTRL_INPUTSEL_VDD ADC_SINGLECTRL_INPUTSEL(10) -#define ADC_SINGLECTRL_INPUTSEL_VSS ADC_SINGLECTRL_INPUTSEL(11) -#define ADC_SINGLECTRL_INPUTSEL_VREFDIV2 ADC_SINGLECTRL_INPUTSEL(12) -#define ADC_SINGLECTRL_INPUTSEL_DAC0OUT0 ADC_SINGLECTRL_INPUTSEL(13) -#define ADC_SINGLECTRL_INPUTSEL_DAC0OUT1 ADC_SINGLECTRL_INPUTSEL(14) -/* DIFF=1 */ -#define ADC_SINGLECTRL_INPUTSEL_CH0CH1 ADC_SINGLECTRL_INPUTSEL(0) -#define ADC_SINGLECTRL_INPUTSEL_CH2CH3 ADC_SINGLECTRL_INPUTSEL(1) -#define ADC_SINGLECTRL_INPUTSEL_CH4CH5 ADC_SINGLECTRL_INPUTSEL(2) -#define ADC_SINGLECTRL_INPUTSEL_CH6CH7 ADC_SINGLECTRL_INPUTSEL(3) -#define ADC_SINGLECTRL_INPUTSEL_DIFF0 ADC_SINGLECTRL_INPUTSEL(4) - -#define ADC_SINGLECTRL_RES_SHIFT (4) -#define ADC_SINGLECTRL_RES_MASK (0x3 << ADC_SINGLECTRL_RES_SHIFT) -#define ADC_SINGLECTRL_RES(v) \ - (((v) << ADC_SINGLECTRL_RES_SHIFT) & ADC_SINGLECTRL_RES_MASK) -#define ADC_SINGLECTRL_RES_12BIT ADC_SINGLECTRL_RES(0) -#define ADC_SINGLECTRL_RES_8BIT ADC_SINGLECTRL_RES(1) -#define ADC_SINGLECTRL_RES_6BIT ADC_SINGLECTRL_RES(2) -#define ADC_SINGLECTRL_RES_OVS ADC_SINGLECTRL_RES(3) - -#define ADC_SINGLECTRL_ADJ (1 << 2) -#define ADC_SINGLECTRL_DIFF (1 << 1) -#define ADC_SINGLECTRL_REP (1 << 0) - -/* ADC_SCANCTRL */ -#define ADC_SCANCTRL_PRSSEL_SHIFT (28) -#define ADC_SCANCTRL_PRSSEL_MASK (0xF << ADC_SCANCTRL_PRSSEL_SHIFT) -#define ADC_SCANCTRL_PRSSEL(v) \ - (((v) << ADC_SCANCTRL_PRSSEL_SHIFT) & ADC_SCANCTRL_PRSSEL_MASK) -#define ADC_SCANCTRL_PRSSEL_PRSCHx(x) ADC_SCANCTRL_PRSSEL(x) -#define ADC_SCANCTRL_PRSSEL_PRSCH0 ADC_SCANCTRL_PRSSEL_PRSCHx(0) -#define ADC_SCANCTRL_PRSSEL_PRSCH1 ADC_SCANCTRL_PRSSEL_PRSCHx(1) -#define ADC_SCANCTRL_PRSSEL_PRSCH2 ADC_SCANCTRL_PRSSEL_PRSCHx(2) -#define ADC_SCANCTRL_PRSSEL_PRSCH3 ADC_SCANCTRL_PRSSEL_PRSCHx(3) -#define ADC_SCANCTRL_PRSSEL_PRSCH4 ADC_SCANCTRL_PRSSEL_PRSCHx(4) -#define ADC_SCANCTRL_PRSSEL_PRSCH5 ADC_SCANCTRL_PRSSEL_PRSCHx(5) -#define ADC_SCANCTRL_PRSSEL_PRSCH6 ADC_SCANCTRL_PRSSEL_PRSCHx(6) -#define ADC_SCANCTRL_PRSSEL_PRSCH7 ADC_SCANCTRL_PRSSEL_PRSCHx(7) -#define ADC_SCANCTRL_PRSSEL_PRSCH8 ADC_SCANCTRL_PRSSEL_PRSCHx(8) -#define ADC_SCANCTRL_PRSSEL_PRSCH9 ADC_SCANCTRL_PRSSEL_PRSCHx(9) -#define ADC_SCANCTRL_PRSSEL_PRSCH10 ADC_SCANCTRL_PRSSEL_PRSCHx(10) -#define ADC_SCANCTRL_PRSSEL_PRSCH11 ADC_SCANCTRL_PRSSEL_PRSCHx(11) - -#define ADC_SCANCTRL_PRSEN (1 << 24) - -#define ADC_SCANCTRL_AT_SHIFT (20) -#define ADC_SCANCTRL_AT_MASK (0xF << ADC_SCANCTRL_AT_SHIFT) -#define ADC_SCANCTRL_AT(v) \ - (((v) << ADC_SCANCTRL_AT_SHIFT) & ADC_SCANCTRL_AT_MASK) -#define ADC_SCANCTRL_AT_1CYCLE ADC_SCANCTRL_AT(0) -#define ADC_SCANCTRL_AT_2CYCLES ADC_SCANCTRL_AT(1) -#define ADC_SCANCTRL_AT_4CYCLES ADC_SCANCTRL_AT(2) -#define ADC_SCANCTRL_AT_8CYCLES ADC_SCANCTRL_AT(3) -#define ADC_SCANCTRL_AT_16CYCLES ADC_SCANCTRL_AT(4) -#define ADC_SCANCTRL_AT_32CYCLES ADC_SCANCTRL_AT(5) -#define ADC_SCANCTRL_AT_64CYCLES ADC_SCANCTRL_AT(6) -#define ADC_SCANCTRL_AT_128CYCLES ADC_SCANCTRL_AT(7) -#define ADC_SCANCTRL_AT_256CYCLES ADC_SCANCTRL_AT(8) - -#define ADC_SCANCTRL_REF_SHIFT (16) -#define ADC_SCANCTRL_REF_MASK (0xF << ADC_SCANCTRL_REF_SHIFT) -#define ADC_SCANCTRL_REF(v) \ - (((v) << ADC_SCANCTRL_REF_SHIFT) & ADC_SCANCTRL_REF_MASK) -#define ADC_SCANCTRL_REF_1V25 ADC_SCANCTRL_REF(0) -#define ADC_SCANCTRL_REF_2V5 ADC_SCANCTRL_REF(1) -#define ADC_SCANCTRL_REF_VDD ADC_SCANCTRL_REF(2) -#define ADC_SCANCTRL_REF_5VDIFF ADC_SCANCTRL_REF(3) -#define ADC_SCANCTRL_REF_EXTSCAN ADC_SCANCTRL_REF(4) -#define ADC_SCANCTRL_REF_2XEXTDIFF ADC_SCANCTRL_REF(5) -#define ADC_SCANCTRL_REF_2XVDD ADC_SCANCTRL_REF(6) - - -#define ADC_SCANCTRL_INPUTSEL_SHIFT (8) -#define ADC_SCANCTRL_INPUTSEL_MASK (0xFF << ADC_SCANCTRL_INPUTSEL_SHIFT) -#define ADC_SCANCTRL_INPUTSEL(v) \ - (((v) << ADC_SCANCTRL_INPUTSEL_SHIFT) & ADC_SCANCTRL_INPUTSEL_MASK) -/* DIFF=0 */ -#define ADC_SCANCTRL_INPUTSEL_CHx(x) ADC_SCANCTRL_INPUTSEL(1 << (x)) -#define ADC_SCANCTRL_INPUTSEL_CH0 ADC_SCANCTRL_INPUTSEL_CHx(0) -#define ADC_SCANCTRL_INPUTSEL_CH1 ADC_SCANCTRL_INPUTSEL_CHx(1) -#define ADC_SCANCTRL_INPUTSEL_CH2 ADC_SCANCTRL_INPUTSEL_CHx(2) -#define ADC_SCANCTRL_INPUTSEL_CH3 ADC_SCANCTRL_INPUTSEL_CHx(3) -#define ADC_SCANCTRL_INPUTSEL_CH4 ADC_SCANCTRL_INPUTSEL_CHx(4) -#define ADC_SCANCTRL_INPUTSEL_CH5 ADC_SCANCTRL_INPUTSEL_CHx(5) -#define ADC_SCANCTRL_INPUTSEL_CH6 ADC_SCANCTRL_INPUTSEL_CHx(6) -#define ADC_SCANCTRL_INPUTSEL_CH7 ADC_SCANCTRL_INPUTSEL_CHx(7) -/* DIFF=1 */ -#define ADC_SCANCTRL_INPUTSEL_CH0CH1 ADC_SCANCTRL_INPUTSEL(1 << 0) -#define ADC_SCANCTRL_INPUTSEL_CH2CH3 ADC_SCANCTRL_INPUTSEL(1 << 1) -#define ADC_SCANCTRL_INPUTSEL_CH4CH5 ADC_SCANCTRL_INPUTSEL(1 << 2) -#define ADC_SCANCTRL_INPUTSEL_CH6CH7 ADC_SCANCTRL_INPUTSEL(1 << 3) - -#define ADC_SCANCTRL_RES_SHIFT (4) -#define ADC_SCANCTRL_RES_MASK (0x3 << ADC_SCANCTRL_RES_SHIFT) -#define ADC_SCANCTRL_RES(v) \ - (((v) << ADC_SCANCTRL_RES_SHIFT) & ADC_SCANCTRL_RES_MASK) -#define ADC_SCANCTRL_RES_12BIT ADC_SCANCTRL_RES(0) -#define ADC_SCANCTRL_RES_8BIT ADC_SCANCTRL_RES(1) -#define ADC_SCANCTRL_RES_6BIT ADC_SCANCTRL_RES(2) -#define ADC_SCANCTRL_RES_OVS ADC_SCANCTRL_RES(3) - -#define ADC_SCANCTRL_ADJ (1 << 2) -#define ADC_SCANCTRL_DIFF (1 << 1) -#define ADC_SCANCTRL_REP (1 << 0) - -/* ADC_IEN */ -#define ADC_IEN_SCANOF (1 << 9) -#define ADC_IEN_SINGLEOF (1 << 8) -#define ADC_IEN_SCAN (1 << 1) -#define ADC_IEN_SINGLE (1 << 0) - -/* ADC_IF */ -#define ADC_IF_SCANOF (1 << 9) -#define ADC_IF_SINGLEOF (1 << 8) -#define ADC_IF_SCAN (1 << 1) -#define ADC_IF_SINGLE (1 << 0) - -/* ADC_IFS */ -#define ADC_IFS_SCANOF (1 << 9) -#define ADC_IFS_SINGLEOF (1 << 8) -#define ADC_IFS_SCAN (1 << 1) -#define ADC_IFS_SINGLE (1 << 0) - -/* ADC_IFC */ -#define ADC_IFC_SCANOF (1 << 9) -#define ADC_IFC_SINGLEOF (1 << 8) -#define ADC_IFC_SCAN (1 << 1) -#define ADC_IFC_SINGLE (1 << 0) - -/* ADC_CAL */ -#define ADC_CAL_SCANGAIN_SHIFT (24) -#define ADC_CAL_SCANGAIN_MASK (0x7F) - -#define ADC_CAL_SCANOFF_SHIFT (16) -#define ADC_CAL_SCANOFF_MASK (0x7F) - -#define ADC_CAL_SINGLEGAIN_SHIFT (8) -#define ADC_CAL_SINGLEGAIN_MASK (0x7F) - -#define ADC_CAL_SINGLEOFF_SHIFT (0) -#define ADC_CAL_SINGLEOFF_MASK (0x7F) - -/* ADC_BIASPROG */ -#define ADC_BIASPROG_COMPBIAS_SHIFT (8) -#define ADC_BIASPROG_COMPBIAS_MASK (0xF) - -#define ADC_BIASPROG_HALFBIAS (1 << 6) - -#define ADC_BIASPROG_BIASPROG_SHIFT (0) -#define ADC_BIASPROG_BIASPROG_MASK (0xF) - -/* ADC0 */ -#define ADC0 ADC0_BASE -#define ADC0_CTRL ADC_CTRL(ADC0) -#define ADC0_CMD ADC_CMD(ADC0) -#define ADC0_STATUS ADC_STATUS(ADC0) -#define ADC0_SINGLECTRL ADC_SINGLECTRL(ADC0) -#define ADC0_SCANCTRL ADC_SCANCTRL(ADC0) -#define ADC0_IEN ADC_IEN(ADC0) -#define ADC0_IF ADC_IF(ADC0) -#define ADC0_IFS ADC_IFS(ADC0) -#define ADC0_IFC ADC_IFC(ADC0) -#define ADC0_SINGLEDATA ADC_SINGLEDATA(ADC0) -#define ADC0_SCANDATA ADC_SCANDATA(ADC0) -#define ADC0_SINGLEDATAP ADC_SINGLEDATAP(ADC0) -#define ADC0_SCANDATAP ADC_SCANDATAP(ADC0) -#define ADC0_CAL ADC_CAL(ADC0) -#define ADC0_BIASPROG ADC_BIASPROG(ADC0) - -/** @defgroup adc_ch ADC Channel Number -@ingroup adc_defines - -@{*/ -#define ADC_CH0 0 -#define ADC_CH1 1 -#define ADC_CH2 2 -#define ADC_CH3 3 -#define ADC_CH4 4 -#define ADC_CH5 5 -#define ADC_CH6 6 -#define ADC_CH7 7 -#define ADC_CH_TEMP 8 -#define ADC_CH_VDDDIV3 9 -#define ADC_CH_VDD 10 -#define ADC_CH_VSS 11 -#define ADC_CH_VREFDIV2 12 -#define ADC_CH_DAC0OUT0 13 -#define ADC_CH_DAC0OUT1 14 - -#define ADC_CH_CH0CH1 0 -#define ADC_CH_CH2CH3 1 -#define ADC_CH_CH4CH5 2 -#define ADC_CH_CH6CH7 3 -#define ADC_CH_DIFF0 4 -/**@}*/ - -BEGIN_DECLS - -void adc_set_oversampling(uint32_t adc, uint32_t oversamp); -void adc_set_warm_up(uint32_t adc, uint8_t clocks); -void adc_set_clock_prescaler(uint32_t adc, uint8_t factor); -void adc_set_lowpass_filter(uint32_t adc, uint32_t lpfmode); - -void adc_enable_tailgating(uint32_t adc); -void adc_disable_tailgating(uint32_t adc); - -void adc_set_warm_up_mode(uint32_t adc, uint32_t warmupmode); - -void adc_single_start(uint32_t adc); -void adc_single_stop(uint32_t adc); - -void adc_scan_start(uint32_t adc); -void adc_scan_stop(uint32_t adc); - -/* TODO: ADC_STATUS */ - -void adc_set_single_prs_trigger(uint32_t adc, uint8_t prssel); -void adc_enable_single_prs_trigger(uint32_t adc); -void adc_disable_single_prs_trigger(uint32_t adc); -void adc_set_single_acquisition_cycle(uint32_t adc, uint32_t at); -void adc_set_single_reference(uint32_t adc, uint32_t ref); -void adc_set_single_channel(uint32_t adc, uint8_t ch); -void adc_set_single_resolution(uint32_t adc, uint32_t res); -void adc_set_single_left_aligned(uint32_t adc); -void adc_set_single_right_aligned(uint32_t adc); -void adc_set_single_single_ended(uint32_t adc); -void adc_set_single_differential(uint32_t adc); -void adc_enable_single_repeat_conv(uint32_t adc); -void adc_disable_single_repeat_conv(uint32_t adc); - -void adc_set_scan_prs_trigger(uint32_t adc, uint8_t prssel); -void adc_enable_scan_prs_trigger(uint32_t adc); -void adc_disable_scan_prs_trigger(uint32_t adc); -void adc_set_scan_acquisition_cycle(uint32_t adc, uint32_t at); -void adc_set_scan_reference(uint32_t adc, uint32_t ref); -void adc_set_scan_channel(uint32_t adc, uint8_t length, - uint8_t channel[]); -void adc_set_scan_resolution(uint32_t adc, uint32_t res); -void adc_set_scan_left_aligned(uint32_t adc); -void adc_set_scan_right_aligned(uint32_t adc); -void adc_set_scan_single_ended(uint32_t adc); -void adc_set_scan_differential(uint32_t adc); -void adc_enable_scan_repeat_conv(uint32_t adc); -void adc_disable_scan_repeat_conv(uint32_t adc); - -void adc_enable_single_result_overflow_interrupt(uint32_t adc); -void adc_disable_single_result_overflow_interrupt(uint32_t adc); -void adc_enable_single_conversion_complete_interrupt(uint32_t adc); -void adc_disable_single_conversion_complete_interrupt(uint32_t adc); -void adc_enable_scan_result_overflow_interrupt(uint32_t adc); -void adc_disable_scan_result_overflow_interrupt(uint32_t adc); -void adc_enable_scan_conversion_complete_interrupt(uint32_t adc); -void adc_disable_scan_conversion_complete_interrupt(uint32_t adc); - -bool adc_get_single_result_overflow_flag(uint32_t adc); -bool adc_get_single_conversion_complete_flag(uint32_t adc); -bool adc_get_scan_result_overflow_flag(uint32_t adc); -bool adc_get_scan_conversion_complete_flag(uint32_t adc); - -void adc_set_single_result_overflow_flag(uint32_t adc); -void adc_set_single_conversion_complete_flag(uint32_t adc); -void adc_set_scan_result_overflow_flag(uint32_t adc); -void adc_set_scan_conversion_complete_flag(uint32_t adc); - -void adc_clear_single_result_overflow_flag(uint32_t adc); -void adc_clear_single_conversion_complete_flag(uint32_t adc); -void adc_clear_scan_result_overflow_flag(uint32_t adc); -void adc_clear_scan_conversion_complete_flag(uint32_t adc); - -uint32_t adc_single_data(uint32_t adc); -uint32_t adc_scan_data(uint32_t adc); - -uint32_t adc_single_data_peak(uint32_t adc); -uint32_t adc_scan_data_peak(uint32_t adc); - -void adc_set_calibration_scan_gain(uint32_t adc, uint8_t scan_gain); -void adc_set_calibration_scan_offset(uint32_t adc, uint8_t scan_offset); - -void adc_set_calibration_single_gain(uint32_t adc, uint8_t single_gain); -void adc_set_calibration_single_offset(uint32_t adc, uint8_t single_offset); - -END_DECLS +#include #endif - diff --git a/include/libopencm3/efm32/lg/burtc.h b/include/libopencm3/efm32/lg/burtc.h index 321c9bbb..132c3d02 100644 --- a/include/libopencm3/efm32/lg/burtc.h +++ b/include/libopencm3/efm32/lg/burtc.h @@ -1,7 +1,7 @@ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2015 Kuldeep Singh Dhaka + * Copyright (C) 2016 Bob Miller * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -17,154 +17,9 @@ * along with this library. If not, see . */ -#ifndef LIBOPENCM3_EFM32_BURTC_H -#define LIBOPENCM3_EFM32_BURTC_H +#ifndef LIBOPENCM3_EFM32_LG_BURTC_H +#define LIBOPENCM3_EFM32_LG_BURTC_H -#include -#include - -#define BURTC_CTRL MMIO32(BURTC_BASE + 0x000) -#define BURTC_LPMODE MMIO32(BURTC_BASE + 0x004) -#define BURTC_CNT MMIO32(BURTC_BASE + 0x008) -#define BURTC_COMP0 MMIO32(BURTC_BASE + 0x00C) -#define BURTC_TIMESTAMP MMIO32(BURTC_BASE + 0x010) -#define BURTC_LFXOFDET MMIO32(BURTC_BASE + 0x014) -#define BURTC_STATUS MMIO32(BURTC_BASE + 0x018) -#define BURTC_CMD MMIO32(BURTC_BASE + 0x01C) -#define BURTC_POWERDOWN MMIO32(BURTC_BASE + 0x020) -#define BURTC_LOCK MMIO32(BURTC_BASE + 0x024) -#define BURTC_IF MMIO32(BURTC_BASE + 0x028) -#define BURTC_IFS MMIO32(BURTC_BASE + 0x02C) -#define BURTC_IFC MMIO32(BURTC_BASE + 0x030) -#define BURTC_IEN MMIO32(BURTC_BASE + 0x034) -#define BURTC_FREEZE MMIO32(BURTC_BASE + 0x038) -#define BURTC_SYNCBUSY MMIO32(BURTC_BASE + 0x03C) - -#define RETx_REG(x) MMIO32(BURTC_BASE + 0x100 + (4 * (x))) -/* [for ease] */ -#define BURTC_RETx(x) RETx_REG(x) - -/* BURTC_CTRL */ -#define BURTC_CTRL_BUMODETSEN (1 << 14) - -#define BURTC_CTRL_CLKSEL_SHIFT (8) -#define BURTC_CTRL_CLKSEL_MASK (0x3 << BURTC_CTRL_CLKSEL_SHIFT) -#define BURTC_CTRL_CLKSEL(v) \ - (((v) << BURTC_CTRL_CLKSEL_SHIFT) & BURTC_CTRL_CLKSEL_MASK) -#define BURTC_CTRL_CLKSEL_NONE BURTC_CTRL_CLKSEL(0) -#define BURTC_CTRL_CLKSEL_LFRCO BURTC_CTRL_CLKSEL(1) -#define BURTC_CTRL_CLKSEL_LFXO BURTC_CTRL_CLKSEL(2) -#define BURTC_CTRL_CLKSEL_ULFRCO BURTC_CTRL_CLKSEL(3) - -#define BURTC_CTRL_PRESC_SHIFT (12) -#define BURTC_CTRL_PRESC_MASK (0x7 << BURTC_CTRL_PRESC_SHIFT) -#define BURTC_CTRL_PRESC(v) \ - (((v) << BURTC_CTRL_PRESC_SHIFT) & BURTC_CTRL_PRESC_MASK) -#define BURTC_CTRL_PRESC_DIV1 BURTC_CTRL_PRESC(0) -#define BURTC_CTRL_PRESC_DIV2 BURTC_CTRL_PRESC(1) -#define BURTC_CTRL_PRESC_DIV4 BURTC_CTRL_PRESC(2) -#define BURTC_CTRL_PRESC_DIV8 BURTC_CTRL_PRESC(3) -#define BURTC_CTRL_PRESC_DIV16 BURTC_CTRL_PRESC(4) -#define BURTC_CTRL_PRESC_DIV32 BURTC_CTRL_PRESC(5) -#define BURTC_CTRL_PRESC_DIV64 BURTC_CTRL_PRESC(6) -#define BURTC_CTRL_PRESC_DIV128 BURTC_CTRL_PRESC(7) -#define BURTC_CTRL_PRESC_NODIV BURTC_CTRL_PRESC_DIV1 - -#define BURTC_CTRL_LPCOMPC_SHIFT (5) -#define BURTC_CTRL_LPCOMPC_MASK (0x7 << BURTC_CTRL_LPCOMPC_SHIFT) -#define BURTC_CTRL_LPCOMPC(v) \ - (((v) << BURTC_CTRL_LPCOMPC_SHIFT) & BURTC_CTRL_LPCOMPC_MASK) -#define BURTC_CTRL_LPCOMPC_IGNxLSB(x) BURTC_CTRL_LPCOMPC(x) -#define BURTC_CTRL_LPCOMPC_IGN0LSB BURTC_CTRL_LPCOMPC_IGNxLSB(0) -#define BURTC_CTRL_LPCOMPC_IGN1LSB BURTC_CTRL_LPCOMPC_IGNxLSB(1) -#define BURTC_CTRL_LPCOMPC_IGN2LSB BURTC_CTRL_LPCOMPC_IGNxLSB(2) -#define BURTC_CTRL_LPCOMPC_IGN3LSB BURTC_CTRL_LPCOMPC_IGNxLSB(3) -#define BURTC_CTRL_LPCOMPC_IGN4LSB BURTC_CTRL_LPCOMPC_IGNxLSB(4) -#define BURTC_CTRL_LPCOMPC_IGN5LSB BURTC_CTRL_LPCOMPC_IGNxLSB(5) -#define BURTC_CTRL_LPCOMPC_IGN6LSB BURTC_CTRL_LPCOMPC_IGNxLSB(6) -#define BURTC_CTRL_LPCOMPC_IGN7LSB BURTC_CTRL_LPCOMPC_IGNxLSB(7) - -#define BURTC_CTRL_COMP0TOP (1 << 4) -#define BURTC_CTRL_RSTEN (1 << 3) -#define BURTC_CTRL_DEBUGRUN (1 << 2) - -#define BURTC_CTRL_MODE_SHIFT (0) -#define BURTC_CTRL_MODE_MASK (0x3 << BURTC_CTRL_MODE_SHIFT) -#define BURTC_CTRL_MODE(v) \ - (((v) << BURTC_CTRL_MODE_SHIFT) & BURTC_CTRL_MODE_MASK) -#define BURTC_CTRL_MODE_DISABLE BURTC_CTRL_MODE(0) -#define BURTC_CTRL_MODE_EM2EN BURTC_CTRL_MODE(1) -#define BURTC_CTRL_MODE_EM3EN BURTC_CTRL_MODE(2) -#define BURTC_CTRL_MODE_EM4EN BURTC_CTRL_MODE(3) - -/* BURTC_LPMODE */ -#define BURTC_LPMODE_LPMODE_SHIFT (0) -#define BURTC_LPMODE_LPMODE_MASK (0x3 << BURTC_LPMODE_LPMODE_SHIFT) -#define BURTC_LPMODE_LPMODE(v) \ - (((v) << BURTC_LPMODE_LPMODE_SHIFT) & BURTC_LPMODE_LPMODE_MASK) -#define BURTC_LPMODE_LPMODE_DISABLE BURTC_LPMODE_LPMODE(0) -#define BURTC_LPMODE_LPMODE_ENABLE BURTC_LPMODE_LPMODE(1) -#define BURTC_LPMODE_LPMODE_BUEN BURTC_LPMODE_LPMODE(2) - -/* BURTC_LFXOFDET */ -#define BURTC_LFXOFDET_TOP_SHIFT (4) -#define BURTC_LFXOFDET_TOP_MASK (0xF << BURTC_LFXOFDET_TOP_SHIFT) -#define BURTC_LFXOFDET_TOP(v) \ - (((v) << BURTC_LFXOFDET_TOP_SHIFT) & BURTC_LFXOFDET_TOP_MASK) - -#define BURTC_LFXOFDET_OSC_SHIFT (0) -#define BURTC_LFXOFDET_OSC_MASK (0x3 << BURTC_LFXOFDET_OSC_SHIFT) -#define BURTC_LFXOFDET_OSC(v) \ - (((v) << BURTC_LFXOFDET_OSC_SHIFT) & BURTC_LFXOFDET_OSC_MASK) -#define BURTC_LFXOFDET_OSC_DISABLE BURTC_LFXOFDET_OSC(0) -#define BURTC_LFXOFDET_OSC_LFRCO BURTC_LFXOFDET_OSC(1) -#define BURTC_LFXOFDET_OSC_ULFRCO BURTC_LFXOFDET_OSC(2) - -/* BURTC_STATUS */ -#define BURTC_STATUS_RAMWERR (1 << 2) -#define BURTC_STATUS_BUMODETS (1 << 1) -#define BURTC_STATUS_LPMODEACT (1 << 0) - -/* BURTC_CMD */ -#define BURTC_CMD_CLRSTATUS (1 << 0) - -/* BURTC_POWERDOWN */ -#define BURTC_POWERDOWN_RAM (1 << 0) - -/* BURTC_LOCK */ -#define BURTC_LOCK_LOCKKEY_SHIFT (0) -#define BURTC_LOCK_LOCKKEY_MASK (0xFFFF << BURTC_LOCK_LOCKKEY_SHIFT) -#define BURTC_LOCK_LOCKKEY_UNLOCKED (0x0000 << BURTC_LOCK_LOCKKEY_SHIFT) -#define BURTC_LOCK_LOCKKEY_LOCKED (0x0001 << BURTC_LOCK_LOCKKEY_SHIFT) -#define BURTC_LOCK_LOCKKEY_LOCK (0x0000 << BURTC_LOCK_LOCKKEY_SHIFT) -#define BURTC_LOCK_LOCKKEY_UNLOCK (0xAEE8 << BURTC_LOCK_LOCKKEY_SHIFT) - -/* BURTC_IF */ -#define BURTC_IF_LFXOFAIL (1 << 2) -#define BURTC_IF_COMP0 (1 << 1) -#define BURTC_IF_OF (1 << 0) - -/* BURTC_IFS */ -#define BURTC_IFS_LFXOFAIL (1 << 2) -#define BURTC_IFS_COMP0 (1 << 1) -#define BURTC_IFS_OF (1 << 0) - -/* BURTC_IFC */ -#define BURTC_IFC_LFXOFAIL (1 << 2) -#define BURTC_IFC_COMP0 (1 << 1) -#define BURTC_IFC_OF (1 << 0) - -/* BURTC_IEN */ -#define BURTC_IEN_LFXOFAIL (1 << 2) -#define BURTC_IEN_COMP0 (1 << 1) -#define BURTC_IEN_OF (1 << 0) - -/* BURTC_FREEZE */ -#define BURTC_FREEZE_REGFREEZE (1 << 0) - -/* BURTC_SYNCBUSY */ -#define BURTC_SYNCBUSY_COMP0 (1 << 1) -#define BURTC_SYNCBUSY_LPMODE (1 << 0) +#include #endif - diff --git a/include/libopencm3/efm32/lg/cmu.h b/include/libopencm3/efm32/lg/cmu.h index 0239dccd..a567a30c 100644 --- a/include/libopencm3/efm32/lg/cmu.h +++ b/include/libopencm3/efm32/lg/cmu.h @@ -1,7 +1,7 @@ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2015 Kuldeep Singh Dhaka + * Copyright (C) 2016 Bob Miller * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -17,689 +17,10 @@ * along with this library. If not, see . */ -#ifndef LIBOPENCM3_EFM32_CMU_H -#define LIBOPENCM3_EFM32_CMU_H +#ifndef LIBOPENCM3_EFM32_LG_CMU_H +#define LIBOPENCM3_EFM32_LG_CMU_H -#include -#include - -#define CMU_CTRL MMIO32(CMU_BASE + 0x000) -#define CMU_HFCORECLKDIV MMIO32(CMU_BASE + 0x004) -#define CMU_HFPERCLKDIV MMIO32(CMU_BASE + 0x008) -#define CMU_HFRCOCTRL MMIO32(CMU_BASE + 0x00C) -#define CMU_LFRCOCTRL MMIO32(CMU_BASE + 0x010) -#define CMU_AUXHFRCOCTRL MMIO32(CMU_BASE + 0x014) -#define CMU_CALCTRL MMIO32(CMU_BASE + 0x018) -#define CMU_CALCNT MMIO32(CMU_BASE + 0x01C) -#define CMU_OSCENCMD MMIO32(CMU_BASE + 0x020) -#define CMU_CMD MMIO32(CMU_BASE + 0x024) -#define CMU_LFCLKSEL MMIO32(CMU_BASE + 0x028) -#define CMU_STATUS MMIO32(CMU_BASE + 0x02C) -#define CMU_IF MMIO32(CMU_BASE + 0x030) -#define CMU_IFS MMIO32(CMU_BASE + 0x034) -#define CMU_IFC MMIO32(CMU_BASE + 0x038) -#define CMU_IEN MMIO32(CMU_BASE + 0x03C) -#define CMU_HFCORECLKEN0 MMIO32(CMU_BASE + 0x040) -#define CMU_HFPERCLKEN0 MMIO32(CMU_BASE + 0x044) -#define CMU_SYNCBUSY MMIO32(CMU_BASE + 0x050) -#define CMU_FREEZE MMIO32(CMU_BASE + 0x054) -#define CMU_LFACLKEN0 MMIO32(CMU_BASE + 0x058) -#define CMU_LFBCLKEN0 MMIO32(CMU_BASE + 0x060) -#define CMU_LFAPRESC0 MMIO32(CMU_BASE + 0x068) -#define CMU_LFBPRESC0 MMIO32(CMU_BASE + 0x070) -#define CMU_PCNTCTRL MMIO32(CMU_BASE + 0x078) -#define CMU_LCDCTRL MMIO32(CMU_BASE + 0x07C) -#define CMU_ROUTE MMIO32(CMU_BASE + 0x080) -#define CMU_LOCK MMIO32(CMU_BASE + 0x084) - -/* CMU_CTRL */ -#define CMU_CTRL_HFLE (1 << 30) -#define CMU_CTRL_DBGCLK (1 << 28) - - -#define CMU_CTRL_CLKOUTSEL1_SHIFT (23) -#define CMU_CTRL_CLKOUTSEL1_MASK (0x7 << CMU_CTRL_CLKOUTSEL1_SHIFT) -#define CMU_CTRL_CLKOUTSEL1(v) \ - (((v) << CMU_CTRL_CLKOUTSEL1_SHIFT) & CMU_CTRL_CLKOUTSEL1_MASK) -#define CMU_CTRL_CLKOUTSEL1_LFRCO CMU_CTRL_CLKOUTSEL1(0) -#define CMU_CTRL_CLKOUTSEL1_LFXO CMU_CTRL_CLKOUTSEL1(1) -#define CMU_CTRL_CLKOUTSEL1_HFCLK CMU_CTRL_CLKOUTSEL1(2) -#define CMU_CTRL_CLKOUTSEL1_LFXOQ CMU_CTRL_CLKOUTSEL1(3) -#define CMU_CTRL_CLKOUTSEL1_HFXOQ CMU_CTRL_CLKOUTSEL1(4) -#define CMU_CTRL_CLKOUTSEL1_LFRCOQ CMU_CTRL_CLKOUTSEL1(5) -#define CMU_CTRL_CLKOUTSEL1_HFRCOQ CMU_CTRL_CLKOUTSEL1(6) -#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ CMU_CTRL_CLKOUTSEL1(7) - -#define CMU_CTRL_CLKOUTSEL0_SHIFT (23) -#define CMU_CTRL_CLKOUTSEL0_MASK (0x7 << CMU_CTRL_CLKOUTSEL0_SHIFT) -#define CMU_CTRL_CLKOUTSEL0(v) \ - (((v) << CMU_CTRL_CLKOUTSEL0_SHIFT) & CMU_CTRL_CLKOUTSEL0_MASK) -#define CMU_CTRL_CLKOUTSEL0_HFRCO CMU_CTRL_CLKOUTSEL0(0) -#define CMU_CTRL_CLKOUTSEL0_HFXO CMU_CTRL_CLKOUTSEL0(1) -#define CMU_CTRL_CLKOUTSEL0_HFCLK2 CMU_CTRL_CLKOUTSEL0(2) -#define CMU_CTRL_CLKOUTSEL0_HFCLK4 CMU_CTRL_CLKOUTSEL0(3) -#define CMU_CTRL_CLKOUTSEL0_HFCLK8 CMU_CTRL_CLKOUTSEL0(4) -#define CMU_CTRL_CLKOUTSEL0_HFCLK16 CMU_CTRL_CLKOUTSEL0(5) -#define CMU_CTRL_CLKOUTSEL0_ULFRCO CMU_CTRL_CLKOUTSEL0(6) -#define CMU_CTRL_CLKOUTSEL0_AUXHFRCO CMU_CTRL_CLKOUTSEL0(7) - -#define CMU_CTRL_LFXOTIMEOUT_SHIFT (18) -#define CMU_CTRL_LFXOTIMEOUT_MASK (0x3 << CMU_CTRL_LFXOTIMEOUT_SHIFT) -#define CMU_CTRL_LFXOTIMEOUT(v) \ - (((v) << CMU_CTRL_LFXOTIMEOUT_SHIFT) & CMU_CTRL_LFXOTIMEOUT_MASK) -#define CMU_CTRL_LFXOTIMEOUT_8CYCLES CMU_CTRL_LFXOTIMEOUT(0) -#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES CMU_CTRL_LFXOTIMEOUT(1) -#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES CMU_CTRL_LFXOTIMEOUT(2) -#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES CMU_CTRL_LFXOTIMEOUT(3) - -#define CMU_CTRL_LFXOBUFCUR (1 << 17) - -#define CMU_CTRL_HFCLKDIV_SHIFT (14) -#define CMU_CTRL_HFCLKDIV_MASK (0x7 << CMU_CTRL_HFCLKDIV_SHIFT) -#define CMU_CTRL_HFCLKDIV(v) \ - (((v) << CMU_CTRL_HFCLKDIV_SHIFT) & CMU_CTRL_HFCLKDIV_MASK) -#define CMU_CTRL_HFCLKDIV_NODIV CMU_CTRL_HFCLKDIV(0) -#define CMU_CTRL_HFCLKDIV_DIV2 CMU_CTRL_HFCLKDIV(1) -#define CMU_CTRL_HFCLKDIV_DIV3 CMU_CTRL_HFCLKDIV(2) -#define CMU_CTRL_HFCLKDIV_DIV4 CMU_CTRL_HFCLKDIV(3) -#define CMU_CTRL_HFCLKDIV_DIV5 CMU_CTRL_HFCLKDIV(4) -#define CMU_CTRL_HFCLKDIV_DIV6 CMU_CTRL_HFCLKDIV(5) -#define CMU_CTRL_HFCLKDIV_DIV7 CMU_CTRL_HFCLKDIV(6) -#define CMU_CTRL_HFCLKDIV_DIV8 CMU_CTRL_HFCLKDIV(7) - -#define CMU_CTRL_LFXOBOOST (1 << 13) - -#define CMU_CTRL_LFXOMODE_SHIFT (11) -#define CMU_CTRL_LFXOMODE_MASK (0x3 << CMU_CTRL_LFXOMODE_SHIFT) -#define CMU_CTRL_LFXOMODE(v) \ - (((v) << CMU_CTRL_LFXOMODE_SHIFT) & CMU_CTRL_LFXOMODE_MASK) -#define CMU_CTRL_LFXOMODE_XTAL CMU_CTRL_LFXOMODE(0) -#define CMU_CTRL_LFXOMODE_BUFEXTCLK CMU_CTRL_LFXOMODE(1) -#define CMU_CTRL_LFXOMODE_DIGEXTCLK CMU_CTRL_LFXOMODE(2) - -#define CMU_CTRL_HFXOTIMEOUT_SHIFT (9) -#define CMU_CTRL_HFXOTIMEOUT_MASK (0x3 << CMU_CTRL_HFXOTIMEOUT_SHIFT) -#define CMU_CTRL_HFXOTIMEOUT(v) \ - (((v) << CMU_CTRL_HFXOTIMEOUT_SHIFT) & CMU_CTRL_HFXOTIMEOUT_MASK) -#define CMU_CTRL_HFXOTIMEOUT_8CYCLES CMU_CTRL_HFXOTIMEOUT(0) -#define CMU_CTRL_HFXOTIMEOUT_256CYCLES CMU_CTRL_HFXOTIMEOUT(1) -#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES CMU_CTRL_HFXOTIMEOUT(2) -#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES CMU_CTRL_HFXOTIMEOUT(3) - -#define CMU_CTRL_HFXOGLITCHDETEN (1 << 7) - -#define CMU_CTRL_HFXOBUFCUR_SHIFT (5) -#define CMU_CTRL_HFXOBUFCUR_MASK (0x3 << CMU_CTRL_HFXOBUFCUR_SHIFT) -#define CMU_CTRL_HFXOBUFCUR(v) \ - (((v) << CMU_CTRL_HFXOBUFCUR_SHIFT) & CMU_CTRL_HFXOBUFCUR_MASK) -#define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ CMU_CTRL_HFXOBUFCUR(1) -#define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ CMU_CTRL_HFXOBUFCUR(3) - -#define CMU_CTRL_HFXOBOOST_SHIFT (2) -#define CMU_CTRL_HFXOBOOST_MASK (0x3 << CMU_CTRL_HFXOBOOST_SHIFT) -#define CMU_CTRL_HFXOBOOST(v) \ - (((v) << CMU_CTRL_HFXOBOOST_SHIFT) & CMU_CTRL_HFXOBOOST_MASK) -#define CMU_CTRL_HFXOBOOST_50PCENT CMU_CTRL_HFXOBOOST(0) -#define CMU_CTRL_HFXOBOOST_70PCENT CMU_CTRL_HFXOBOOST(1) -#define CMU_CTRL_HFXOBOOST_80PCENT CMU_CTRL_HFXOBOOST(2) -#define CMU_CTRL_HFXOBOOST_100PCENT CMU_CTRL_HFXOBOOST(3) - -#define CMU_CTRL_HFXOMODE_SHIFT (0) -#define CMU_CTRL_HFXOMODE_MASK (0x3 << CMU_CTRL_HFXOMODE_SHIFT) -#define CMU_CTRL_HFXOMODE(v) \ - (((v) << CMU_CTRL_HFXOMODE_SHIFT) & CMU_CTRL_HFXOMODE_MASK) -#define CMU_CTRL_HFXOMODE_XTAL CMU_CTRL_HFXOMODE(0) -#define CMU_CTRL_HFXOMODE_BUFEXTCLK CMU_CTRL_HFXOMODE(1) -#define CMU_CTRL_HFXOMODE_DIGEXTCLK CMU_CTRL_HFXOMODE(2) - -/* CMU_HFCORECLKDIV */ -#define CMU_HFCORECLKDIV_HFCORECLKLEDIV (1 << 8) - -#define CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT (0) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_MASK \ - (0xF << CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT) -#define CMU_HFCORECLKDIV_HFCORECLKDIV(v) \ - (((v) << CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT) & \ - CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK \ - CMU_HFCORECLKDIV_HFCORECLKDIV(0) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(1) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(2) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(3) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(4) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(5) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(6) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(7) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(8) -#define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 \ - CMU_HFCORECLKDIV_HFCORECLKDIV(9) - -#define CMU_HFCORECLKDIV_HFCORECLKDIV_NODIV \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV2 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV4 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV8 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV16 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV32 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV64 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV128 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV256 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 -#define CMU_HFCORECLKDIV_HFCORECLKDIV_DIV512 \ - CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 - -/* CMU_HFPERCLKDIV */ -#define CMU_HFPERCLKDIV_HFPERCLKEN (1 << 8) - -#define CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT (0) -#define CMU_HFPERCLKDIV_HFPERCLKDIV_MASK \ - (0xF << CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT) -#define CMU_HFPERCLKDIV_HFPERCLKDIV(v) \ - (((v) << CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT) & \ - CMU_HFPERCLKDIV_HFPERCLKDIV_MASK) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK CMU_HFPERCLKDIV_HFPERCLKDIV(0) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK2 CMU_HFPERCLKDIV_HFPERCLKDIV(1) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK4 CMU_HFPERCLKDIV_HFPERCLKDIV(2) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK8 CMU_HFPERCLKDIV_HFPERCLKDIV(3) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK16 CMU_HFPERCLKDIV_HFPERCLKDIV(4) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK32 CMU_HFPERCLKDIV_HFPERCLKDIV(5) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK64 CMU_HFPERCLKDIV_HFPERCLKDIV(6) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK128 CMU_HFPERCLKDIV_HFPERCLKDIV(7) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK256 CMU_HFPERCLKDIV_HFPERCLKDIV(8) -#define CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK512 CMU_HFPERCLKDIV_HFPERCLKDIV(9) - -/* CMU_HFPERCLKDIV_HFPERCLKHFCLK_HFCLK* to CMU_HFPERCLKDIV_HFPERCLKHFCLK_DIV* */ -#define CMU_HFPERCLKDIV_HFPERCLKDIV_NODIV \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV2 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV4 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV8 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV16 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV32 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV64 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV128 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV256 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 -#define CMU_HFPERCLKDIV_HFPERCLKDIV_DIV512 \ - CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 - -/* CMU_HFRCOCTRL */ -#define CMU_HFRCOCTRL_SUDELAY_SHIFT (12) -#define CMU_HFRCOCTRL_SUDELAY_MASK (0x1F << CMU_HFRCOCTRL_SUDELAY_SHIFT) -#define CMU_HFRCOCTRL_SUDELAY(v) \ - ((((v) << CMU_HFRCOCTRL_SUDELAY_SHIFT) & CMU_HFRCOCTRL_SUDELAY_MASK)) - -#define CMU_HFRCOCTRL_BAND_SHIFT (8) -#define CMU_HFRCOCTRL_BAND_MASK (0x7 << CMU_HFRCOCTRL_BAND_SHIFT) -#define CMU_HFRCOCTRL_BAND(v) \ - (((v) << CMU_HFRCOCTRL_BAND_SHIFT) & CMU_HFRCOCTRL_BAND_MASK) -#define CMU_HFRCOCTRL_BAND_1MHZ CMU_HFRCOCTRL_BAND(0) -#define CMU_HFRCOCTRL_BAND_7MHZ CMU_HFRCOCTRL_BAND(1) -#define CMU_HFRCOCTRL_BAND_11MHZ CMU_HFRCOCTRL_BAND(2) -#define CMU_HFRCOCTRL_BAND_14MHZ CMU_HFRCOCTRL_BAND(3) -#define CMU_HFRCOCTRL_BAND_21MHZ CMU_HFRCOCTRL_BAND(4) -#define CMU_HFRCOCTRL_BAND_28MHZ CMU_HFRCOCTRL_BAND(5) - -#define CMU_HFRCOCTRL_TUNING_SHIFT (0) -#define CMU_HFRCOCTRL_TUNING_MASK (0xFF << CMU_HFRCOCTRL_TUNING_SHIFT) -#define CMU_HFRCOCTRL_TUNING(v) \ - (((v) << CMU_HFRCOCTRL_TUNING_SHIFT) & CMU_HFRCOCTRL_TUNING_MASK) - -/* CMU_LFRCOCTRL */ -#define CMU_LFRCOCTRL_TUNING_SHIFT (0) -#define CMU_LFRCOCTRL_TUNING_MASK (0xFF << CMU_LFRCOCTRL_TUNING_SHIFT) -#define CMU_LFRCOCTRL_TUNING(v) \ - (((v) << CMU_LFRCOCTRL_TUNING_SHIFT) & CMU_LFRCOCTRL_TUNING_MASK) - -/* CMU_AUXHFRCOCTRL */ -#define CMU_AUXHFRCOCTRL_BAND_SHIFT (8) -#define CMU_AUXHFRCOCTRL_BAND_MASK (0x7 << CMU_AUXHFRCOCTRL_BAND_SHIFT) -#define CMU_AUXHFRCOCTRL_BAND(v) \ - (((v) << CMU_AUXHFRCOCTRL_BAND_SHIFT) & CMU_AUXHFRCOCTRL_BAND_MASK) -#define CMU_AUXHFRCOCTRL_BAND_14MHZ CMU_AUXHFRCOCTRL_BAND(0) -#define CMU_AUXHFRCOCTRL_BAND_11MHZ CMU_AUXHFRCOCTRL_BAND(1) -#define CMU_AUXHFRCOCTRL_BAND_7MHZ CMU_AUXHFRCOCTRL_BAND(2) -#define CMU_AUXHFRCOCTRL_BAND_1MHZ CMU_AUXHFRCOCTRL_BAND(3) -#define CMU_AUXHFRCOCTRL_BAND_28MHZ CMU_AUXHFRCOCTRL_BAND(6) -#define CMU_AUXHFRCOCTRL_BAND_21MHZ CMU_AUXHFRCOCTRL_BAND(7) - -#define CMU_AUXHFRCOCTRL_TUNING_SHIFT (0) -#define CMU_AUXHFRCOCTRL_TUNING_MASK (0xFF << CMU_AUXHFRCOCTRL_TUNING_SHIFT) -#define CMU_AUXHFRCOCTRL_TUNING(v) \ - (((v) << CMU_AUXHFRCOCTRL_TUNING_SHIFT) & CMU_AUXHFRCOCTRL_TUNING_MASK) - -/* CMU_CALCTRL */ -#define CMU_CALCTRL_CONT (1 << 6) - -#define CMU_CALCTRL_DOWNSEL_SHIFT (3) -#define CMU_CALCTRL_DOWNSEL_MASK (0x7 << CMU_CALCTRL_DOWNSEL_SHIFT) -#define CMU_CALCTRL_DOWNSEL(v) \ - (((v) << CMU_CALCTRL_DOWNSEL_SHIFT) & CMU_CALCTRL_DOWNSEL_MASK) -#define CMU_CALCTRL_DOWNSEL_HFCLK CMU_CALCTRL_DOWNSEL(0) -#define CMU_CALCTRL_DOWNSEL_HFXO CMU_CALCTRL_DOWNSEL(1) -#define CMU_CALCTRL_DOWNSEL_LFXO CMU_CALCTRL_DOWNSEL(2) -#define CMU_CALCTRL_DOWNSEL_HFRCO CMU_CALCTRL_DOWNSEL(3) -#define CMU_CALCTRL_DOWNSEL_LFRCO CMU_CALCTRL_DOWNSEL(4) -#define CMU_CALCTRL_DOWNSEL_AUXHFRCO CMU_CALCTRL_DOWNSEL(5) - -#define CMU_CALCTRL_UPSEL_SHIFT (3) -#define CMU_CALCTRL_UPSEL_MASK (0x7 << CMU_CALCTRL_UPSEL_SHIFT) -#define CMU_CALCTRL_UPSEL(v) \ - (((v) << CMU_CALCTRL_UPSEL_SHIFT) & CMU_CALCTRL_UPSEL_MASK) -#define CMU_CALCTRL_UPSEL_HFXO CMU_CALCTRL_UPSEL(0) -#define CMU_CALCTRL_UPSEL_LFXO CMU_CALCTRL_UPSEL(1) -#define CMU_CALCTRL_UPSEL_HFRCO CMU_CALCTRL_UPSEL(2) -#define CMU_CALCTRL_UPSEL_LFRCO CMU_CALCTRL_UPSEL(3) -#define CMU_CALCTRL_UPSEL_AUXHFRCO CMU_CALCTRL_UPSEL(4) - -/* CMU_CALCNT */ -#define CMU_CALCNT_CALCNT_SHIFT (0) -#define CMU_CALCNT_CALCNT_MASK (0xFFFFF << CMU_CALCNT_CALCNT_SHIFT) -#define CMU_CALCNT_CALCNT(v) \ - (((v) << CMU_CALCNT_CALCNT_SHIFT) & CMU_CALCNT_CALCNT_MASK) - -/* CMU_OSCENCMD */ -#define CMU_OSCENCMD_LFXODIS (1 << 9) -#define CMU_OSCENCMD_LFXOEN (1 << 8) -#define CMU_OSCENCMD_LFRCODIS (1 << 7) -#define CMU_OSCENCMD_LFRCOEN (1 << 6) -#define CMU_OSCENCMD_AUXHFRCODIS (1 << 5) -#define CMU_OSCENCMD_AUXHFRCOEN (1 << 4) -#define CMU_OSCENCMD_HFXODIS (1 << 3) -#define CMU_OSCENCMD_HFXOEN (1 << 2) -#define CMU_OSCENCMD_HFRCODIS (1 << 1) -#define CMU_OSCENCMD_HFRCOEN (1 << 0) - -/* CMU_CMD */ -#define CMU_CMD_USBCCLKSEL_SHIFT (5) -#define CMU_CMD_USBCCLKSEL_MASK (0x3 << CMU_CMD_USBCCLKSEL_SHIFT) -#define CMU_CMD_USBCCLKSEL(v) \ - (((v) << CMU_CMD_USBCCLKSEL_SHIFT) & CMU_CMD_USBCCLKSEL_MASK) -#define CMU_CMD_USBCCLKSEL_HFCLKNODIV CMU_CMD_USBCCLKSEL(1) -#define CMU_CMD_USBCCLKSEL_LFXO CMU_CMD_USBCCLKSEL(2) -#define CMU_CMD_USBCCLKSEL_LFRCO CMU_CMD_USBCCLKSEL(3) - -#define CMU_CMD_CALSTOP (1 << 4) -#define CMU_CMD_CALSTART (1 << 3) - -#define CMU_CMD_HFCLKSEL_SHIFT (0) -#define CMU_CMD_HFCLKSEL_MASK (0x7 << CMU_CMD_HFCLKSEL_SHIFT) -#define CMU_CMD_HFCLKSEL(v) \ - (((v) << CMU_CMD_HFCLKSEL_SHIFT) & CMU_CMD_HFCLKSEL_MASK) -#define CMU_CMD_HFCLKSEL_HFRCO CMU_CMD_HFCLKSEL(1) -#define CMU_CMD_HFCLKSEL_HFXO CMU_CMD_HFCLKSEL(2) -#define CMU_CMD_HFCLKSEL_LFRCO CMU_CMD_HFCLKSEL(3) -#define CMU_CMD_HFCLKSEL_LFXO CMU_CMD_HFCLKSEL(4) - -/* CMU_LFCLKSEL */ -#define CMU_LFCLKSEL_LFBE (1 << 20) -#define CMU_LFCLKSEL_LFAE (1 << 16) - -#define CMU_LFCLKSEL_LFB_SHIFT (2) -#define CMU_LFCLKSEL_LFB_MASK (0x3 << CMU_LFCLKSEL_LFB_MASK) -#define CMU_LFCLKSEL_LFB(v) \ - (((v) << CMU_LFCLKSEL_LFB_MASK) & CMU_LFCLKSEL_LFB_MASK) - -#define CMU_LFCLKSEL_LFA_SHIFT (0) -#define CMU_LFCLKSEL_LFA_MASK (0x3 << CMU_LFCLKSEL_LFA_MASK) -#define CMU_LFCLKSEL_LFA(v) \ - (((v) << CMU_LFCLKSEL_LFA_MASK) & CMU_LFCLKSEL_LFA_MASK) - -/* CMU_STATUS */ -#define CMU_STATUS_USBCLFRCOSEL (1 << 17) -#define CMU_STATUS_USBCLFXOSEL (1 << 16) -#define CMU_STATUS_USBCHFCLKSEL (1 << 15) -#define CMU_STATUS_CALBSY (1 << 14) -#define CMU_STATUS_LFXOSEL (1 << 13) -#define CMU_STATUS_LFRCOSEL (1 << 12) -#define CMU_STATUS_HFXOSEL (1 << 11) -#define CMU_STATUS_HFRCOSEL (1 << 10) -#define CMU_STATUS_LFXORDY (1 << 9) -#define CMU_STATUS_LFXOENS (1 << 8) -#define CMU_STATUS_LFRCORDY (1 << 7) -#define CMU_STATUS_LFRCOENS (1 << 6) -#define CMU_STATUS_AUXHFRCORDY (1 << 5) -#define CMU_STATUS_AUXHFRCOENS (1 << 4) -#define CMU_STATUS_HFXORDY (1 << 3) -#define CMU_STATUS_HFXOENS (1 << 2) -#define CMU_STATUS_HFRCORDY (1 << 1) -#define CMU_STATUS_HFRCOENS (1 << 0) - -/* CMU_IF */ -#define CMU_IF_USBCHFCLKSEL (1 << 7) -#define CMU_IF_CALOF (1 << 6) -#define CMU_IF_CALRDY (1 << 5) -#define CMU_IF_AUXHFRCORDY (1 << 4) -#define CMU_IF_LFXORDY (1 << 3) -#define CMU_IF_LFRCORDY (1 << 2) -#define CMU_IF_HFXORDY (1 << 1) -#define CMU_IF_HFRCORDY (1 << 0) - -/* CMU_IFS */ -#define CMU_IFS_USBCHFCLKSEL (1 << 7) -#define CMU_IFS_CALOF (1 << 6) -#define CMU_IFS_CALRDY (1 << 5) -#define CMU_IFS_AUXHFRCORDY (1 << 4) -#define CMU_IFS_LFXORDY (1 << 3) -#define CMU_IFS_LFRCORDY (1 << 2) -#define CMU_IFS_HFXORDY (1 << 1) -#define CMU_IFS_HFRCORDY (1 << 0) - -/* CMU_IFC */ -#define CMU_IFC_USBCHFCLKSEL (1 << 7) -#define CMU_IFC_CALOF (1 << 6) -#define CMU_IFC_CALRDY (1 << 5) -#define CMU_IFC_AUXHFRCORDY (1 << 4) -#define CMU_IFC_LFXORDY (1 << 3) -#define CMU_IFC_LFRCORDY (1 << 2) -#define CMU_IFC_HFXORDY (1 << 1) -#define CMU_IFC_HFRCORDY (1 << 0) - -/* CMU_IEN */ -#define CMU_IEN_USBCHFCLKSEL (1 << 7) -#define CMU_IEN_CALOF (1 << 6) -#define CMU_IEN_CALRDY (1 << 5) -#define CMU_IEN_AUXHFRCORDY (1 << 4) -#define CMU_IEN_LFXORDY (1 << 3) -#define CMU_IEN_LFRCORDY (1 << 2) -#define CMU_IEN_HFXORDY (1 << 1) -#define CMU_IEN_HFRCORDY (1 << 0) - -/* CMU_HFCORECLKEN0 */ -#define CMU_HFCORECLKEN0_EBI (1 << 5) -#define CMU_HFCORECLKEN0_LE (1 << 4) -#define CMU_HFCORECLKEN0_USB (1 << 3) -#define CMU_HFCORECLKEN0_USBC (1 << 2) -#define CMU_HFCORECLKEN0_AES (1 << 1) -#define CMU_HFCORECLKEN0_DMA (1 << 0) - -/* CMU_HFPERCLKEN0 */ -#define CMU_HFPERCLKEN0_DAC0 (1 << 17) -#define CMU_HFPERCLKEN0_ADC0 (1 << 16) -#define CMU_HFPERCLKEN0_PRS (1 << 15) -#define CMU_HFPERCLKEN0_VCMP (1 << 14) -#define CMU_HFPERCLKEN0_GPIO (1 << 13) -#define CMU_HFPERCLKEN0_I2C1 (1 << 12) -#define CMU_HFPERCLKEN0_I2C0 (1 << 11) -#define CMU_HFPERCLKEN0_ACMP1 (1 << 10) -#define CMU_HFPERCLKEN0_ACMP0 (1 << 9) -#define CMU_HFPERCLKEN0_TIMER3 (1 << 8) -#define CMU_HFPERCLKEN0_TIMER2 (1 << 7) -#define CMU_HFPERCLKEN0_TIMER1 (1 << 6) -#define CMU_HFPERCLKEN0_TIMER0 (1 << 5) -#define CMU_HFPERCLKEN0_UART1 (1 << 4) -#define CMU_HFPERCLKEN0_UART0 (1 << 3) -#define CMU_HFPERCLKEN0_USART2 (1 << 2) -#define CMU_HFPERCLKEN0_USART1 (1 << 1) -#define CMU_HFPERCLKEN0_USART0 (1 << 0) - -/* CMU_SYNCBUSY */ -#define CMU_SYNCBUSY_LFBPRESC0 (1 << 6) -#define CMU_SYNCBUSY_LFBCLKEN0 (1 << 4) -#define CMU_SYNCBUSY_LFAPRESC0 (1 << 2) -#define CMU_SYNCBUSY_LFACLKEN0 (1 << 0) - -/* CMU_FREEZE */ -#define CMU_FREEZE_REGFREEZE (1 << 0) - -/* CMU_LFACLKEN0 */ -#define CMU_LFACLKEN0_LCD (1 << 3) -#define CMU_LFACLKEN0_LETIMER0 (1 << 2) -#define CMU_LFACLKEN0_RTC (1 << 1) -#define CMU_LFACLKEN0_LESENSE (1 << 0) - -/* CMU_LFBCLKEN0 */ -#define CMU_LFBCLKEN0_LEUART1 (1 << 1) -#define CMU_LFBCLKEN0_LEUART0 (1 << 0) - -/* CMU_LFAPRESC0 */ -#define CMU_LFAPRESC0_LCD_SHIFT (12) -#define CMU_LFAPRESC0_LCD_MASK (0x3 << CMU_LFAPRESC0_LCD_SHIFT) -#define CMU_LFAPRESC0_LCD(v) \ - (((v) << CMU_LFAPRESC0_LCD_SHIFT) & CMU_LFAPRESC0_LCD_MASK) -#define CMU_LFAPRESC0_LCD_DIV16 CMU_LFAPRESC0_LCD(0) -#define CMU_LFAPRESC0_LCD_DIV32 CMU_LFAPRESC0_LCD(1) -#define CMU_LFAPRESC0_LCD_DIV64 CMU_LFAPRESC0_LCD(2) -#define CMU_LFAPRESC0_LCD_DIV128 CMU_LFAPRESC0_LCD(3) - -#define CMU_LFAPRESC0_LETIMER0_SHIFT (8) -#define CMU_LFAPRESC0_LETIMER0_MASK (0xF << CMU_LFAPRESC0_LETIMER0_SHIFT) -#define CMU_LFAPRESC0_LETIMER0(v) \ - (((v) << CMU_LFAPRESC0_LETIMER0_SHIFT) & CMU_LFAPRESC0_LETIMER0_MASK) -#define CMU_LFAPRESC0_LETIMER0_DIV1 CMU_LFAPRESC0_LETIMER0(0) -#define CMU_LFAPRESC0_LETIMER0_DIV2 CMU_LFAPRESC0_LETIMER0(1) -#define CMU_LFAPRESC0_LETIMER0_DIV4 CMU_LFAPRESC0_LETIMER0(2) -#define CMU_LFAPRESC0_LETIMER0_DIV8 CMU_LFAPRESC0_LETIMER0(3) -#define CMU_LFAPRESC0_LETIMER0_DIV16 CMU_LFAPRESC0_LETIMER0(4) -#define CMU_LFAPRESC0_LETIMER0_DIV32 CMU_LFAPRESC0_LETIMER0(5) -#define CMU_LFAPRESC0_LETIMER0_DIV64 CMU_LFAPRESC0_LETIMER0(6) -#define CMU_LFAPRESC0_LETIMER0_DIV128 CMU_LFAPRESC0_LETIMER0(7) -#define CMU_LFAPRESC0_LETIMER0_DIV256 CMU_LFAPRESC0_LETIMER0(8) -#define CMU_LFAPRESC0_LETIMER0_DIV512 CMU_LFAPRESC0_LETIMER0(9) -#define CMU_LFAPRESC0_LETIMER0_DIV1024 CMU_LFAPRESC0_LETIMER0(10) -#define CMU_LFAPRESC0_LETIMER0_DIV2048 CMU_LFAPRESC0_LETIMER0(11) -#define CMU_LFAPRESC0_LETIMER0_DIV4096 CMU_LFAPRESC0_LETIMER0(12) -#define CMU_LFAPRESC0_LETIMER0_DIV8192 CMU_LFAPRESC0_LETIMER0(13) -#define CMU_LFAPRESC0_LETIMER0_DIV16384 CMU_LFAPRESC0_LETIMER0(14) -#define CMU_LFAPRESC0_LETIMER0_DIV32768 CMU_LFAPRESC0_LETIMER0(15) -#define CMU_LFAPRESC0_LETIMER0_NODIV CMU_LFAPRESC0_LETIMER0_DIV1 - -#define CMU_LFAPRESC0_RTC_SHIFT (4) -#define CMU_LFAPRESC0_RTC_MASK (0xF << CMU_LFAPRESC0_RTC_SHIFT) -#define CMU_LFAPRESC0_RTC(v) \ - (((v) << CMU_LFAPRESC0_RTC_SHIFT) & CMU_LFAPRESC0_RTC_MASK) -#define CMU_LFAPRESC0_RTC_DIV1 CMU_LFAPRESC0_RTC(0) -#define CMU_LFAPRESC0_RTC_DIV2 CMU_LFAPRESC0_RTC(1) -#define CMU_LFAPRESC0_RTC_DIV4 CMU_LFAPRESC0_RTC(2) -#define CMU_LFAPRESC0_RTC_DIV8 CMU_LFAPRESC0_RTC(3) -#define CMU_LFAPRESC0_RTC_DIV16 CMU_LFAPRESC0_RTC(4) -#define CMU_LFAPRESC0_RTC_DIV32 CMU_LFAPRESC0_RTC(5) -#define CMU_LFAPRESC0_RTC_DIV64 CMU_LFAPRESC0_RTC(6) -#define CMU_LFAPRESC0_RTC_DIV128 CMU_LFAPRESC0_RTC(7) -#define CMU_LFAPRESC0_RTC_DIV256 CMU_LFAPRESC0_RTC(8) -#define CMU_LFAPRESC0_RTC_DIV512 CMU_LFAPRESC0_RTC(9) -#define CMU_LFAPRESC0_RTC_DIV1024 CMU_LFAPRESC0_RTC(10) -#define CMU_LFAPRESC0_RTC_DIV2048 CMU_LFAPRESC0_RTC(11) -#define CMU_LFAPRESC0_RTC_DIV4096 CMU_LFAPRESC0_RTC(12) -#define CMU_LFAPRESC0_RTC_DIV8192 CMU_LFAPRESC0_RTC(13) -#define CMU_LFAPRESC0_RTC_DIV16384 CMU_LFAPRESC0_RTC(14) -#define CMU_LFAPRESC0_RTC_DIV32768 CMU_LFAPRESC0_RTC(15) -#define CMU_LFAPRESC0_RTC_NODIV CMU_LFAPRESC0_RTC_DIV1 - -#define CMU_LFAPRESC0_LESENSE_SHIFT (12) -#define CMU_LFAPRESC0_LESENSE_MASK (0x3 << CMU_LFAPRESC0_LESENSE_SHIFT) -#define CMU_LFAPRESC0_LESENSE(v) \ - (((v) << CMU_LFAPRESC0_LESENSE_SHIFT) & CMU_LFAPRESC0_LESENSE_MASK) -#define CMU_LFAPRESC0_LESENSE_DIV1 CMU_LFAPRESC0_LESENSE(0) -#define CMU_LFAPRESC0_LESENSE_DIV2 CMU_LFAPRESC0_LESENSE(1) -#define CMU_LFAPRESC0_LESENSE_DIV4 CMU_LFAPRESC0_LESENSE(2) -#define CMU_LFAPRESC0_LESENSE_DIV8 CMU_LFAPRESC0_LESENSE(3) -#define CMU_LFAPRESC0_LESENSE_NODIV CMU_LFAPRESC0_LESENSE_DIV1 - -/* CMU_LFBPRESC0 */ -#define CMU_LFBPRESC0_LEUART1_SHIFT (4) -#define CMU_LFBPRESC0_LEUART1_MASK (0x3 << CMU_LFBPRESC0_LEUART1_SHIFT) -#define CMU_LFBPRESC0_LEUART1(v) \ - (((v) << CMU_LFBPRESC0_LEUART1_SHIFT) & CMU_LFBPRESC0_LEUART1_MASK) -#define CMU_LFBPRESC0_LEUART1_DIV1 CMU_LFBPRESC0_LEUART1(0) -#define CMU_LFBPRESC0_LEUART1_DIV2 CMU_LFBPRESC0_LEUART1(1) -#define CMU_LFBPRESC0_LEUART1_DIV4 CMU_LFBPRESC0_LEUART1(2) -#define CMU_LFBPRESC0_LEUART1_DIV8 CMU_LFBPRESC0_LEUART1(3) -#define CMU_LFBPRESC0_LEUART1_NODIV CMU_LFBPRESC0_LEUART1_DIV1 - -#define CMU_LFBPRESC0_LEUART0_SHIFT (0) -#define CMU_LFBPRESC0_LEUART0_MASK (0x3 << CMU_LFBPRESC0_LEUART0_SHIFT) -#define CMU_LFBPRESC0_LEUART0(v) \ - (((v) << CMU_LFBPRESC0_LEUART0_SHIFT) & CMU_LFBPRESC0_LEUART0_MASK) -#define CMU_LFBPRESC0_LEUART0_DIV1 CMU_LFBPRESC0_LEUART0(0) -#define CMU_LFBPRESC0_LEUART0_DIV2 CMU_LFBPRESC0_LEUART0(1) -#define CMU_LFBPRESC0_LEUART0_DIV4 CMU_LFBPRESC0_LEUART0(2) -#define CMU_LFBPRESC0_LEUART0_DIV8 CMU_LFBPRESC0_LEUART0(3) -#define CMU_LFBPRESC0_LEUART0_NODIV CMU_LFBPRESC0_LEUART0_DIV1 - -/* CMU_PCNTCTRL */ -#define CMU_PCNTCTRL_PCNT2CLKSE (1 << 5) -#define CMU_PCNTCTRL_PCNT2CLKEN (1 << 4) -#define CMU_PCNTCTRL_PCNT1CLKSEL (1 << 3) -#define CMU_PCNTCTRL_PCNT1CLKEN (1 << 2) -#define CMU_PCNTCTRL_PCNT0CLKSEL (1 << 1) -#define CMU_PCNTCTRL_PCNT0CLKEN (1 << 0) - -/* CMU_LCDCTRL */ -#define CMU_LCDCTRL_VBFDIV_SHIFT (4) -#define CMU_LCDCTRL_VBFDIV_MASK (0xF << CMU_LCDCTRL_VBFDIV_SHIFT) -#define CMU_LCDCTRL_VBFDIV(v) \ - (((v) << CMU_LCDCTRL_VBFDIV_SHIFT) & CMU_LCDCTRL_VBFDIV_MASK) -#define CMU_LCDCTRL_VBFDIV_DIV1 CMU_LCDCTRL_VBFDIV(0) -#define CMU_LCDCTRL_VBFDIV_DIV2 CMU_LCDCTRL_VBFDIV(1) -#define CMU_LCDCTRL_VBFDIV_DIV4 CMU_LCDCTRL_VBFDIV(2) -#define CMU_LCDCTRL_VBFDIV_DIV8 CMU_LCDCTRL_VBFDIV(3) -#define CMU_LCDCTRL_VBFDIV_DIV16 CMU_LCDCTRL_VBFDIV(4) -#define CMU_LCDCTRL_VBFDIV_DIV32 CMU_LCDCTRL_VBFDIV(5) -#define CMU_LCDCTRL_VBFDIV_DIV64 CMU_LCDCTRL_VBFDIV(6) -#define CMU_LCDCTRL_VBFDIV_DIV128 CMU_LCDCTRL_VBFDIV(7) -#define CMU_LCDCTRL_VBFDIV_NODIV CMU_LCDCTRL_VBFDIV_DIV1 - -#define CMU_LCDCTRL_VBOOSTEN (1 << 3) - -#define CMU_LCDCTRL_FDIV_SHIFT (0) -#define CMU_LCDCTRL_FDIV_MASK (0x3 << CMU_LCDCTRL_FDIV_SHIFT) -#define CMU_LCDCTRL_FDIV(v) \ - (((v) & CMU_LCDCTRL_FDIV_MASK) << CMU_LCDCTRL_FDIV_SHIFT) - -/* CMU_ROUTE */ -#define CMU_ROUTE_LOCATION_SHIFT (2) -#define CMU_ROUTE_LOCATION_MASK (0x7 << CMU_ROUTE_LOCATION_SHIFT) -#define CMU_ROUTE_LOCATION_LOCx(i) \ - (((i) << CMU_ROUTE_LOCATION_SHIFT) & CMU_ROUTE_LOCATION_MASK) -#define CMU_ROUTE_LOCATION_LOC0 CMU_ROUTE_LOCATION_LOCx(0) -#define CMU_ROUTE_LOCATION_LOC1 CMU_ROUTE_LOCATION_LOCx(1) -#define CMU_ROUTE_LOCATION_LOC2 CMU_ROUTE_LOCATION_LOCx(2) - -#define CMU_ROUTE_CLKOUT1PEN (1 << 1) -#define CMU_ROUTE_CLKOUT0PEN (1 << 0) - -/* CMU_LOCK */ -#define CMU_LOCK_LOCKKEY_SHIFT (0) -#define CMU_LOCK_LOCKKEY_MASK (0xFFFF << CMU_LOCK_LOCKKEY_SHIFT) -#define CMU_LOCK_LOCKKEY_UNLOCKED (0x0000 << CMU_LOCK_LOCKKEY_SHIFT) -#define CMU_LOCK_LOCKKEY_LOCKED (0x0001 << CMU_LOCK_LOCKKEY_SHIFT) -#define CMU_LOCK_LOCKKEY_LOCK (0x0000 << CMU_LOCK_LOCKKEY_SHIFT) -#define CMU_LOCK_LOCKKEY_UNLOCK (0x580E << CMU_LOCK_LOCKKEY_SHIFT) - -#define _REG_BIT(base, bit) (((base) << 5) + (bit)) - -enum cmu_periph_clken { - /* CMU_PCNTCTRL */ - CMU_PCNT2 = _REG_BIT(0x078, 4), - CMU_PCNT1 = _REG_BIT(0x078, 2), - CMU_PCNT0 = _REG_BIT(0x078, 0), - - /* CMU_LFBCLKEN0 */ - CMU_LEUART1 = _REG_BIT(0x060, 1), - CMU_LEUART0 = _REG_BIT(0x060, 0), - - /* CMU_LFACLKEN0 */ - CMU_LCD = _REG_BIT(0x058, 3), - CMU_LETIMER0 = _REG_BIT(0x058, 2), - CMU_RTC = _REG_BIT(0x058, 1), - CMU_LESENSE = _REG_BIT(0x058, 0), - - /* CMU_HFPERCLKEN0 */ - CMU_DAC0 = _REG_BIT(0x044, 17), - CMU_ADC0 = _REG_BIT(0x044, 16), - CMU_PRS = _REG_BIT(0x044, 15), - CMU_VCMP = _REG_BIT(0x044, 14), - CMU_GPIO = _REG_BIT(0x044, 13), - CMU_I2C1 = _REG_BIT(0x044, 12), - CMU_I2C0 = _REG_BIT(0x044, 11), - CMU_ACMP1 = _REG_BIT(0x044, 10), - CMU_ACMP0 = _REG_BIT(0x044, 9), - CMU_TIMER3 = _REG_BIT(0x044, 8), - CMU_TIMER2 = _REG_BIT(0x044, 7), - CMU_TIMER1 = _REG_BIT(0x044, 6), - CMU_TIMER0 = _REG_BIT(0x044, 5), - CMU_UART1 = _REG_BIT(0x044, 4), - CMU_UART0 = _REG_BIT(0x044, 3), - CMU_USART2 = _REG_BIT(0x044, 2), - CMU_USART1 = _REG_BIT(0x044, 1), - CMU_USART0 = _REG_BIT(0x044, 0), - - /* CMU_HFCORECLKEN0 */ - CMU_EBI = _REG_BIT(0x040, 5), - CMU_LE = _REG_BIT(0x040, 4), - CMU_USB = _REG_BIT(0x040, 3), - CMU_USBC = _REG_BIT(0x040, 2), - CMU_AES = _REG_BIT(0x040, 1), - CMU_DMA = _REG_BIT(0x040, 0) -}; - -enum cmu_osc { - HFRCO, /**< Internal, 1 - 28Mhz */ - LFRCO, /**< Internal, 32.768kHz */ - ULFRCO, /**< Internal, 1Khz */ - HFXO, /**< External, 4-48Mhz */ - LFXO, /**< External, 32.768kHz */ - AUXHFRCO, /**< Internal, 1-28Mhz */ -}; - -/* --- Function prototypes ------------------------------------------------- */ - -BEGIN_DECLS - -void cmu_enable_lock(void); -void cmu_disable_lock(void); -bool cmu_get_lock_flag(void); - -void cmu_periph_clock_enable(enum cmu_periph_clken periph); -void cmu_periph_clock_disable(enum cmu_periph_clken periph); - -/* TODO: CMU_CTRL, CMU_HFCORECLKDIV, CMU_HFPERCLKDIV, CMU_HFRCOCTRL, - * CMU_LFRCOCTRL, CMU_AUXHFRCOCTRL, CMU_CALCTRL, CMU_CALCNT */ - -void cmu_osc_on(enum cmu_osc osc); -void cmu_osc_off(enum cmu_osc osc); - -/* TODO: CMU_CMD, CMU_LFCLKSEL */ - -/* TODO: portions of CMU_STATUS */ -bool cmu_osc_ready_flag(enum cmu_osc osc); -void cmu_wait_for_osc_ready(enum cmu_osc osc); -void cmu_set_hfclk_source(enum cmu_osc osc); -void cmu_set_usbclk_source(enum cmu_osc osc); -enum cmu_osc cmu_get_hfclk_source(void); - -/* TODO: CMU_IF, CMU_IFS, CMU_IFC, CMU_IEN */ - -/* TODO: CMU_SYNCBUSY, CMU_FREEZE, CMU_LFACLKEN0 */ - -/* TODO: CMU_LFAPRESC0, CMU_LFBPRESC0, CMU_PCNTCTRL, CMU_LCDCTRL, CMU_ROUTE */ - -void cmu_clock_setup_in_hfxo_out_48mhz(void); - -END_DECLS +#include #endif diff --git a/include/libopencm3/efm32/lg/dac.h b/include/libopencm3/efm32/lg/dac.h index 1c7b37f3..5ad9dfe0 100644 --- a/include/libopencm3/efm32/lg/dac.h +++ b/include/libopencm3/efm32/lg/dac.h @@ -1,7 +1,7 @@ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2015 Kuldeep Singh Dhaka + * Copyright (C) 2016 Bob Miller * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -17,496 +17,9 @@ * along with this library. If not, see . */ -#ifndef LIBOPENCM3_EFM32_DAC_H -#define LIBOPENCM3_EFM32_DAC_H +#ifndef LIBOPENCM3_EFM32_LG_DAC_H +#define LIBOPENCM3_EFM32_LG_DAC_H -#include -#include -#include - -#define DAC_CTRL(base) MMIO32((base) + 0x00) -#define DAC_STATUS(base) MMIO32((base) + 0x04) -#define DAC_CHx_CTRL(base, x) MMIO32((base) + 0x08 + (0x04 * (x))) -#define DAC_CH0CTRL(base) DAC_CHx_CTRL(base, 0) -#define DAC_CH1CTRL(base) DAC_CHx_CTRL(base, 1) -#define DAC_IEN(base) MMIO32((base) + 0x010) -#define DAC_IF(base) MMIO32((base) + 0x014) -#define DAC_IFS(base) MMIO32((base) + 0x018) -#define DAC_IFC(base) MMIO32((base) + 0x01C) -#define DAC_CH0DATA(base) MMIO32((base) + 0x020) -#define DAC_CH1DATA(base) MMIO32((base) + 0x024) -#define DAC_COMBDATA(base) MMIO32((base) + 0x028) -#define DAC_CAL(base) MMIO32((base) + 0x02C) -#define DAC_BIASPROG(base) MMIO32((base) + 0x030) -#define DAC_OPACTRL(base) MMIO32((base) + 0x054) -#define DAC_OPAOFFSET(base) MMIO32((base) + 0x058) -#define DAC_OPA0MUX(base) MMIO32((base) + 0x05C) -#define DAC_OPA1MUX(base) MMIO32((base) + 0x060) -#define DAC_OPA2MUX(base) MMIO32((base) + 0x064) - -/* DAC_CTRL */ -#define DAC_CTRL_REFRSEL_SHIFT (20) -#define DAC_CTRL_REFRSEL_MASK (0x3 << DAC_CTRL_REFRSEL_SHIFT) -#define DAC_CTRL_REFRSEL(v) \ - (((v) << DAC_CTRL_REFRSEL_SHIFT) & DAC_CTRL_REFRSEL_MASK) -#define DAC_CTRL_REFRSEL_8CYCLES DAC_CTRL_REFRSEL(0) -#define DAC_CTRL_REFRSEL_16CYCLES DAC_CTRL_REFRSEL(1) -#define DAC_CTRL_REFRSEL_32CYCLES DAC_CTRL_REFRSEL(2) -#define DAC_CTRL_REFRSEL_64CYCLES DAC_CTRL_REFRSEL(3) - -#define DAC_CTRL_PRESC_SHIFT (16) -#define DAC_CTRL_PRESC_MASK (0x7 << DAC_CTRL_PRESC_SHIFT) -#define DAC_CTRL_PRESC(v) \ - (((v) << DAC_CTRL_PRESC_SHIFT) & DAC_CTRL_PRESC_MASK) -#define DAC_CTRL_PRESC_DIV1 DAC_CTRL_PRESC(0) -#define DAC_CTRL_PRESC_DIV2 DAC_CTRL_PRESC(1) -#define DAC_CTRL_PRESC_DIV4 DAC_CTRL_PRESC(2) -#define DAC_CTRL_PRESC_DIV8 DAC_CTRL_PRESC(3) -#define DAC_CTRL_PRESC_DIV16 DAC_CTRL_PRESC(4) -#define DAC_CTRL_PRESC_DIV32 DAC_CTRL_PRESC(5) -#define DAC_CTRL_PRESC_DIV64 DAC_CTRL_PRESC(6) -#define DAC_CTRL_PRESC_DIV128 DAC_CTRL_PRESC(7) -#define DAC_CTRL_PRESC_NODIV DAC_CTRL_PRESC_DIV1 - -#define DAC_CTRL_REFSEL_SHIFT (8) -#define DAC_CTRL_REFSEL_MASK (0x3 << DAC_CTRL_REFSEL_SHIFT) -#define DAC_CTRL_REFSEL(v) \ - (((v) << DAC_CTRL_REFSEL_SHIFT) & DAC_CTRL_REFSEL_MASK) -#define DAC_CTRL_REFSEL_1V25 DAC_CTRL_REFSEL(0) -#define DAC_CTRL_REFSEL_2V5 DAC_CTRL_REFSEL(1) -#define DAC_CTRL_REFSEL_VDD DAC_CTRL_REFSEL(2) - -#define DAC_CTRL_CH0PRESCRST (1 << 7) -#define DAC_CTRL_OUTENPRS (1 << 6) - -#define DAC_CTRL_OUTMODE_SHIFT (4) -#define DAC_CTRL_OUTMODE_MASK (0x3 << DAC_CTRL_OUTMODE_SHIFT) -#define DAC_CTRL_OUTMODE(v) \ - (((v) << DAC_CTRL_OUTMODE_SHIFT) & DAC_CTRL_OUTMODE_MASK) -#define DAC_CTRL_OUTMODE_DISABLE DAC_CTRL_OUTMODE(0) -#define DAC_CTRL_OUTMODE_PIN DAC_CTRL_OUTMODE(1) -#define DAC_CTRL_OUTMODE_ADC DAC_CTRL_OUTMODE(2) -#define DAC_CTRL_OUTMODE_PINADC DAC_CTRL_OUTMODE(3) - -#define DAC_CTRL_CONVMODE_SHIFT (2) -#define DAC_CTRL_CONVMODE_MASK (0x3 << DAC_CTRL_CONVMODE_SHIFT) -#define DAC_CTRL_CONVMODE(v) \ - (((v) << DAC_CTRL_CONVMODE_SHIFT) & DAC_CTRL_CONVMODE_MASK) -#define DAC_CTRL_CONVMODE_CONTINUOUS DAC_CTRL_CONVMODE(0) -#define DAC_CTRL_CONVMODE_SAMPLEHOLD DAC_CTRL_CONVMODE(1) -#define DAC_CTRL_CONVMODE_SAMPLEOFF DAC_CTRL_CONVMODE(2) - -#define DAC_CTRL_SINMODE (1 << 1) -#define DAC_CTRL_DIFF (1 << 0) - -/* DAC_STATUS */ -#define DAC_STATUS_CH1DV (1 << 1) -#define DAC_STATUS_CH0DV (1 << 0) - -/* DAC_CH_CTRL */ -#define DAC_CH_CTRL_PRSSEL_SHIFT (4) -#define DAC_CH_CTRL_PRSSEL_MASK (0xF << DAC_CH_CTRL_PRSSEL_SHIFT) -#define DAC_CH_CTRL_PRSSEL(v) \ - (((v) << DAC_CH_CTRL_PRSSEL_SHIFT) & DAC_CH_CTRL_PRSSEL_MASK) -#define DAC_CH_CTRL_PRSSEL_PRSCHx(x) DAC_CH_CTRL_PRSSEL(x) -#define DAC_CH_CTRL_PRSSEL_PRSCH0 DAC_CH_CTRL_PRSSEL_PRSCHx(0) -#define DAC_CH_CTRL_PRSSEL_PRSCH1 DAC_CH_CTRL_PRSSEL_PRSCHx(1) -#define DAC_CH_CTRL_PRSSEL_PRSCH2 DAC_CH_CTRL_PRSSEL_PRSCHx(2) -#define DAC_CH_CTRL_PRSSEL_PRSCH3 DAC_CH_CTRL_PRSSEL_PRSCHx(3) -#define DAC_CH_CTRL_PRSSEL_PRSCH4 DAC_CH_CTRL_PRSSEL_PRSCHx(4) -#define DAC_CH_CTRL_PRSSEL_PRSCH5 DAC_CH_CTRL_PRSSEL_PRSCHx(5) -#define DAC_CH_CTRL_PRSSEL_PRSCH6 DAC_CH_CTRL_PRSSEL_PRSCHx(6) -#define DAC_CH_CTRL_PRSSEL_PRSCH7 DAC_CH_CTRL_PRSSEL_PRSCHx(7) -#define DAC_CH_CTRL_PRSSEL_PRSCH8 DAC_CH_CTRL_PRSSEL_PRSCHx(8) -#define DAC_CH_CTRL_PRSSEL_PRSCH9 DAC_CH_CTRL_PRSSEL_PRSCHx(9) -#define DAC_CH_CTRL_PRSSEL_PRSCH10 DAC_CH_CTRL_PRSSEL_PRSCHx(10) -#define DAC_CH_CTRL_PRSSEL_PRSCH11 DAC_CH_CTRL_PRSSEL_PRSCHx(11) - -#define DAC_CH_CTRL_PRSEN (1 << 2) -#define DAC_CH_CTRL_REFREN (1 << 1) -#define DAC_CH_CTRL_EN (1 << 0) - -/* DAC_CH0CTRL */ -#define DAC_CH0CTRL_PRSSEL_SHIFT DAC_CH_CTRL_PRSSEL_SHIFT -#define DAC_CH0CTRL_PRSSEL_MASK DAC_CH_CTRL_PRSSEL_MASK -#define DAC_CH0CTRL_PRSSEL(v) DAC_CH_CTRL_PRSSEL(v) -#define DAC_CH0CTRL_PRSSEL_PRSCHx(x) DAC_CH_CTRL_PRSSEL_PRSCHx(x) -#define DAC_CH0CTRL_PRSSEL_PRSCH0 DAC_CH0CTRL_PRSSEL_PRSCH0 -#define DAC_CH0CTRL_PRSSEL_PRSCH1 DAC_CH_CTRL_PRSSEL_PRSCH1 -#define DAC_CH0CTRL_PRSSEL_PRSCH2 DAC_CH_CTRL_PRSSEL_PRSCH2 -#define DAC_CH0CTRL_PRSSEL_PRSCH3 DAC_CH_CTRL_PRSSEL_PRSCH3 -#define DAC_CH0CTRL_PRSSEL_PRSCH4 DAC_CH_CTRL_PRSSEL_PRSCH4 -#define DAC_CH0CTRL_PRSSEL_PRSCH5 DAC_CH_CTRL_PRSSEL_PRSCH5 -#define DAC_CH0CTRL_PRSSEL_PRSCH6 DAC_CH_CTRL_PRSSEL_PRSCH6 -#define DAC_CH0CTRL_PRSSEL_PRSCH7 DAC_CH_CTRL_PRSSEL_PRSCH7 -#define DAC_CH0CTRL_PRSSEL_PRSCH8 DAC_CH_CTRL_PRSSEL_PRSCH8 -#define DAC_CH0CTRL_PRSSEL_PRSCH9 DAC_CH_CTRL_PRSSEL_PRSCH9 -#define DAC_CH0CTRL_PRSSEL_PRSCH10 DAC_CH_CTRL_PRSSEL_PRSCH10 -#define DAC_CH0CTRL_PRSSEL_PRSCH11 DAC_CH_CTRL_PRSSEL_PRSCH11 - -#define DAC_CH0CTRL_PRSEN DAC_CH_CTRL_PRSEN -#define DAC_CH0CTRL_REFREN DAC_CH_CTRL_REFREN -#define DAC_CH0CTRL_EN DAC_CH_CTRL_EN - -/* DAC_CH1CTRL */ -#define DAC_CH1CTRL_PRSSEL_SHIFT DAC_CH_CTRL_PRSSEL_SHIFT -#define DAC_CH1CTRL_PRSSEL_MASK DAC_CH_CTRL_PRSSEL_MASK -#define DAC_CH1CTRL_PRSSEL(v) DAC_CH_CTRL_PRSSEL(v) -#define DAC_CH1CTRL_PRSSEL_PRSCHx(x) DAC_CH_CTRL_PRSSEL_PRSCHx(x) -#define DAC_CH1CTRL_PRSSEL_PRSCH0 DAC_CH_CTRL_PRSSEL_PRSCH0 -#define DAC_CH1CTRL_PRSSEL_PRSCH1 DAC_CH_CTRL_PRSSEL_PRSCH1 -#define DAC_CH1CTRL_PRSSEL_PRSCH2 DAC_CH_CTRL_PRSSEL_PRSCH2 -#define DAC_CH1CTRL_PRSSEL_PRSCH3 DAC_CH_CTRL_PRSSEL_PRSCH3 -#define DAC_CH1CTRL_PRSSEL_PRSCH4 DAC_CH_CTRL_PRSSEL_PRSCH4 -#define DAC_CH1CTRL_PRSSEL_PRSCH5 DAC_CH_CTRL_PRSSEL_PRSCH5 -#define DAC_CH1CTRL_PRSSEL_PRSCH6 DAC_CH_CTRL_PRSSEL_PRSCH6 -#define DAC_CH1CTRL_PRSSEL_PRSCH7 DAC_CH_CTRL_PRSSEL_PRSCH7 -#define DAC_CH1CTRL_PRSSEL_PRSCH8 DAC_CH_CTRL_PRSSEL_PRSCH8 -#define DAC_CH1CTRL_PRSSEL_PRSCH9 DAC_CH_CTRL_PRSSEL_PRSCH9 -#define DAC_CH1CTRL_PRSSEL_PRSCH10 DAC_CH_CTRL_PRSSEL_PRSCH10 -#define DAC_CH1CTRL_PRSSEL_PRSCH11 DAC_CH_CTRL_PRSSEL_PRSCH11 - -#define DAC_CH1CTRL_PRSEN DAC_CH_CTRL_PRSEN -#define DAC_CH1CTRL_REFREN DAC_CH_CTRL_REFREN -#define DAC_CH1CTRL_EN DAC_CH_CTRL_EN - -/* DAC_IEN */ -#define DAC_IEN_CH1UF (5 << 0) -#define DAC_IEN_CH0UF (4 << 0) -#define DAC_IEN_CH1 (1 << 1) -#define DAC_IEN_CH0 (1 << 0) - -/* DAC_IF */ -#define DAC_IF_CH1UF (5 << 0) -#define DAC_IF_CH0UF (4 << 0) -#define DAC_IF_CH1 (1 << 1) -#define DAC_IF_CH0 (1 << 0) - -/* DAC_IFS */ -#define DAC_IFS_CH1UF (5 << 0) -#define DAC_IFS_CH0UF (4 << 0) -#define DAC_IFS_CH1 (1 << 1) -#define DAC_IFS_CH0 (1 << 0) - -/* DAC_IFC */ -#define DAC_IFC_CH1UF (5 << 0) -#define DAC_IFC_CH0UF (4 << 0) -#define DAC_IFC_CH1 (1 << 1) -#define DAC_IFC_CH0 (1 << 0) - -/* DAC_CAL */ -#define DAC_CAL_GAIN_SHIFT (16) -#define DAC_CAL_GAIN_MASK (0x7F << DAC_CAL_GAIN_SHIFT) -#define DAC_CAL_GAIN(v) \ - (((v) << DAC_CAL_GAIN_SHIFT) & DAC_CAL_GAIN_MASK) - -#define DAC_CAL_CH1OFFSET_SHIFT (8) -#define DAC_CAL_CH1OFFSET_MASK (0x3F << DAC_CAL_CH1OFFSET_SHIFT) -#define DAC_CAL_CH1OFFSET(v) \ - (((v) << DAC_CAL_CH1OFFSET_SHIFT) & DAC_CAL_CH1OFFSET_MASK) - -#define DAC_CAL_CH0OFFSET_SHIFT (0) -#define DAC_CAL_CH0OFFSET_MASK (0x3F << DAC_CAL_CH0OFFSET_SHIFT) -#define DAC_CAL_CH0OFFSET(v) \ - (((v) << DAC_CAL_CH0OFFSET_SHIFT) & DAC_CAL_CH0OFFSET_MASK) - -/* DAC_BIASPROG */ -#define DAC_BIASPROG_OPA2HALFBIAS (1 << 14) - -#define DAC_BIASPROG_OPA2BIASPROG_SHIFT (8) -#define DAC_BIASPROG_OPA2BIASPROG_MASK (0xF << DAC_BIASPROG_OPA2BIASPROG_SHIFT) -#define DAC_BIASPROG_OPA2BIASPROG(v) \ - ((((v) << DAC_BIASPROG_OPA2BIASPROG_SHIFT)) & \ - DAC_BIASPROG_OPA2BIASPROG_MASK) - -#define DAC_BIASPROG_HALFBIAS (1 << 6) - -#define DAC_BIASPROG_BIASPROG_SHIFT (0) -#define DAC_BIASPROG_BIASPROG_MASK (0xF << DAC_BIASPROG_BIASPROG_SHIFT) -#define DAC_BIASPROG_BIASPROG(v) \ - ((((v) << DAC_BIASPROG_BIASPROG_SHIFT)) & DAC_BIASPROG_BIASPROG_MASK) - -/* DAC_OPACTRL */ -#define DAC_OPACTRL_OPA2SHORT (1 << 24) -#define DAC_OPACTRL_OPA1SHORT (1 << 23) -#define DAC_OPACTRL_OPA0SHORT (1 << 22) - -#define DAC_OPACTRL_OPA2LPFDIS_SHIFT (16) -#define DAC_OPACTRL_OPA2LPFDIS_MASK (0x3 << DAC_OPACTRL_OPA2LPFDIS_SHIFT) -#define DAC_OPACTRL_OPA2LPFDIS(v) \ - (((v) << DAC_OPACTRL_OPA2LPFDIS_SHIFT) & DAC_OPACTRL_OPA2LPFDIS_MASK) -#define DAC_OPACTRL_OPA2LPFDIS_PLPFDIS DAC_OPACTRL_OPA2LPFDIS(0b01) -#define DAC_OPACTRL_OPA2LPFDIS_NLPFDIS DAC_OPACTRL_OPA2LPFDIS(0b10) - -#define DAC_OPACTRL_OPA1LPFDIS_SHIFT (14) -#define DAC_OPACTRL_OPA1LPFDIS_MASK (0x3 << DAC_OPACTRL_OPA1LPFDIS_SHIFT) -#define DAC_OPACTRL_OPA1LPFDIS(v) \ - (((v) << DAC_OPACTRL_OPA1LPFDIS_SHIFT) & DAC_OPACTRL_OPA1LPFDIS_MASK) -#define DAC_OPACTRL_OPA1LPFDIS_PLPFDIS DAC_OPACTRL_OPA1LPFDIS(0b01) -#define DAC_OPACTRL_OPA1LPFDIS_NLPFDIS DAC_OPACTRL_OPA1LPFDIS(0b10) - -#define DAC_OPACTRL_OPA0LPFDIS_SHIFT (14) -#define DAC_OPACTRL_OPA0LPFDIS_MASK (0x3 << DAC_OPACTRL_OPA0LPFDIS_SHIFT) -#define DAC_OPACTRL_OPA0LPFDIS(v) \ - (((v) << DAC_OPACTRL_OPA0LPFDIS_SHIFT) & DAC_OPACTRL_OPA0LPFDIS_MASK) -#define DAC_OPACTRL_OPA0LPFDIS_PLPFDIS DAC_OPACTRL_OPA0LPFDIS(0b01) -#define DAC_OPACTRL_OPA0LPFDIS_NLPFDIS DAC_OPACTRL_OPA0LPFDIS(0b10) - -#define DAC_OPACTRL_OPA2HCMDIS (1 << 8) -#define DAC_OPACTRL_OPA1HCMDIS (1 << 7) -#define DAC_OPACTRL_OPA0HCMDIS (1 << 6) - -#define DAC_OPACTRL_OPA2EN (1 << 2) -#define DAC_OPACTRL_OPA1EN (1 << 1) -#define DAC_OPACTRL_OPA0EN (1 << 0) - -/* DAC_OPA0MUX */ -#define DAC_OPA0MUX_RESSEL_SHIFT (28) -#define DAC_OPA0MUX_RESSEL_MASK (0x7 << DAC_OPA0MUX_RESSEL_SHIFT) -#define DAC_OPA0MUX_RESSEL_RESSEL(v) \ - ((((v) << DAC_OPA0MUX_RESSEL_SHIFT)) & DAC_OPA0MUX_RESSEL_MASK) -#define DAC_OPA0MUX_RESSEL_RESSEL_RESx(x) DAC_OPA0MUX_RESSEL_RESSEL(x) -#define DAC_OPA0MUX_RESSEL_RESSEL_RES0 DAC_OPA0MUX_RESSEL_RESSEL_RESx(0) -#define DAC_OPA0MUX_RESSEL_RESSEL_RES1 DAC_OPA0MUX_RESSEL_RESSEL_RESx(1) -#define DAC_OPA0MUX_RESSEL_RESSEL_RES2 DAC_OPA0MUX_RESSEL_RESSEL_RESx(2) -#define DAC_OPA0MUX_RESSEL_RESSEL_RES3 DAC_OPA0MUX_RESSEL_RESSEL_RESx(3) -#define DAC_OPA0MUX_RESSEL_RESSEL_RES4 DAC_OPA0MUX_RESSEL_RESSEL_RESx(4) -#define DAC_OPA0MUX_RESSEL_RESSEL_RES5 DAC_OPA0MUX_RESSEL_RESSEL_RESx(5) -#define DAC_OPA0MUX_RESSEL_RESSEL_RES6 DAC_OPA0MUX_RESSEL_RESSEL_RESx(6) -#define DAC_OPA0MUX_RESSEL_RESSEL_RES7 DAC_OPA0MUX_RESSEL_RESSEL_RESx(7) - -#define DAC_OPA0MUX_NEXTOUT (1 << 26) - -#define DAC_OPA0MUX_OUTMODE_SHIFT (22) -#define DAC_OPA0MUX_OUTMODE_MASK (0x3 << DAC_OPA0MUX_OUTMODE_SHIFT) -#define DAC_OPA0MUX_OUTMODE(v) \ - (((v) << DAC_OPA0MUX_OUTMODE_SHIFT) & DAC_OPA0MUX_OUTMODE_MASK) -#define DAC_OPA0MUX_OUTMODE_DISABLE DAC_OPA0MUX_OUTMODE(0) -#define DAC_OPA0MUX_OUTMODE_MAIN DAC_OPA0MUX_OUTMODE(1) -#define DAC_OPA0MUX_OUTMODE_ALT DAC_OPA0MUX_OUTMODE(2) -#define DAC_OPA0MUX_OUTMODE_ALL DAC_OPA0MUX_OUTMODE(3) - -#define DAC_OPA0MUX_OUTPEN_SHIFT (18) -#define DAC_OPA0MUX_OUTPEN_MASK (0x1F << DAC_OPA0MUX_OUTPEN_SHIFT) -#define DAC_OPA0MUX_OUTPEN(v) \ - (((v) << DAC_OPA0MUX_OUTPEN_SHIFT) & DAC_OPA0MUX_OUTPEN_MASK) -#define DAC_OPA0MUX_OUTPEN_OUT0 DAC_OPA0MUX_OUTPEN(1 << 0) -#define DAC_OPA0MUX_OUTPEN_OUT1 DAC_OPA0MUX_OUTPEN(1 << 1) -#define DAC_OPA0MUX_OUTPEN_OUT2 DAC_OPA0MUX_OUTPEN(1 << 2) -#define DAC_OPA0MUX_OUTPEN_OUT3 DAC_OPA0MUX_OUTPEN(1 << 3) -#define DAC_OPA0MUX_OUTPEN_OUT4 DAC_OPA0MUX_OUTPEN(1 << 4) - -#define DAC_OPA0MUX_NPEN (1 << 13) -#define DAC_OPA0MUX_PPEN (1 << 12) - -#define DAC_OPA0MUX_RESINMUX_SHIFT (8) -#define DAC_OPA0MUX_RESINMUX_MASK (0x7 << DAC_OPA0MUX_RESINMUX_SHIFT) -#define DAC_OPA0MUX_RESINMUX(v) \ - (((v) << DAC_OPA0MUX_RESINMUX_SHIFT) & DAC_OPA0MUX_RESINMUX_MASK) -#define DAC_OPA0MUX_RESINMUX_DISABLE DAC_OPA0MUX_RESINMUX(0) -#define DAC_OPA0MUX_RESINMUX_OPA0INP DAC_OPA0MUX_RESINMUX(1) -#define DAC_OPA0MUX_RESINMUX_NEGPAD DAC_OPA0MUX_RESINMUX(2) -#define DAC_OPA0MUX_RESINMUX_POSPAD DAC_OPA0MUX_RESINMUX(3) -#define DAC_OPA0MUX_RESINMUX_VSS DAC_OPA0MUX_RESINMUX(4) - -#define DAC_OPA0MUX_NEGSEL_SHIFT (4) -#define DAC_OPA0MUX_NEGSEL_MASK (0x3 << DAC_OPA0MUX_NEGSEL_SHIFT) -#define DAC_OPA0MUX_NEGSEL(v) \ - (((v) << DAC_OPA0MUX_NEGSEL_SHIFT) & DAC_OPA0MUX_NEGSEL_MASK) -#define DAC_OPA0MUX_NEGSEL_DISABLE DAC_OPA0MUX_NEGSEL(0) -#define DAC_OPA0MUX_NEGSEL_UG DAC_OPA0MUX_NEGSEL(1) -#define DAC_OPA0MUX_NEGSEL_OPATAP DAC_OPA0MUX_NEGSEL(2) -#define DAC_OPA0MUX_NEGSEL_NEGPAD DAC_OPA0MUX_NEGSEL(3) - -#define DAC_OPA0MUX_POSSEL_SHIFT (0) -#define DAC_OPA0MUX_POSSEL_MASK (0x7 << DAC_OPA0MUX_POSSEL_SHIFT) -#define DAC_OPA0MUX_POSSEL(v) \ - (((v) << DAC_OPA0MUX_POSSEL_SHIFT) & DAC_OPA0MUX_POSSEL_MASK) -#define DAC_OPA0MUX_POSSEL_DISABLE DAC_OPA0MUX_POSSEL(0) -#define DAC_OPA0MUX_POSSEL_DAC DAC_OPA0MUX_POSSEL(1) -#define DAC_OPA0MUX_POSSEL_POSPAD DAC_OPA0MUX_POSSEL(2) -#define DAC_OPA0MUX_POSSEL_OPA0INP DAC_OPA0MUX_POSSEL(3) -#define DAC_OPA0MUX_POSSEL_OPATAP DAC_OPA0MUX_POSSEL(4) - -/* DAC_OPA1MUX */ -#define DAC_OPA1MUX_RESSEL_SHIFT (28) -#define DAC_OPA1MUX_RESSEL_MASK (0x7 << DAC_OPA1MUX_RESSEL_SHIFT) -#define DAC_OPA1MUX_RESSEL_RESSEL(v) \ - ((((v) << DAC_OPA1MUX_RESSEL_SHIFT)) & DAC_OPA1MUX_RESSEL_MASK) -#define DAC_OPA1MUX_RESSEL_RESSEL_RESx(x) DAC_OPA1MUX_RESSEL_RESSEL(x) -#define DAC_OPA1MUX_RESSEL_RESSEL_RES0 DAC_OPA1MUX_RESSEL_RESSEL_RESx(0) -#define DAC_OPA1MUX_RESSEL_RESSEL_RES1 DAC_OPA1MUX_RESSEL_RESSEL_RESx(1) -#define DAC_OPA1MUX_RESSEL_RESSEL_RES2 DAC_OPA1MUX_RESSEL_RESSEL_RESx(2) -#define DAC_OPA1MUX_RESSEL_RESSEL_RES3 DAC_OPA1MUX_RESSEL_RESSEL_RESx(3) -#define DAC_OPA1MUX_RESSEL_RESSEL_RES4 DAC_OPA1MUX_RESSEL_RESSEL_RESx(4) -#define DAC_OPA1MUX_RESSEL_RESSEL_RES5 DAC_OPA1MUX_RESSEL_RESSEL_RESx(5) -#define DAC_OPA1MUX_RESSEL_RESSEL_RES6 DAC_OPA1MUX_RESSEL_RESSEL_RESx(6) -#define DAC_OPA1MUX_RESSEL_RESSEL_RES7 DAC_OPA1MUX_RESSEL_RESSEL_RESx(7) - -#define DAC_OPA1MUX_NEXTOUT (1 << 26) - -#define DAC_OPA1MUX_OUTMODE_SHIFT (22) -#define DAC_OPA1MUX_OUTMODE_MASK (0x3 << DAC_OPA1MUX_OUTMODE_SHIFT) -#define DAC_OPA1MUX_OUTMODE(v) \ - (((v) << DAC_OPA1MUX_OUTMODE_SHIFT) & DAC_OPA1MUX_OUTMODE_MASK) -#define DAC_OPA1MUX_OUTMODE_DISABLE DAC_OPA1MUX_OUTMODE(0) -#define DAC_OPA1MUX_OUTMODE_MAIN DAC_OPA1MUX_OUTMODE(1) -#define DAC_OPA1MUX_OUTMODE_ALT DAC_OPA1MUX_OUTMODE(2) -#define DAC_OPA1MUX_OUTMODE_ALL DAC_OPA1MUX_OUTMODE(3) - -#define DAC_OPA1MUX_OUTPEN_SHIFT (18) -#define DAC_OPA1MUX_OUTPEN_MASK (0x1F << DAC_OPA1MUX_OUTPEN_SHIFT) -#define DAC_OPA1MUX_OUTPEN(v) \ - (((v) << DAC_OPA1MUX_OUTPEN_SHIFT) & DAC_OPA1MUX_OUTPEN_MASK) -#define DAC_OPA1MUX_OUTPEN_OUT0 DAC_OPA1MUX_OUTPEN(1 << 0) -#define DAC_OPA1MUX_OUTPEN_OUT1 DAC_OPA1MUX_OUTPEN(1 << 1) -#define DAC_OPA1MUX_OUTPEN_OUT2 DAC_OPA1MUX_OUTPEN(1 << 2) -#define DAC_OPA1MUX_OUTPEN_OUT3 DAC_OPA1MUX_OUTPEN(1 << 3) -#define DAC_OPA1MUX_OUTPEN_OUT4 DAC_OPA1MUX_OUTPEN(1 << 4) - -#define DAC_OPA1MUX_NPEN (1 << 13) -#define DAC_OPA1MUX_PPEN (1 << 12) - -#define DAC_OPA1MUX_RESINMUX_SHIFT (8) -#define DAC_OPA1MUX_RESINMUX_MASK (0x7 << DAC_OPA1MUX_RESINMUX_SHIFT) -#define DAC_OPA1MUX_RESINMUX(v) \ - (((v) << DAC_OPA1MUX_RESINMUX_SHIFT) & DAC_OPA1MUX_RESINMUX_MASK) -#define DAC_OPA1MUX_RESINMUX_DISABLE DAC_OPA1MUX_RESINMUX(0) -#define DAC_OPA1MUX_RESINMUX_OPA0INP DAC_OPA1MUX_RESINMUX(1) -#define DAC_OPA1MUX_RESINMUX_NEGPAD DAC_OPA1MUX_RESINMUX(2) -#define DAC_OPA1MUX_RESINMUX_POSPAD DAC_OPA1MUX_RESINMUX(3) -#define DAC_OPA1MUX_RESINMUX_VSS DAC_OPA1MUX_RESINMUX(4) - -#define DAC_OPA1MUX_NEGSEL_SHIFT (4) -#define DAC_OPA1MUX_NEGSEL_MASK (0x3 << DAC_OPA1MUX_NEGSEL_SHIFT) -#define DAC_OPA1MUX_NEGSEL(v) \ - (((v) << DAC_OPA1MUX_NEGSEL_SHIFT) & DAC_OPA1MUX_NEGSEL_MASK) -#define DAC_OPA1MUX_NEGSEL_DISABLE DAC_OPA1MUX_NEGSEL(0) -#define DAC_OPA1MUX_NEGSEL_UG DAC_OPA1MUX_NEGSEL(1) -#define DAC_OPA1MUX_NEGSEL_OPATAP DAC_OPA1MUX_NEGSEL(2) -#define DAC_OPA1MUX_NEGSEL_NEGPAD DAC_OPA1MUX_NEGSEL(3) - -#define DAC_OPA1MUX_POSSEL_SHIFT (0) -#define DAC_OPA1MUX_POSSEL_MASK (0x7 << DAC_OPA1MUX_POSSEL_SHIFT) -#define DAC_OPA1MUX_POSSEL(v) \ - (((v) << DAC_OPA1MUX_POSSEL_SHIFT) & DAC_OPA1MUX_POSSEL_MASK) -#define DAC_OPA1MUX_POSSEL_DISABLE DAC_OPA1MUX_POSSEL(0) -#define DAC_OPA1MUX_POSSEL_DAC DAC_OPA1MUX_POSSEL(1) -#define DAC_OPA1MUX_POSSEL_POSPAD DAC_OPA1MUX_POSSEL(2) -#define DAC_OPA1MUX_POSSEL_OPA0INP DAC_OPA1MUX_POSSEL(3) -#define DAC_OPA1MUX_POSSEL_OPATAP DAC_OPA1MUX_POSSEL(4) - - -/* DAC_OPA2MUX */ -#define DAC_OPA2MUX_RESSEL_SHIFT (28) -#define DAC_OPA2MUX_RESSEL_MASK (0x7 << DAC_OPA2MUX_RESSEL_SHIFT) -#define DAC_OPA2MUX_RESSEL_RESSEL(v) \ - ((((v) << DAC_OPA2MUX_RESSEL_SHIFT)) & DAC_OPA2MUX_RESSEL_MASK) -#define DAC_OPA2MUX_RESSEL_RESSEL_RESx(x) DAC_OPA2MUX_RESSEL_RESSEL(x) -#define DAC_OPA2MUX_RESSEL_RESSEL_RES0 DAC_OPA2MUX_RESSEL_RESSEL_RESx(0) -#define DAC_OPA2MUX_RESSEL_RESSEL_RES1 DAC_OPA2MUX_RESSEL_RESSEL_RESx(1) -#define DAC_OPA2MUX_RESSEL_RESSEL_RES2 DAC_OPA2MUX_RESSEL_RESSEL_RESx(2) -#define DAC_OPA2MUX_RESSEL_RESSEL_RES3 DAC_OPA2MUX_RESSEL_RESSEL_RESx(3) -#define DAC_OPA2MUX_RESSEL_RESSEL_RES4 DAC_OPA2MUX_RESSEL_RESSEL_RESx(4) -#define DAC_OPA2MUX_RESSEL_RESSEL_RES5 DAC_OPA2MUX_RESSEL_RESSEL_RESx(5) -#define DAC_OPA2MUX_RESSEL_RESSEL_RES6 DAC_OPA2MUX_RESSEL_RESSEL_RESx(6) -#define DAC_OPA2MUX_RESSEL_RESSEL_RES7 DAC_OPA2MUX_RESSEL_RESSEL_RESx(7) - -#define DAC_OPA2MUX_NEXTOUT (1 << 26) - -#define DAC_OPA2MUX_OUTMODE (1 << 22) - -#define DAC_OPA2MUX_OUTPEN_SHIFT (14) -#define DAC_OPA2MUX_OUTPEN_MASK (0x3 << DAC_OPA2MUX_OUTPEN_SHIFT) -#define DAC_OPA2MUX_OUTPEN(v) \ - (((v) << DAC_OPA2MUX_OUTPEN_SHIFT) & DAC_OPA2MUX_OUTPEN_MASK) -#define DAC_OPA2MUX_OUTPEN_OUT0 DAC_OPA2MUX_OUTPEN(0) -#define DAC_OPA2MUX_OUTPEN_OUT1 DAC_OPA2MUX_OUTPEN(1) - -#define DAC_OPA2MUX_NPEN (1 << 13) -#define DAC_OPA2MUX_PPEN (1 << 12) - -#define DAC_OPA2MUX_RESINMUX_SHIFT (8) -#define DAC_OPA2MUX_RESINMUX_MASK (0x7 << DAC_OPA2MUX_RESINMUX_SHIFT) -#define DAC_OPA2MUX_RESINMUX(v) \ - (((v) << DAC_OPA2MUX_RESINMUX_SHIFT) & DAC_OPA2MUX_RESINMUX_MASK) -#define DAC_OPA2MUX_RESINMUX_DISABLE DAC_OPA2MUX_RESINMUX(0) -#define DAC_OPA2MUX_RESINMUX_OPA1INP DAC_OPA2MUX_RESINMUX(1) -#define DAC_OPA2MUX_RESINMUX_NEGPAD DAC_OPA2MUX_RESINMUX(2) -#define DAC_OPA2MUX_RESINMUX_POSPAD DAC_OPA2MUX_RESINMUX(3) -#define DAC_OPA2MUX_RESINMUX_VSS DAC_OPA2MUX_RESINMUX(4) - -#define DAC_OPA2MUX_NEGSEL_SHIFT (4) -#define DAC_OPA2MUX_NEGSEL_MASK (0x3 << DAC_OPA2MUX_NEGSEL_SHIFT) -#define DAC_OPA2MUX_NEGSEL(v) \ - (((v) << DAC_OPA2MUX_NEGSEL_SHIFT) & DAC_OPA2MUX_NEGSEL_MASK) -#define DAC_OPA2MUX_NEGSEL_DISABLE DAC_OPA2MUX_NEGSEL(0) -#define DAC_OPA2MUX_NEGSEL_UG DAC_OPA2MUX_NEGSEL(1) -#define DAC_OPA2MUX_NEGSEL_OPATAP DAC_OPA2MUX_NEGSEL(2) -#define DAC_OPA2MUX_NEGSEL_NEGPAD DAC_OPA2MUX_NEGSEL(3) - -#define DAC_OPA2MUX_POSSEL_SHIFT (0) -#define DAC_OPA2MUX_POSSEL_MASK (0x7 << DAC_OPA2MUX_POSSEL_SHIFT) -#define DAC_OPA2MUX_POSSEL(v) \ - (((v) << DAC_OPA2MUX_POSSEL_SHIFT) & DAC_OPA2MUX_POSSEL_MASK) -#define DAC_OPA2MUX_POSSEL_DISABLE DAC_OPA2MUX_POSSEL(0) -#define DAC_OPA2MUX_POSSEL_DAC DAC_OPA2MUX_POSSEL(1) -#define DAC_OPA2MUX_POSSEL_POSPAD DAC_OPA2MUX_POSSEL(2) -#define DAC_OPA2MUX_POSSEL_OPA1INP DAC_OPA2MUX_POSSEL(3) -#define DAC_OPA2MUX_POSSEL_OPATAP DAC_OPA2MUX_POSSEL(4) - -/* DAC0 */ -#define DAC0 DAC0_BASE -#define DAC0_CTRL DAC_CTRL(DAC0) -#define DAC0_STATUS DAC_STATUS(DAC0) -#define DAC0_CH0CTRL DAC_CH0CTRL(DAC0) -#define DAC0_CH1CTRL DAC_CH1CTRL(DAC0) -#define DAC0_IEN DAC_IEN(DAC0) -#define DAC0_IF DAC_IF(DAC0) -#define DAC0_IFS DAC_IFS(DAC0) -#define DAC0_IFC DAC_IFC(DAC0) -#define DAC0_CH0DATA DAC_CH0DATA(DAC0) -#define DAC0_CH1DATA DAC_CH1DATA(DAC0) -#define DAC0_COMBDATA DAC_COMBDATA(DAC0) -#define DAC0_CAL DAC_CAL(DAC0) -#define DAC0_BIASPROG DAC_BIASPROG(DAC0) -#define DAC0_OPACTRL DAC_OPACTRL(DAC0) -#define DAC0_OPAOFFSET DAC_OPAOFFSET(DAC0) -#define DAC0_OPAOFFSET DAC_OPAOFFSET(DAC0) -#define DAC0_OPA1MUX DAC_OPA1MUX(DAC0) -#define DAC0_OPA2MUX DAC_OPA2MUX(DAC0) - -/** @defgroup dac_ch DAC Channel Number -@ingroup dac_defines - -@{*/ -enum dac_ch { - DAC_CH0 = 0, - DAC_CH1 -}; -/**@}*/ - -BEGIN_DECLS - -void dac_set_refresh_cycle(uint32_t dac_base, uint32_t refrsel); -void dac_set_clock_prescaler(uint32_t dac_base, uint32_t presc); -void dac_set_reference(uint32_t dac_base, uint32_t refsel); -void dac_set_out_mode(uint32_t dac_base, uint32_t outmode); -void dac_set_conversion_mode(uint32_t dac_base, uint32_t convmode); -void dac_enable_sine(uint32_t dac_base); -void dac_disable_sine(uint32_t dac_base); - -void dac_set_prs_trigger(uint32_t dac_base, enum dac_ch dac_chan, - enum prs_ch prs_chan); -void dac_enable_prs_trigger(uint32_t dac_base, enum dac_ch ch); -void dac_disable_prs_trigger(uint32_t dac_base, enum dac_ch ch); -void dac_enable_auto_refresh(uint32_t dac_base, enum dac_ch ch); -void dac_disable_auto_refresh(uint32_t dac_base, enum dac_ch ch); - -void dac_enable_channel(uint32_t dac_base, enum dac_ch ch); -void dac_disable_channel(uint32_t dac_base, enum dac_ch ch); - -END_DECLS +#include #endif - diff --git a/include/libopencm3/efm32/lg/dma.h b/include/libopencm3/efm32/lg/dma.h index b6fffb8b..f32149a1 100644 --- a/include/libopencm3/efm32/lg/dma.h +++ b/include/libopencm3/efm32/lg/dma.h @@ -1,7 +1,7 @@ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2015 Kuldeep Singh Dhaka + * Copyright (C) 2016 Bob Miller * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -17,896 +17,9 @@ * along with this library. If not, see . */ -#ifndef LIBOPENCM3_EFM32_DMA_H -#define LIBOPENCM3_EFM32_DMA_H +#ifndef LIBOPENCM3_EFM32_LG_DMA_H +#define LIBOPENCM3_EFM32_LG_DMA_H -#include -#include - -/* - * As per the datasheet, it is an PL230 (licenced from ARM) - * note: but only implement 12 channel (PL230 can have upto 32 channels) - * - * in-future: we can move this to a common peripherial directory - * that is idependent of core and as well as uC. - * something like device tree in Linux kernel - * - * note: DMA_STATUS contain the number of PL230 channel are implemented - */ - -#define DMA DMA_BASE - -#define DMA_STATUS MMIO32(DMA_BASE + 0x000) -#define DMA_CONFIG MMIO32(DMA_BASE + 0x004) -#define DMA_CTRLBASE MMIO32(DMA_BASE + 0x008) -#define DMA_ALTCTRLBASE MMIO32(DMA_BASE + 0x00C) - -#define DMA_CHWAITSTATUS MMIO32(DMA_BASE + 0x010) -#define DMA_CHSWREQ MMIO32(DMA_BASE + 0x014) -#define DMA_CHUSEBURSTS MMIO32(DMA_BASE + 0x018) -#define DMA_CHUSEBURSTC MMIO32(DMA_BASE + 0x01C) -#define DMA_CHREQMASKS MMIO32(DMA_BASE + 0x020) -#define DMA_CHREQMASKC MMIO32(DMA_BASE + 0x024) -#define DMA_CHENS MMIO32(DMA_BASE + 0x028) -#define DMA_CHENC MMIO32(DMA_BASE + 0x02C) -#define DMA_CHALTS MMIO32(DMA_BASE + 0x030) -#define DMA_CHALTC MMIO32(DMA_BASE + 0x034) -#define DMA_CHPRIS MMIO32(DMA_BASE + 0x038) -#define DMA_CHPRIC MMIO32(DMA_BASE + 0x03C) -#define DMA_ERRORC MMIO32(DMA_BASE + 0x04C) -#define DMA_CHREQSTATUS MMIO32(DMA_BASE + 0xE10) -#define DMA_CHSREQSTATUS MMIO32(DMA_BASE + 0xE18) -#define DMA_IF MMIO32(DMA_BASE + 0x1000) -#define DMA_IFS MMIO32(DMA_BASE + 0x1004) -#define DMA_IFC MMIO32(DMA_BASE + 0x1008) -#define DMA_IEN MMIO32(DMA_BASE + 0x100C) -#define DMA_CTRL MMIO32(DMA_BASE + 0x1010) -#define DMA_RDS MMIO32(DMA_BASE + 0x1014) - -#define DMA_LOOPx(i) MMIO32(DMA_BASE + 0x1020 + ((i) * 0x4)) -#define DMA_LOOP0 DMA_LOOPx(0) -#define DMA_LOOP1 DMA_LOOPx(1) - -#define DMA_RECTx(i) MMIO32(DMA_BASE + 0x1060 + ((i) * 0x4)) -#define DMA_RECT0 DMA_RECT(0) - -#define DMA_CHx_CTRL(i) MMIO32(DMA_BASE + 0x1100 + ((i) * 0x4)) -#define DMA_CH0_CTRL DMA_CHx_CTRL(0) -#define DMA_CH1_CTRL DMA_CHx_CTRL(1) -#define DMA_CH2_CTRL DMA_CHx_CTRL(2) -#define DMA_CH3_CTRL DMA_CHx_CTRL(3) -#define DMA_CH4_CTRL DMA_CHx_CTRL(4) -#define DMA_CH5_CTRL DMA_CHx_CTRL(5) -#define DMA_CH6_CTRL DMA_CHx_CTRL(6) -#define DMA_CH7_CTRL DMA_CHx_CTRL(7) -#define DMA_CH8_CTRL DMA_CHx_CTRL(8) -#define DMA_CH9_CTRL DMA_CHx_CTRL(9) -#define DMA_CH10_CTRL DMA_CHx_CTRL(10) -#define DMA_CH11_CTRL DMA_CHx_CTRL(11) - -/* DMA_STATUS */ -#define DMA_STATUS_CHNUM_SHIFT (16) -#define DMA_STATUS_CHNUM_MASK (0x1F << DMA_STATUS_CHNUM_SHIFT) - -#define DMA_STATUS_STATE_SHIFT (4) -#define DMA_STATUS_STATE_MASK (0xF << DMA_STATUS_STATE_SHIFT) -#define DMA_STATUS_STATE(v) \ - (((v) << DMA_STATUS_STATE_SHIFT) & DMA_STATUS_STATE_MASK) -#define DMA_STATUS_STATE_IDLE DMA_STATUS_STATE(0) -#define DMA_STATUS_STATE_RDCHCTRLDATA DMA_STATUS_STATE(1) -#define DMA_STATUS_STATE_RDSRCENDPTR DMA_STATUS_STATE(2) -#define DMA_STATUS_STATE_RDDSTENDPTR DMA_STATUS_STATE(3) -#define DMA_STATUS_STATE_RDSRCDATA DMA_STATUS_STATE(4) -#define DMA_STATUS_STATE_WRDSTDATA DMA_STATUS_STATE(5) -#define DMA_STATUS_STATE_WAITREQCLR DMA_STATUS_STATE(6) -#define DMA_STATUS_STATE_WRCHCTRLDATA DMA_STATUS_STATE(7) -#define DMA_STATUS_STATE_STALLED DMA_STATUS_STATE(8) -#define DMA_STATUS_STATE_DONE DMA_STATUS_STATE(9) -#define DMA_STATUS_STATE_PERSCATTRANS DMA_STATUS_STATE(10) - -#define DMA_STATUS_EN (1 << 0) - -/* DMA_CONFIG */ -#define DMA_CONFIG_CHPROT (1 << 5) -#define DMA_CONFIG_EN (1 << 0) - -/* DMA_CHWAITSTATUS */ -#define DMA_CHWAITSTATUS_CHxWAITSTATUS(i) (1 << (i)) -#define DMA_CHWAITSTATUS_CH11WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(11) -#define DMA_CHWAITSTATUS_CH10WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(10) -#define DMA_CHWAITSTATUS_CH9WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(9) -#define DMA_CHWAITSTATUS_CH8WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(8) -#define DMA_CHWAITSTATUS_CH7WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(7) -#define DMA_CHWAITSTATUS_CH6WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(6) -#define DMA_CHWAITSTATUS_CH5WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(5) -#define DMA_CHWAITSTATUS_CH4WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(4) -#define DMA_CHWAITSTATUS_CH3WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(3) -#define DMA_CHWAITSTATUS_CH2WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(2) -#define DMA_CHWAITSTATUS_CH1WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(1) -#define DMA_CHWAITSTATUS_CH0WAITSTATUS DMA_CHWAITSTATUS_CHxWAITSTATUS(0) - -/* DMA_CHSWREQ */ -#define DMA_CHSWREQ_CHxSWREQ(i) (1 << (i)) -#define DMA_CHSWREQ_CH11SWREQ DMA_CHSWREQ_CHxSWREQ(11) -#define DMA_CHSWREQ_CH10SWREQ DMA_CHSWREQ_CHxSWREQ(10) -#define DMA_CHSWREQ_CH9SWREQ DMA_CHSWREQ_CHxSWREQ(9) -#define DMA_CHSWREQ_CH8SWREQ DMA_CHSWREQ_CHxSWREQ(8) -#define DMA_CHSWREQ_CH7SWREQ DMA_CHSWREQ_CHxSWREQ(7) -#define DMA_CHSWREQ_CH6SWREQ DMA_CHSWREQ_CHxSWREQ(6) -#define DMA_CHSWREQ_CH5SWREQ DMA_CHSWREQ_CHxSWREQ(5) -#define DMA_CHSWREQ_CH4SWREQ DMA_CHSWREQ_CHxSWREQ(4) -#define DMA_CHSWREQ_CH3SWREQ DMA_CHSWREQ_CHxSWREQ(3) -#define DMA_CHSWREQ_CH2SWREQ DMA_CHSWREQ_CHxSWREQ(2) -#define DMA_CHSWREQ_CH1SWREQ DMA_CHSWREQ_CHxSWREQ(1) -#define DMA_CHSWREQ_CH0SWREQ DMA_CHSWREQ_CHxSWREQ(0) - -/* DMA_CHUSEBURSTS */ -#define DMA_CHUSEBURSTS_CHxSUSEBURSTS(i) (1 << (i)) -#define DMA_CHUSEBURSTS_CH11SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(11) -#define DMA_CHUSEBURSTS_CH10SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(10) -#define DMA_CHUSEBURSTS_CH9SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(9) -#define DMA_CHUSEBURSTS_CH8SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(8) -#define DMA_CHUSEBURSTS_CH7SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(7) -#define DMA_CHUSEBURSTS_CH6SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(6) -#define DMA_CHUSEBURSTS_CH5SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(5) -#define DMA_CHUSEBURSTS_CH4SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(4) -#define DMA_CHUSEBURSTS_CH3SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(3) -#define DMA_CHUSEBURSTS_CH2SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(2) -#define DMA_CHUSEBURSTS_CH1SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(1) -#define DMA_CHUSEBURSTS_CH0SUSEBURSTS DMA_CHUSEBURSTS_CHxSUSEBURSTS(0) - -/* DMA_CHUSEBURSTC */ -#define DMA_CHUSEBURSTC_CHxSUSEBURSTC(i) (1 << (i)) -#define DMA_CHUSEBURSTC_CH11SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(11) -#define DMA_CHUSEBURSTC_CH10SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(10) -#define DMA_CHUSEBURSTC_CH9SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(9) -#define DMA_CHUSEBURSTC_CH8SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(8) -#define DMA_CHUSEBURSTC_CH7SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(7) -#define DMA_CHUSEBURSTC_CH6SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(6) -#define DMA_CHUSEBURSTC_CH5SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(5) -#define DMA_CHUSEBURSTC_CH4SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(4) -#define DMA_CHUSEBURSTC_CH3SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(3) -#define DMA_CHUSEBURSTC_CH2SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(2) -#define DMA_CHUSEBURSTC_CH1SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(1) -#define DMA_CHUSEBURSTC_CH0SUSEBURSTC DMA_CHUSEBURSTC_CHxSUSEBURSTC(0) - -/* DMA_CHREQMASKS */ -#define DMA_CHREQMASKS_CHxSREQMASKS(i) (1 << (i)) -#define DMA_CHREQMASKS_CH11SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(11) -#define DMA_CHREQMASKS_CH10SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(10) -#define DMA_CHREQMASKS_CH9SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(9) -#define DMA_CHREQMASKS_CH8SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(8) -#define DMA_CHREQMASKS_CH7SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(7) -#define DMA_CHREQMASKS_CH6SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(6) -#define DMA_CHREQMASKS_CH5SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(5) -#define DMA_CHREQMASKS_CH4SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(4) -#define DMA_CHREQMASKS_CH3SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(3) -#define DMA_CHREQMASKS_CH2SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(2) -#define DMA_CHREQMASKS_CH1SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(1) -#define DMA_CHREQMASKS_CH0SREQMASKS DMA_CHREQMASKS_CHxSREQMASKS(0) - -/* DMA_CHREQMASKC */ -#define DMA_CHREQMASKC_CHxSREQMASKC(i) (1 << (i)) -#define DMA_CHREQMASKC_CH11SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(11) -#define DMA_CHREQMASKC_CH10SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(10) -#define DMA_CHREQMASKC_CH9SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(9) -#define DMA_CHREQMASKC_CH8SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(8) -#define DMA_CHREQMASKC_CH7SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(7) -#define DMA_CHREQMASKC_CH6SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(6) -#define DMA_CHREQMASKC_CH5SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(5) -#define DMA_CHREQMASKC_CH4SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(4) -#define DMA_CHREQMASKC_CH3SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(3) -#define DMA_CHREQMASKC_CH2SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(2) -#define DMA_CHREQMASKC_CH1SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(1) -#define DMA_CHREQMASKC_CH0SREQMASKC DMA_CHREQMASKC_CHxSREQMASKC(0) - -/* DMA_CHENS */ -#define DMA_CHENS_CHxSENS(i) (1 << (i)) -#define DMA_CHENS_CH11SENS DMA_CHENS_CHxSENS(11) -#define DMA_CHENS_CH10SENS DMA_CHENS_CHxSENS(10) -#define DMA_CHENS_CH9SENS DMA_CHENS_CHxSENS(9) -#define DMA_CHENS_CH8SENS DMA_CHENS_CHxSENS(8) -#define DMA_CHENS_CH7SENS DMA_CHENS_CHxSENS(7) -#define DMA_CHENS_CH6SENS DMA_CHENS_CHxSENS(6) -#define DMA_CHENS_CH5SENS DMA_CHENS_CHxSENS(5) -#define DMA_CHENS_CH4SENS DMA_CHENS_CHxSENS(4) -#define DMA_CHENS_CH3SENS DMA_CHENS_CHxSENS(3) -#define DMA_CHENS_CH2SENS DMA_CHENS_CHxSENS(2) -#define DMA_CHENS_CH1SENS DMA_CHENS_CHxSENS(1) -#define DMA_CHENS_CH0SENS DMA_CHENS_CHxSENS(0) - -/* DMA_CHENC */ -#define DMA_CHENC_CHxSENC(i) (1 << (i)) -#define DMA_CHENC_CH11SENC DMA_CHENC_CHxSENC(11) -#define DMA_CHENC_CH10SENC DMA_CHENC_CHxSENC(10) -#define DMA_CHENC_CH9SENC DMA_CHENC_CHxSENC(9) -#define DMA_CHENC_CH8SENC DMA_CHENC_CHxSENC(8) -#define DMA_CHENC_CH7SENC DMA_CHENC_CHxSENC(7) -#define DMA_CHENC_CH6SENC DMA_CHENC_CHxSENC(6) -#define DMA_CHENC_CH5SENC DMA_CHENC_CHxSENC(5) -#define DMA_CHENC_CH4SENC DMA_CHENC_CHxSENC(4) -#define DMA_CHENC_CH3SENC DMA_CHENC_CHxSENC(3) -#define DMA_CHENC_CH2SENC DMA_CHENC_CHxSENC(2) -#define DMA_CHENC_CH1SENC DMA_CHENC_CHxSENC(1) -#define DMA_CHENC_CH0SENC DMA_CHENC_CHxSENC(0) - -/* DMA_CHALTS */ -#define DMA_CHALTS_CHxSALTS(i) (1 << (i)) -#define DMA_CHALTS_CH11SALTS DMA_CHALTS_CHxSALTS(11) -#define DMA_CHALTS_CH10SALTS DMA_CHALTS_CHxSALTS(10) -#define DMA_CHALTS_CH9SALTS DMA_CHALTS_CHxSALTS(9) -#define DMA_CHALTS_CH8SALTS DMA_CHALTS_CHxSALTS(8) -#define DMA_CHALTS_CH7SALTS DMA_CHALTS_CHxSALTS(7) -#define DMA_CHALTS_CH6SALTS DMA_CHALTS_CHxSALTS(6) -#define DMA_CHALTS_CH5SALTS DMA_CHALTS_CHxSALTS(5) -#define DMA_CHALTS_CH4SALTS DMA_CHALTS_CHxSALTS(4) -#define DMA_CHALTS_CH3SALTS DMA_CHALTS_CHxSALTS(3) -#define DMA_CHALTS_CH2SALTS DMA_CHALTS_CHxSALTS(2) -#define DMA_CHALTS_CH1SALTS DMA_CHALTS_CHxSALTS(1) -#define DMA_CHALTS_CH0SALTS DMA_CHALTS_CHxSALTS(0) - -/* DMA_CHALTC */ -#define DMA_CHALTC_CHxSALTC(i) (1 << (i)) -#define DMA_CHALTC_CH11SALTC DMA_CHALTC_CHxSALTC(11) -#define DMA_CHALTC_CH10SALTC DMA_CHALTC_CHxSALTC(10) -#define DMA_CHALTC_CH9SALTC DMA_CHALTC_CHxSALTC(9) -#define DMA_CHALTC_CH8SALTC DMA_CHALTC_CHxSALTC(8) -#define DMA_CHALTC_CH7SALTC DMA_CHALTC_CHxSALTC(7) -#define DMA_CHALTC_CH6SALTC DMA_CHALTC_CHxSALTC(6) -#define DMA_CHALTC_CH5SALTC DMA_CHALTC_CHxSALTC(5) -#define DMA_CHALTC_CH4SALTC DMA_CHALTC_CHxSALTC(4) -#define DMA_CHALTC_CH3SALTC DMA_CHALTC_CHxSALTC(3) -#define DMA_CHALTC_CH2SALTC DMA_CHALTC_CHxSALTC(2) -#define DMA_CHALTC_CH1SALTC DMA_CHALTC_CHxSALTC(1) -#define DMA_CHALTC_CH0SALTC DMA_CHALTC_CHxSALTC(0) - -/* DMA_CHPRIS */ -#define DMA_CHPRIS_CHxSPRIC(i) (1 << (i)) -#define DMA_CHPRIS_CH11SPRIC DMA_CHPRIS_CHxSPRIC(11) -#define DMA_CHPRIS_CH10SPRIC DMA_CHPRIS_CHxSPRIC(10) -#define DMA_CHPRIS_CH9SPRIC DMA_CHPRIS_CHxSPRIC(9) -#define DMA_CHPRIS_CH8SPRIC DMA_CHPRIS_CHxSPRIC(8) -#define DMA_CHPRIS_CH7SPRIC DMA_CHPRIS_CHxSPRIC(7) -#define DMA_CHPRIS_CH6SPRIC DMA_CHPRIS_CHxSPRIC(6) -#define DMA_CHPRIS_CH5SPRIC DMA_CHPRIS_CHxSPRIC(5) -#define DMA_CHPRIS_CH4SPRIC DMA_CHPRIS_CHxSPRIC(4) -#define DMA_CHPRIS_CH3SPRIC DMA_CHPRIS_CHxSPRIC(3) -#define DMA_CHPRIS_CH2SPRIC DMA_CHPRIS_CHxSPRIC(2) -#define DMA_CHPRIS_CH1SPRIC DMA_CHPRIS_CHxSPRIC(1) -#define DMA_CHPRIS_CH0SPRIC DMA_CHPRIS_CHxSPRIC(0) - -/* DMA_CHPRIC */ -#define DMA_CHPRIC_CHxSPRIC(i) (1 << (i)) -#define DMA_CHPRIC_CH11SPRIC DMA_CHPRIC_CHxSPRIC(11) -#define DMA_CHPRIC_CH10SPRIC DMA_CHPRIC_CHxSPRIC(10) -#define DMA_CHPRIC_CH9SPRIC DMA_CHPRIC_CHxSPRIC(9) -#define DMA_CHPRIC_CH8SPRIC DMA_CHPRIC_CHxSPRIC(8) -#define DMA_CHPRIC_CH7SPRIC DMA_CHPRIC_CHxSPRIC(7) -#define DMA_CHPRIC_CH6SPRIC DMA_CHPRIC_CHxSPRIC(6) -#define DMA_CHPRIC_CH5SPRIC DMA_CHPRIC_CHxSPRIC(5) -#define DMA_CHPRIC_CH4SPRIC DMA_CHPRIC_CHxSPRIC(4) -#define DMA_CHPRIC_CH3SPRIC DMA_CHPRIC_CHxSPRIC(3) -#define DMA_CHPRIC_CH2SPRIC DMA_CHPRIC_CHxSPRIC(2) -#define DMA_CHPRIC_CH1SPRIC DMA_CHPRIC_CHxSPRIC(1) -#define DMA_CHPRIC_CH0SPRIC DMA_CHPRIC_CHxSPRIC(0) - -/* DMA_ERRORC */ -#define DMA_ERRORC_ERRORC (1 << 0) - -/* DMA_CHREQSTATUS */ -#define DMA_CHREQSTATUS_CHxSREQSTATUS(i) (1 << (i)) -#define DMA_CHREQSTATUS_CH11SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(11) -#define DMA_CHREQSTATUS_CH10SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(10) -#define DMA_CHREQSTATUS_CH9SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(9) -#define DMA_CHREQSTATUS_CH8SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(8) -#define DMA_CHREQSTATUS_CH7SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(7) -#define DMA_CHREQSTATUS_CH6SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(6) -#define DMA_CHREQSTATUS_CH5SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(5) -#define DMA_CHREQSTATUS_CH4SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(4) -#define DMA_CHREQSTATUS_CH3SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(3) -#define DMA_CHREQSTATUS_CH2SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(2) -#define DMA_CHREQSTATUS_CH1SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(1) -#define DMA_CHREQSTATUS_CH0SREQSTATUS DMA_CHREQSTATUS_CHxSREQSTATUS(0) - -/* DMA_CHSREQSTATUS */ -#define DMA_CHSREQSTATUS_CHxSREQSTATUS(i) (1 << (i)) -#define DMA_CHSREQSTATUS_CH11SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(11) -#define DMA_CHSREQSTATUS_CH10SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(10) -#define DMA_CHSREQSTATUS_CH9SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(9) -#define DMA_CHSREQSTATUS_CH8SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(8) -#define DMA_CHSREQSTATUS_CH7SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(7) -#define DMA_CHSREQSTATUS_CH6SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(6) -#define DMA_CHSREQSTATUS_CH5SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(5) -#define DMA_CHSREQSTATUS_CH4SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(4) -#define DMA_CHSREQSTATUS_CH3SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(3) -#define DMA_CHSREQSTATUS_CH2SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(2) -#define DMA_CHSREQSTATUS_CH1SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(1) -#define DMA_CHSREQSTATUS_CH0SREQSTATUS DMA_CHSREQSTATUS_CHxSREQSTATUS(0) - -/* DMA_IF */ -#define DMA_IF_ERR (1UL << 31) -#define DMA_IF_CHxDONE(x) (1 << (x)) -#define DMA_IF_CH11DONE DMA_IF_CHxDONE(11) -#define DMA_IF_CH10DONE DMA_IF_CHxDONE(10) -#define DMA_IF_CH9DONE DMA_IF_CHxDONE(9) -#define DMA_IF_CH8DONE DMA_IF_CHxDONE(8) -#define DMA_IF_CH7DONE DMA_IF_CHxDONE(7) -#define DMA_IF_CH6DONE DMA_IF_CHxDONE(6) -#define DMA_IF_CH5DONE DMA_IF_CHxDONE(5) -#define DMA_IF_CH4DONE DMA_IF_CHxDONE(4) -#define DMA_IF_CH3DONE DMA_IF_CHxDONE(3) -#define DMA_IF_CH2DONE DMA_IF_CHxDONE(2) -#define DMA_IF_CH1DONE DMA_IF_CHxDONE(1) -#define DMA_IF_CH0DONE DMA_IF_CHxDONE(0) - - -/* DMA_IFS */ -#define DMA_IFS_ERR (1 << 31) -#define DMA_IFS_CHxDONE(x) (1 << (x)) -#define DMA_IFS_CH11DONE DMA_IFS_CHxDONE(11) -#define DMA_IFS_CH10DONE DMA_IFS_CHxDONE(10) -#define DMA_IFS_CH9DONE DMA_IFS_CHxDONE(9) -#define DMA_IFS_CH8DONE DMA_IFS_CHxDONE(8) -#define DMA_IFS_CH7DONE DMA_IFS_CHxDONE(7) -#define DMA_IFS_CH6DONE DMA_IFS_CHxDONE(6) -#define DMA_IFS_CH5DONE DMA_IFS_CHxDONE(5) -#define DMA_IFS_CH4DONE DMA_IFS_CHxDONE(4) -#define DMA_IFS_CH3DONE DMA_IFS_CHxDONE(3) -#define DMA_IFS_CH2DONE DMA_IFS_CHxDONE(2) -#define DMA_IFS_CH1DONE DMA_IFS_CHxDONE(1) -#define DMA_IFS_CH0DONE DMA_IFS_CHxDONE(0) - -/* DMA_IFC */ -#define DMA_IFC_ERR (1 << 31) -#define DMA_IFC_CHxDONE(x) (1 << (x)) -#define DMA_IFC_CH11DONE DMA_IFC_CHxDONE(11) -#define DMA_IFC_CH10DONE DMA_IFC_CHxDONE(10) -#define DMA_IFC_CH9DONE DMA_IFC_CHxDONE(9) -#define DMA_IFC_CH8DONE DMA_IFC_CHxDONE(8) -#define DMA_IFC_CH7DONE DMA_IFC_CHxDONE(7) -#define DMA_IFC_CH6DONE DMA_IFC_CHxDONE(6) -#define DMA_IFC_CH5DONE DMA_IFC_CHxDONE(5) -#define DMA_IFC_CH4DONE DMA_IFC_CHxDONE(4) -#define DMA_IFC_CH3DONE DMA_IFC_CHxDONE(3) -#define DMA_IFC_CH2DONE DMA_IFC_CHxDONE(2) -#define DMA_IFC_CH1DONE DMA_IFC_CHxDONE(1) -#define DMA_IFC_CH0DONE DMA_IFC_CHxDONE(0) - -/* DMA_IEN */ -#define DMA_IEN_ERR (1 << 31) -#define DMA_IEN_CHxDONE(x) (1 << (x)) -#define DMA_IEN_CH11DONE DMA_IEN_CHxDONE(11) -#define DMA_IEN_CH10DONE DMA_IEN_CHxDONE(10) -#define DMA_IEN_CH9DONE DMA_IEN_CHxDONE(9) -#define DMA_IEN_CH8DONE DMA_IEN_CHxDONE(8) -#define DMA_IEN_CH7DONE DMA_IEN_CHxDONE(7) -#define DMA_IEN_CH6DONE DMA_IEN_CHxDONE(6) -#define DMA_IEN_CH5DONE DMA_IEN_CHxDONE(5) -#define DMA_IEN_CH4DONE DMA_IEN_CHxDONE(4) -#define DMA_IEN_CH3DONE DMA_IEN_CHxDONE(3) -#define DMA_IEN_CH2DONE DMA_IEN_CHxDONE(2) -#define DMA_IEN_CH1DONE DMA_IEN_CHxDONE(1) -#define DMA_IEN_CH0DONE DMA_IEN_CHxDONE(0) - -/* DMA_CTRL */ -#define DMA_CTRL_PRDU (1 << 1) -#define DMA_CTRL_DESCRECT (1 << 0) - -/* DMA_RDS */ -#define DMA_RDS_RDSCHx(i) (1 << (i)) -#define DMA_RDS_RDSCH11 DMA_RDS_RDSCHx(11) -#define DMA_RDS_RDSCH10 DMA_RDS_RDSCHx(10) -#define DMA_RDS_RDSCH9 DMA_RDS_RDSCHx(9) -#define DMA_RDS_RDSCH8 DMA_RDS_RDSCHx(8) -#define DMA_RDS_RDSCH7 DMA_RDS_RDSCHx(7) -#define DMA_RDS_RDSCH6 DMA_RDS_RDSCHx(6) -#define DMA_RDS_RDSCH5 DMA_RDS_RDSCHx(5) -#define DMA_RDS_RDSCH4 DMA_RDS_RDSCHx(4) -#define DMA_RDS_RDSCH3 DMA_RDS_RDSCHx(3) -#define DMA_RDS_RDSCH2 DMA_RDS_RDSCHx(2) -#define DMA_RDS_RDSCH1 DMA_RDS_RDSCHx(1) -#define DMA_RDS_RDSCH0 DMA_RDS_RDSCHx(0) - -/* DMA_LOOP */ -#define DMA_LOOP_EN (1 << 16) -#define DMA_LOOP_WIDTH_SHIFT (0) -#define DMA_LOOP_WIDTH_MASK (0x3FF << DMA_LOOP_WIDTH_SHIFT) -#define DMA_LOOP_WIDTH(v) \ - (((v) << DMA_LOOP_WIDTH_SHIFT) & DMA_LOOP_WIDTH_MASK) - -/* DMA_RECT */ -#define DMA_RECT_DSTSTRIDE_SHIFT (21) -#define DMA_RECT_DSTSTRIDE_MASK (0x7FF << DMA_RECT_DSTSTRIDE_SHIFT) -#define DMA_RECT_DSTSTRIDE(v) \ - (((v) << DMA_RECT_DSTSTRIDE_SHIFT) & DMA_RECT_DSTSTRIDE_MASK) - -#define DMA_RECT_SRCSTRIDE_SHIFT (10) -#define DMA_RECT_SRCSTRIDE_MASK (0x7FF << DMA_RECT_SRCSTRIDE_SHIFT) -#define DMA_RECT_SRCSTRIDE(v) \ - (((v) << DMA_RECT_SRCSTRIDE_SHIFT) & DMA_RECT_SRCSTRIDE_MASK) - -#define DMA_RECT_HEIGHT_SHIFT (0) -#define DMA_RECT_HEIGHT_MASK (0x3FF << DMA_RECT_HEIGHT_SHIFT) -#define DMA_RECT_HEIGHT(v) \ - (((v) << DMA_RECT_HEIGHT_SHIFT) & DMA_RECT_HEIGHT_MASK) - -/* DMA_CH_CTRL */ -#define DMA_CH_CTRL_SOURCESEL_SHIFT (16) -#define DMA_CH_CTRL_SOURCESEL_MASK (0x3F << DMA_CH_CTRL_SOURCESEL_SHIFT) -#define DMA_CH_CTRL_SOURCESEL(v) \ - (((v) << DMA_CH_CTRL_SOURCESEL_SHIFT) & DMA_CH_CTRL_SOURCESEL_MASK) -#define DMA_CH_CTRL_SOURCESEL_NONE DMA_CH_CTRL_SOURCESEL(0b000000) -#define DMA_CH_CTRL_SOURCESEL_ADC0 DMA_CH_CTRL_SOURCESEL(0b001000) -#define DMA_CH_CTRL_SOURCESEL_DAC0 DMA_CH_CTRL_SOURCESEL(0b001010) -#define DMA_CH_CTRL_SOURCESEL_USART0 DMA_CH_CTRL_SOURCESEL(0b001100) -#define DMA_CH_CTRL_SOURCESEL_USART1 DMA_CH_CTRL_SOURCESEL(0b001101) -#define DMA_CH_CTRL_SOURCESEL_USART2 DMA_CH_CTRL_SOURCESEL(0b001110) -#define DMA_CH_CTRL_SOURCESEL_LEUART0 DMA_CH_CTRL_SOURCESEL(0b010000) -#define DMA_CH_CTRL_SOURCESEL_LEUART1 DMA_CH_CTRL_SOURCESEL(0b010001) -#define DMA_CH_CTRL_SOURCESEL_I2C0 DMA_CH_CTRL_SOURCESEL(0b010100) -#define DMA_CH_CTRL_SOURCESEL_I2C1 DMA_CH_CTRL_SOURCESEL(0b010101) -#define DMA_CH_CTRL_SOURCESEL_TIMER0 DMA_CH_CTRL_SOURCESEL(0b011000) -#define DMA_CH_CTRL_SOURCESEL_TIMER1 DMA_CH_CTRL_SOURCESEL(0b011001) -#define DMA_CH_CTRL_SOURCESEL_TIMER2 DMA_CH_CTRL_SOURCESEL(0b011010) -#define DMA_CH_CTRL_SOURCESEL_TIMER3 DMA_CH_CTRL_SOURCESEL(0b011011) -#define DMA_CH_CTRL_SOURCESEL_UART0 DMA_CH_CTRL_SOURCESEL(0b101100) -#define DMA_CH_CTRL_SOURCESEL_UART1 DMA_CH_CTRL_SOURCESEL(0b101101) -#define DMA_CH_CTRL_SOURCESEL_MSC DMA_CH_CTRL_SOURCESEL(0b110000) -#define DMA_CH_CTRL_SOURCESEL_AES DMA_CH_CTRL_SOURCESEL(0b110001) -#define DMA_CH_CTRL_SOURCESEL_LESENSE DMA_CH_CTRL_SOURCESEL(0b110010) -#define DMA_CH_CTRL_SOURCESEL_EBI DMA_CH_CTRL_SOURCESEL(0b110011) - -#define DMA_CH_CTRL_SIGSEL_SHIFT (0) -#define DMA_CH_CTRL_SIGSEL_MASK (0xF << DMA_CH_CTRL_SIGSEL_SHIFT) -#define DMA_CH_CTRL_SIGSEL(v) \ - (((v) << DMA_CH_CTRL_SIGSEL_SHIFT) & DMA_CH_CTRL_SIGSEL_MASK) - -#define DMA_CH_CTRL_SIGSEL_OFF DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_ADC0SINGLE DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_ADC0SCAN DMA_CH_CTRL_SIGSEL(1) -#define DMA_CH_CTRL_SIGSEL_DAC0CH0 DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_DAC0CH1 DMA_CH_CTRL_SIGSEL(1) -#define DMA_CH_CTRL_SIGSEL_USART0RXDATAV DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_USART0TXBL DMA_CH_CTRL_SIGSEL(1) -#define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY DMA_CH_CTRL_SIGSEL(2) -#define DMA_CH_CTRL_SIGSEL_USART1RXDATAV DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_USART1TXBL DMA_CH_CTRL_SIGSEL(1) -#define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY DMA_CH_CTRL_SIGSEL(2) -#define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT DMA_CH_CTRL_SIGSEL(3) -#define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT DMA_CH_CTRL_SIGSEL(4) -#define DMA_CH_CTRL_SIGSEL_USART2RXDATAV DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_USART2TXBL DMA_CH_CTRL_SIGSEL(1) -#define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY DMA_CH_CTRL_SIGSEL(2) -#define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT DMA_CH_CTRL_SIGSEL(3) -#define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT DMA_CH_CTRL_SIGSEL(4) -#define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_LEUART0TXBL DMA_CH_CTRL_SIGSEL(1) -#define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY DMA_CH_CTRL_SIGSEL(2) -#define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_LEUART1TXBL DMA_CH_CTRL_SIGSEL(1) -#define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY DMA_CH_CTRL_SIGSEL(2) -#define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_I2C0TXBL DMA_CH_CTRL_SIGSEL(1) -#define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_I2C1TXBL DMA_CH_CTRL_SIGSEL(1) -#define DMA_CH_CTRL_SIGSEL_TIMER0UFOF DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_TIMER0CC0 DMA_CH_CTRL_SIGSEL(1) -#define DMA_CH_CTRL_SIGSEL_TIMER0CC1 DMA_CH_CTRL_SIGSEL(2) -#define DMA_CH_CTRL_SIGSEL_TIMER0CC2 DMA_CH_CTRL_SIGSEL(3) -#define DMA_CH_CTRL_SIGSEL_TIMER1UFOF DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_TIMER1CC0 DMA_CH_CTRL_SIGSEL(1) -#define DMA_CH_CTRL_SIGSEL_TIMER1CC1 DMA_CH_CTRL_SIGSEL(2) -#define DMA_CH_CTRL_SIGSEL_TIMER1CC2 DMA_CH_CTRL_SIGSEL(3) -#define DMA_CH_CTRL_SIGSEL_TIMER2UFOF DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_TIMER2CC0 DMA_CH_CTRL_SIGSEL(1) -#define DMA_CH_CTRL_SIGSEL_TIMER2CC1 DMA_CH_CTRL_SIGSEL(2) -#define DMA_CH_CTRL_SIGSEL_TIMER2CC2 DMA_CH_CTRL_SIGSEL(3) -#define DMA_CH_CTRL_SIGSEL_TIMER3UFOF DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_TIMER3CC0 DMA_CH_CTRL_SIGSEL(1) -#define DMA_CH_CTRL_SIGSEL_TIMER3CC1 DMA_CH_CTRL_SIGSEL(2) -#define DMA_CH_CTRL_SIGSEL_TIMER3CC2 DMA_CH_CTRL_SIGSEL(3) -#define DMA_CH_CTRL_SIGSEL_UART0RXDATAV DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_UART0TXBL DMA_CH_CTRL_SIGSEL(1) -#define DMA_CH_CTRL_SIGSEL_UART0TXEMPTY DMA_CH_CTRL_SIGSEL(2) -#define DMA_CH_CTRL_SIGSEL_UART1RXDATAV DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_UART1TXBL DMA_CH_CTRL_SIGSEL(1) -#define DMA_CH_CTRL_SIGSEL_UART1TXEMPTY DMA_CH_CTRL_SIGSEL(2) -#define DMA_CH_CTRL_SIGSEL_MSCWDATA DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_AESDATAWR DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_AESXORDATAWR DMA_CH_CTRL_SIGSEL(1) -#define DMA_CH_CTRL_SIGSEL_AESDATARD DMA_CH_CTRL_SIGSEL(2) -#define DMA_CH_CTRL_SIGSEL_AESKEYWR DMA_CH_CTRL_SIGSEL(3) -#define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_EBIPXL0EMPTY DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_EBIPXL1EMPTY DMA_CH_CTRL_SIGSEL(1) -#define DMA_CH_CTRL_SIGSEL_EBIPXLFULL DMA_CH_CTRL_SIGSEL(2) -#define DMA_CH_CTRL_SIGSEL_EBIDDEMPTY DMA_CH_CTRL_SIGSEL(3) - -/* generic of above */ -#define DMA_CH_CTRL_SIGSEL_ADC_SINGLE DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_ADC_SCAN DMA_CH_CTRL_SIGSEL(1) -#define DMA_CH_CTRL_SIGSEL_DAC_CHx(x) DMA_CH_CTRL_SIGSEL(x) -#define DMA_CH_CTRL_SIGSEL_DAC_CH0 DMA_CH_CTRL_SIGSEL_DAC_CHx(0) -#define DMA_CH_CTRL_SIGSEL_DAC_CH1 DMA_CH_CTRL_SIGSEL_DAC_CHx(1) -#define DMA_CH_CTRL_SIGSEL_USART_RXDATAV DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_USART_TXBL DMA_CH_CTRL_SIGSEL(1) -#define DMA_CH_CTRL_SIGSEL_USART_TXEMPTY DMA_CH_CTRL_SIGSEL(2) -#define DMA_CH_CTRL_SIGSEL_USART_RXDATAVRIGHT DMA_CH_CTRL_SIGSEL(3) -#define DMA_CH_CTRL_SIGSEL_USART_TXBLRIGHT DMA_CH_CTRL_SIGSEL(4) -#define DMA_CH_CTRL_SIGSEL_LEUART_RXDATAV DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_LEUART_TXBL DMA_CH_CTRL_SIGSEL(1) -#define DMA_CH_CTRL_SIGSEL_LEUART_TXEMPTY DMA_CH_CTRL_SIGSEL(2) -#define DMA_CH_CTRL_SIGSEL_I2C_RXDATAV DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_I2C_TXBL DMA_CH_CTRL_SIGSEL(1) -#define DMA_CH_CTRL_SIGSEL_I2C_RXDATAV DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_I2C_TXBL DMA_CH_CTRL_SIGSEL(1) -#define DMA_CH_CTRL_SIGSEL_TIMER_UFOF DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_TIMER_CCx(x) DMA_CH_CTRL_SIGSEL((x) + 1) -#define DMA_CH_CTRL_SIGSEL_TIMER_CC0 DMA_CH_CTRL_SIGSEL_TIMER_CCx(0) -#define DMA_CH_CTRL_SIGSEL_TIMER_CC1 DMA_CH_CTRL_SIGSEL_TIMER_CCx(1) -#define DMA_CH_CTRL_SIGSEL_TIMER_CC2 DMA_CH_CTRL_SIGSEL_TIMER_CCx(3) -#define DMA_CH_CTRL_SIGSEL_UART_RXDATAV DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_UART_TXBL DMA_CH_CTRL_SIGSEL(1) -#define DMA_CH_CTRL_SIGSEL_UART_TXEMPTY DMA_CH_CTRL_SIGSEL(2) -#define DMA_CH_CTRL_SIGSEL_MSC_WDATA DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_AES_DATA_WR DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_AES_XOR_DATA_WR DMA_CH_CTRL_SIGSEL(1) -#define DMA_CH_CTRL_SIGSEL_AES_DATA_RD DMA_CH_CTRL_SIGSEL(2) -#define DMA_CH_CTRL_SIGSEL_AES_KEY_WR DMA_CH_CTRL_SIGSEL(3) -#define DMA_CH_CTRL_SIGSEL_LESENSE_BUF_DATAV DMA_CH_CTRL_SIGSEL(0) -#define DMA_CH_CTRL_SIGSEL_EBI_PXLx_EMPTY(x) DMA_CH_CTRL_SIGSEL(x) -#define DMA_CH_CTRL_SIGSEL_EBI_PXL0_EMPTY \ - DMA_CH_CTRL_SIGSEL_EBI_PXLx_EMPTY(0) -#define DMA_CH_CTRL_SIGSEL_EBI_PXL1_EMPTY \ - DMA_CH_CTRL_SIGSEL_EBI_PXLx_EMPTY(1) -#define DMA_CH_CTRL_SIGSEL_EBI_PXL_FULL DMA_CH_CTRL_SIGSEL(2) -#define DMA_CH_CTRL_SIGSEL_EBI_DD_EMPTY DMA_CH_CTRL_SIGSEL(3) - -/** - * Application needs to allocate (DMA_DESC_CH_SIZE * N) byte - * where N is the number of first N channels to use. - * and this allocated memory needs to be assigned to DMA using - * dma_set_desc_address(). - * - * if the application code needs alternate descriptor facility also. - * it needs to allocate the required memory (usually equal to the one above) - * and assign the memory using dma_set_alternate_desc_address() - * - * rest of the work will be transparently managed by convience functions. - * - * all the memory above should be aligned to 256bit - * (ie LSB 8bits of array address should be 0) - * use gcc's __attribute__((aligned(256))) - */ -#define DMA_DESC_CH_SIZE (0x4 * 0x4) -#define DMA_DESC_CHx_BASE(base, x) \ - ((base) + ((x) * DMA_DESC_CH_SIZE)) -#define DMA_DESC_CHx_SRC_DATA_END_PTR(base, x) \ - MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x00) -#define DMA_DESC_CHx_DEST_DATA_END_PTR(base, x) \ - MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x04) -#define DMA_DESC_CHx_CFG(base, x) \ - MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x08) -#define DMA_DESC_CHx_USER_DATA(base, x) \ - MMIO32(DMA_DESC_CHx_BASE(base, x) + 0x0C) - -/* DMA_DESC_CH_CFG */ -#define DMA_DESC_CH_CFG_DEST_INC_SHIFT (30) -#define DMA_DESC_CH_CFG_DEST_INC_MASK \ - (0x3 << DMA_DESC_CH_CFG_DEST_INC_SHIFT) -#define DMA_DESC_CH_CFG_DEST_INC(v) \ - (((v) << DMA_DESC_CH_CFG_DEST_INC_SHIFT) & \ - DMA_DESC_CH_CFG_DEST_INC_MASK) -#define DMA_DESC_CH_CFG_DEST_INC_BYTE DMA_DESC_CH_CFG_DEST_INC(0) -#define DMA_DESC_CH_CFG_DEST_INC_HALFWORD DMA_DESC_CH_CFG_DEST_INC(1) -#define DMA_DESC_CH_CFG_DEST_INC_WORD DMA_DESC_CH_CFG_DEST_INC(2) -#define DMA_DESC_CH_CFG_DEST_INC_NOINC DMA_DESC_CH_CFG_DEST_INC(3) - -#define DMA_DESC_CH_CFG_DEST_SIZE_SHIFT (28) -#define DMA_DESC_CH_CFG_DEST_SIZE_MASK \ - (0x3 << DMA_DESC_CH_CFG_DEST_SIZE_SHIFT) -#define DMA_DESC_CH_CFG_DEST_SIZE(v) \ - (((v) << DMA_DESC_CH_CFG_DEST_SIZE_SHIFT) & \ - DMA_DESC_CH_CFG_DEST_SIZE_MASK) -#define DMA_DESC_CH_CFG_DEST_SIZE_BYTE DMA_DESC_CH_CFG_DEST_SIZE(0) -#define DMA_DESC_CH_CFG_DEST_SIZE_HALFWORD DMA_DESC_CH_CFG_DEST_SIZE(1) -#define DMA_DESC_CH_CFG_DEST_SIZE_WORD DMA_DESC_CH_CFG_DEST_SIZE(2) -#define DMA_DESC_CH_CFG_DEST_SIZE_NOINC DMA_DESC_CH_CFG_DEST_SIZE(3) - -#define DMA_DESC_CH_CFG_SRC_INC_SHIFT (26) -#define DMA_DESC_CH_CFG_SRC_INC_MASK \ - (0x3 << DMA_DESC_CH_CFG_SRC_INC_SHIFT) -#define DMA_DESC_CH_CFG_SRC_INC(v) \ - (((v) << DMA_DESC_CH_CFG_SRC_INC_SHIFT) & \ - DMA_DESC_CH_CFG_SRC_INC_MASK) -#define DMA_DESC_CH_CFG_SRC_INC_BYTE DMA_DESC_CH_CFG_SRC_INC(0) -#define DMA_DESC_CH_CFG_SRC_INC_HALFWORD DMA_DESC_CH_CFG_SRC_INC(1) -#define DMA_DESC_CH_CFG_SRC_INC_WORD DMA_DESC_CH_CFG_SRC_INC(2) -#define DMA_DESC_CH_CFG_SRC_INC_NOINC DMA_DESC_CH_CFG_SRC_INC(3) - -#define DMA_DESC_CH_CFG_SRC_SIZE_SHIFT (24) -#define DMA_DESC_CH_CFG_SRC_SIZE_MASK \ - (0x3 << DMA_DESC_CH_CFG_SRC_SIZE_SHIFT) -#define DMA_DESC_CH_CFG_SRC_SIZE(v) \ - (((v) << DMA_DESC_CH_CFG_SRC_SIZE_SHIFT) & \ - DMA_DESC_CH_CFG_SRC_SIZE_MASK) -#define DMA_DESC_CH_CFG_SRC_SIZE_BYTE DMA_DESC_CH_CFG_SRC_SIZE(0) -#define DMA_DESC_CH_CFG_SRC_SIZE_HALFWORD DMA_DESC_CH_CFG_SRC_SIZE(1) -#define DMA_DESC_CH_CFG_SRC_SIZE_WORD DMA_DESC_CH_CFG_SRC_SIZE(2) -#define DMA_DESC_CH_CFG_SRC_SIZE_NOINC DMA_DESC_CH_CFG_SRC_SIZE(3) - -#define DMA_DESC_CH_CFG_R_POWER_SHIFT (14) -#define DMA_DESC_CH_CFG_R_POWER_MASK \ - (0xF << DMA_DESC_CH_CFG_R_POWER_SHIFT) -#define DMA_DESC_CH_CFG_R_POWER(v) \ - (((v) << DMA_DESC_CH_CFG_R_POWER_SHIFT) & \ - DMA_DESC_CH_CFG_R_POWER_MASK) - -#define DMA_DESC_CH_CFG_CYCLE_CTRL_SHIFT (0) -#define DMA_DESC_CH_CFG_CYCLE_CTRL_MASK \ - (0x7 << DMA_DESC_CH_CFG_CYCLE_CTRL_SHIFT) -#define DMA_DESC_CH_CFG_CYCLE_CTRL(v) \ - (((v) << DMA_DESC_CH_CFG_CYCLE_CTRL_SHIFT) & \ - DMA_DESC_CH_CFG_CYCLE_CTRL_MASK) -#define DMA_DESC_CH_CFG_CYCLE_CTRL_INVALD \ - DMA_DESC_CH_CFG_CYCLE_CTRL(0) -#define DMA_DESC_CH_CFG_CYCLE_CTRL_BASIC \ - DMA_DESC_CH_CFG_CYCLE_CTRL(1) -#define DMA_DESC_CH_CFG_CYCLE_CTRL_AUTOREQUEST \ - DMA_DESC_CH_CFG_CYCLE_CTRL(2) -#define DMA_DESC_CH_CFG_CYCLE_CTRL_PINGPONG \ - DMA_DESC_CH_CFG_CYCLE_CTRL(3) -#define DMA_DESC_CH_CFG_CYCLE_CTRL_MEM_SCAT_GATH_PRIM \ - DMA_DESC_CH_CFG_CYCLE_CTRL(4) -#define DMA_DESC_CH_CFG_CYCLE_CTRL_MEM_SCAT_GATH_ALT \ - DMA_DESC_CH_CFG_CYCLE_CTRL(5) -#define DMA_DESC_CH_CFG_CYCLE_CTRL_PERIPH_SCAT_GATH_PRIM \ - DMA_DESC_CH_CFG_CYCLE_CTRL(6) -#define DMA_DESC_CH_CFG_CYCLE_CTRL_PERIPH_SCAT_GATH_ALT \ - DMA_DESC_CH_CFG_CYCLE_CTRL(7) - -#define DMA_DESC_CH_CFG_DEST_PROT_CTRL_SHIFT (21) -#define DMA_DESC_CH_CFG_DEST_PROT_CTRL_MASK \ - (0x7 << DMA_DESC_CH_CFG_DEST_PROT_CTRL_SHIFT) -#define DMA_DESC_CH_CFG_DEST_PROT_CTRL(v) \ - (((v) << DMA_DESC_CH_CFG_DEST_PROT_CTRL_SHIFT) & \ - DMA_DESC_CH_CFG_DEST_PROT_CTRL_MASK) - -#define DMA_DESC_CH_CFG_SRC_PROT_CTRL_SHIFT (18) -#define DMA_DESC_CH_CFG_SRC_PROT_CTRL_MASK \ - (0x7 << DMA_DESC_CH_CFG_SRC_PROT_CTRL_SHIFT) -#define DMA_DESC_CH_CFG_SRC_PROT_CTRL(v) \ - (((v) << DMA_DESC_CH_CFG_SRC_PROT_CTRL_SHIFT) & \ - DMA_DESC_CH_CFG_SRC_PROT_CTRL_SHIFT) - -#define DMA_DESC_CH_CFG_N_MINUS_1_SHIFT (4) -#define DMA_DESC_CH_CFG_N_MINUS_1_MASK \ - (0x3FF << DMA_DESC_CH_CFG_N_MINUS_1_SHIFT) -#define DMA_DESC_CH_CFG_N_MINUS_1(v) \ - (((v) << DMA_DESC_CH_CFG_N_MINUS_1_SHIFT) & \ - DMA_DESC_CH_CFG_N_MINUS_1_MASK) - -#define DMA_DESC_CH_CFG_NEXT_USEBURST (1 << 3) - -/* DMA Channel Descriptor in structure style */ -struct dma_chan_desc { - uint32_t src_data_end_ptr; - uint32_t dst_data_end_ptr; - uint32_t cfg; - uint32_t user_data; -} __attribute__((packed)); - -/** @defgroup dma_ch DMA Channel Number -@ingroup dma_defines - -@{*/ -enum dma_ch { - DMA_CH0 = 0, - DMA_CH1, - DMA_CH2, - DMA_CH3, - DMA_CH4, - DMA_CH5, - DMA_CH6, - DMA_CH7, - DMA_CH8, - DMA_CH9, - DMA_CH10, - DMA_CH11 -}; -/**@}*/ - -/* API version for {src, dest} * {size, inc} */ -enum dma_mem { - DMA_MEM_BYTE = 0, - DMA_MEM_HALF_WORD, - DMA_MEM_WORD, - DMA_MEM_NONE -}; - -/* API version of DMA_DESC_CH_CFG_CYCLE_CTRL_* */ -enum dma_mode { - DMA_MODE_INVALID = 0, - DMA_MODE_BASIC, - DMA_MODE_AUTO_REQUEST, - DMA_MODE_PING_PONG, - DMA_MODE_MEM_SCAT_GATH_PRIM, - DMA_MODE_MEM_SCAT_GATH_ALT, - DMA_MODE_PERIPH_SCAT_GATH_PRIM, - DMA_MODE_PERIPH_SCAT_GATH_ALT, -}; - -/* API version of DMA_DESC_CH_CFG_R_POWER() */ -enum dma_r_power { - DMA_R_POWER_1 = 0, - DMA_R_POWER_2, - DMA_R_POWER_4, - DMA_R_POWER_8, - DMA_R_POWER_16, - DMA_R_POWER_32, - DMA_R_POWER_64, - DMA_R_POWER_128, - DMA_R_POWER_256, - DMA_R_POWER_512, - DMA_R_POWER_1024 -}; - -BEGIN_DECLS - -void dma_enable(void); -void dma_disable(void); - -bool dma_get_wait_on_request_flag(enum dma_ch ch); - -/*bool dma_get_wait_flag(enum dma_ch ch);*/ - -void dma_enable_with_unprivileged_access(void); -void dma_enable_with_privileged_access(void); - -void dma_set_desc_address(uint32_t desc_base); - -void dma_generate_software_request(enum dma_ch ch); - -void dma_enable_burst_only(enum dma_ch ch); -void dma_enable_single_and_burst(enum dma_ch ch); - -void dma_enable_periph_request(enum dma_ch ch); -void dma_disable_periph_request(enum dma_ch ch); - -void dma_enable_channel(enum dma_ch ch); -void dma_disable_channel(enum dma_ch ch); - -void dma_disable_alternate_structure(enum dma_ch ch); -void dma_enable_alternate_structure(enum dma_ch ch); - -void dma_enable_priority(enum dma_ch ch); -void dma_disable_priority(enum dma_ch ch); - -bool dma_get_bus_error_flag(void); -void dma_clear_bus_error_flag(void); - -bool dma_get_request_flag(enum dma_ch ch); - -/*bool dma_get_single_request_flag(enum dma_ch ch);*/ - -bool dma_get_bus_error_interrupt_flag(void); -bool dma_get_done_interrupt_flag(enum dma_ch ch); - -void dma_set_bus_error_interrupt_flag(void); -void dma_set_done_interrupt_flag(enum dma_ch ch); - -void dma_clear_bus_error_interrupt_flag(void); -void dma_clear_done_interrupt_flag(enum dma_ch ch); - -void dma_enable_bus_error_interrupt(void); -void dma_disable_bus_error_interrupt(void); -void dma_enable_done_interrupt(enum dma_ch ch); -void dma_disable_done_interrupt(enum dma_ch ch); - -/* TODO: DMA_CTRL, DMA_RDS, DMA_LOOP0, DMA_LOOP1, DMA_RECT0 */ - -void dma_set_source(enum dma_ch ch, uint32_t source); -void dma_set_signal(enum dma_ch ch, uint32_t signal); - -void dma_channel_reset(enum dma_ch ch); - -void dma_set_loop_count(enum dma_ch ch, uint16_t count); -void dma_enable_loop(enum dma_ch ch); -void dma_disable_loop(enum dma_ch ch); - -/* descriptor convient function. (prefix "dma_desc_") */ -void dma_desc_set_dest_size(uint32_t desc_base, enum dma_ch ch, - enum dma_mem size); -void dma_desc_set_dest_inc(uint32_t desc_base, enum dma_ch ch, - enum dma_mem inc); -void dma_desc_set_src_size(uint32_t desc_base, enum dma_ch ch, - enum dma_mem size); -void dma_desc_set_src_inc(uint32_t desc_base, enum dma_ch ch, - enum dma_mem inc); - -void dma_desc_set_r_power(uint32_t desc_base, enum dma_ch ch, - enum dma_r_power r_power); - -void dma_desc_enable_next_useburst(uint32_t desc_base, enum dma_ch ch); -void dma_desc_disable_next_useburst(uint32_t desc_base, enum dma_ch ch); - -void dma_desc_set_count(uint32_t desc_base, enum dma_ch ch, uint16_t count); - -void dma_desc_set_user_data(uint32_t desc_base, enum dma_ch ch, - uint32_t user_data); -uint32_t dma_desc_get_user_data(uint32_t desc_base, enum dma_ch ch); - -void dma_desc_set_src_address(uint32_t desc_base, enum dma_ch ch, - uint32_t src); -void dma_desc_set_dest_address(uint32_t desc_base, enum dma_ch ch, - uint32_t dest); - -void dma_desc_set_mode(uint32_t desc_base, enum dma_ch ch, enum dma_mode mode); - -/* based on descriptor convient, macro are passing - * {DMA_CTRLBASE, CTRL_ALTCTRLBASE} as per naming */ -#define dma_set_dest_size(ch, size) \ - dma_desc_set_dest_size(DMA_CTRLBASE, ch, size) -#define dma_set_dest_inc(ch, inc) \ - dma_desc_set_dest_inc(DMA_CTRLBASE, ch, inc) -#define dma_set_src_size(ch, size) \ - dma_desc_set_src_size(DMA_CTRLBASE, ch, size) -#define dma_set_src_inc(ch, inc) \ - dma_desc_set_src_inc(DMA_CTRLBASE, ch, inc) - -#define dma_set_alt_dest_size(ch, size) \ - dma_desc_set_dest_size(DMA_ALTCTRLBASE, ch, size) -#define dma_set_alt_dest_inc(ch, inc) \ - dma_desc_set_dest_inc(DMA_ALTCTRLBASE, ch, inc) -#define dma_set_alt_src_size(ch, size) \ - dma_desc_set_src_size(DMA_ALTCTRLBASE, ch, size) -#define dma_set_alt_src_inc(ch, inc) \ - dma_desc_set_src_inc(DMA_ALTCTRLBASE, ch, inc) - -#define dma_set_r_power(ch, r_power) \ - dma_desc_set_r_power(DMA_CTRLBASE, ch, r_power) -#define dma_set_alt_r_power(ch, r_power) \ - dma_desc_set_r_power(DMA_ALTCTRLBASE, ch, r_power) - -#define dma_enable_next_useburst(ch) \ - dma_desc_enable_next_useburst(DMA_CTRLBASE, ch) -#define dma_disable_next_useburst(ch) \ - dma_desc_disable_next_useburst(DMA_CTRLBASE, ch) -#define dma_enable_alt_next_useburst(ch) \ - dma_desc_enable_alt_next_useburst(DMA_CTRLBASE, ch) -#define dma_disable_alt_next_useburst(ch) \ - dma_desc_disable_alt_next_useburst(DMA_CTRLBASE, ch) - -#define dma_set_count(ch, count) \ - dma_desc_set_count(DMA_CTRLBASE, ch, count) -#define dma_set_alt_count(ch, count) \ - dma_desc_set_count(DMA_ALTCTRLBASE, ch, count) - -#define dma_set_user_data(ch, user_data) \ - dma_desc_set_user_data(DMA_CTRLBASE, ch, user_data) -#define dma_set_alt_user_data(ch, user_data) \ - dma_desc_set_user_data(DMA_ALTCTRLBASE, ch, user_data) - -#define dma_get_user_data(ch) \ - dma_desc_get_user_data(DMA_CTRLBASE, ch) -#define dma_get_alt_user_data(ch) \ - dma_desc_get_user_data(DMA_ALTCTRLBASE, ch) - -#define dma_set_src_address(ch, src) \ - dma_desc_set_src_address(DMA_CTRLBASE, ch, src) -#define dma_set_alt_src_address(ch, src) \ - dma_desc_set_src_address(DMA_ALTCTRLBASE, ch, src) -#define dma_set_dest_address(ch, dest) \ - dma_desc_set_dest_address(DMA_CTRLBASE, ch, dest) -#define dma_set_alt_dest_address(ch, dest) \ - dma_desc_set_dest_address(DMA_ALTCTRLBASE, ch, dest) - -#define dma_set_mode(ch, mode) \ - dma_desc_set_mode(DMA_CTRLBASE, ch, mode) -#define dma_set_alt_mode(ch, mode) \ - dma_desc_set_mode(DMA_ALTCTRLBASE, ch, mode) - -END_DECLS +#include #endif - diff --git a/include/libopencm3/efm32/lg/emu.h b/include/libopencm3/efm32/lg/emu.h index 96e5ddd6..d104663b 100644 --- a/include/libopencm3/efm32/lg/emu.h +++ b/include/libopencm3/efm32/lg/emu.h @@ -1,7 +1,7 @@ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2015 Kuldeep Singh Dhaka + * Copyright (C) 2016 Bob Miller * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -17,173 +17,9 @@ * along with this library. If not, see . */ -#ifndef LIBOPENCM3_EFM32_EMU_H -#define LIBOPENCM3_EFM32_EMU_H +#ifndef LIBOPENCM3_EFM32_LG_EMU_H +#define LIBOPENCM3_EFM32_LG_EMU_H -#include -#include - -#define EMU_CTRL MMIO32(EMU_BASE + 0x000) -#define EMU_LOCK MMIO32(EMU_BASE + 0x008) -#define EMU_AUXCTRL MMIO32(EMU_BASE + 0x024) -#define EMU_EM4CONF MMIO32(EMU_BASE + 0x02C) -#define EMU_BUCTRL MMIO32(EMU_BASE + 0x030) -#define EMU_PWRCONF MMIO32(EMU_BASE + 0x034) -#define EMU_BUINACT MMIO32(EMU_BASE + 0x038) -#define EMU_BUACT MMIO32(EMU_BASE + 0x03C) -#define EMU_STATUS MMIO32(EMU_BASE + 0x040) -#define EMU_ROUTE MMIO32(EMU_BASE + 0x044) -#define EMU_IF MMIO32(EMU_BASE + 0x048) -#define EMU_IFS MMIO32(EMU_BASE + 0x04C) -#define EMU_IFC MMIO32(EMU_BASE + 0x050) -#define EMU_IEN MMIO32(EMU_BASE + 0x054) -#define EMU_BUBODBUVINCAL MMIO32(EMU_BASE + 0x058) -#define EMU_BUBODUNREGCAL MMIO32(EMU_BASE + 0x05C) - -/* EMU_CTRL */ -#define EMU_CTRL_EM4CTRL_SHIFT (2) -#define EMU_CTRL_EM4CTRL_MASK (0x3 << EMU_CTRL_EM4CTRL_SHIFT) -#define EMU_CTLR_EM4CTRL(v) \ - (((v) << EMU_CTRL_EM4CTRL_SHIFT) & EMU_CTRL_EM4CTRL_MASK) - -#define EMU_CTRL_EM2BLOCK (1 << 1) -#define EMU_CTRL_EMVREG (1 << 0) - -/* EMU_LOCK */ -#define EMU_LOCK_LOCKKEY_MASK (0xFFFF) -#define EMU_LOCK_LOCKKEY_LOCK (0) -#define EMU_LOCK_LOCKKEY_UNLOCK (0xADE8) - -/* EMU_AUXCTRL */ -#define EMU_AUXCTRL_HRCCLR (1 << 0) - -/* EMU_EM4CONF */ -#define EMU_EM4CONF_LOCKCONF (1 << 16) -#define EMU_EM4CONF_BUBODRSTDIS (1 << 4) - -#define EMU_EM4CONF_OSC_SHIFT (2) -#define EMU_EM4CONF_OSC_MASK (0x3 << EMU_EM4CONF_OSC_SHIFT) -#define EMU_EM4CONF_OSC(v) \ - (((v) << EMU_EM4CONF_OSC_SHIFT) & EMU_EM4CONF_OSC_MASK) -#define EMU_EM4CONF_OSC_ULFRCO EMU_EM4CONF_OSC(0) -#define EMU_EM4CONF_OSC_LFRCO EMU_EM4CONF_OSC(1) -#define EMU_EM4CONF_OSC_LFXO EMU_EM4CONF_OSC(2) - -#define EMU_EM4CONF_BURTCWU (1 << 1) -#define EMU_EM4CONF_VREGEN (1 << 0) - -/* EMU_BUCTRL */ -#define EMU_BUCTRL_PROBE_SHIFT (5) -#define EMU_BUCTRL_PROBE_MASK (0x3 << EMU_BUCTRL_PROBE_SHIFT) -#define EMU_BUCTRL_PROBE(v) \ - (((v) << EMU_BUCTRL_PROBE_SHIFT) & EMU_BUCTRL_PROBE_MASK) -#define EMU_BUCTRL_PROBE_DISABLE EMU_BUCTRL_PROBE(0) -#define EMU_BUCTRL_PROBE_VDDDREG EMU_BUCTRL_PROBE(1) -#define EMU_BUCTRL_PROBE_BUIN EMU_BUCTRL_PROBE(2) -#define EMU_BUCTRL_PROBE_BUOUT EMU_BUCTRL_PROBE(3) - -#define EMU_BUCTRL_BUMODEBODEN (1 << 3) -#define EMU_BUCTRL_BODCAL (1 << 2) -#define EMU_BUCTRL_STATEN (1 << 1) -#define EMU_BUCTRL_EN (1 << 0) - -/* EMU_PWRCONF */ -#define EMU_PWRCONF_PWRRES_SHIFT (3) -#define EMU_PWRCONF_PWRRES_MASK (0x3 << EMU_PWRCONF_PWRRES_SHIFT) -#define EMU_PWRCONF_PWRRES(v) \ - (((v) << EMU_PWRCONF_PWRRES_SHIFT) & EMU_PWRCONF_PWRRES_MASK) -#define EMU_PWRCONF_PWRRES_DISABLE EMU_PWRCONF_PWRRES(0) -#define EMU_PWRCONF_PWRRES_VDDDREG EMU_PWRCONF_PWRRES(1) -#define EMU_PWRCONF_PWRRES_BUIN EMU_PWRCONF_PWRRES(2) -#define EMU_PWRCONF_PWRRES_BUOUT EMU_PWRCONF_PWRRES(3) - -#define EMU_PWRCONF_VOUTSTRONG (1 << 2) -#define EMU_PWRCONF_VOUTMED (1 << 1) -#define EMU_PWRCONF_VOUTWEAK (1 << 0) - -/* EMU_BUINACT */ -#define EMU_BUINACT_PWRCON_SHIFT (5) -#define EMU_BUINACT_PWRCON_MASK (0x3 << EMU_BUINACT_PWRCON_SHIFT) -#define EMU_BUINACT_PWRCON(v) \ - (((v) << EMU_BUINACT_PWRCON_SHIFT) & EMU_BUINACT_PWRCON_MASK) -#define EMU_BUINACT_PWRCON_NONE EMU_BUINACT_PWRCON(0) -#define EMU_BUINACT_PWRCON_BUMAIN EMU_BUINACT_PWRCON(1) -#define EMU_BUINACT_PWRCON_MAINBU EMU_BUINACT_PWRCON(2) -#define EMU_BUINACT_PWRCON_NODIODE EMU_BUINACT_PWRCON(3) - -#define EMU_BUINACT_BUENRANGE_SHIFT (3) -#define EMU_BUINACT_BUENRANGE_MASK (0x3 << EMU_BUINACT_BUENRANGE_SHIFT) -#define EMU_BUINACT_BUENRANGE(v) \ - (((v) << EMU_BUINACT_BUENRANGE_SHIFT) & EMU_BUINACT_BUENRANGE_MASK) - -#define EMU_BUINACT_BUENTHRES_SHIFT (0) -#define EMU_BUINACT_BUENTHRES_MASK (0x7 << EMU_BUINACT_BUENTHRES_SHIFT) -#define EMU_BUINACT_BUENTHRES(v) \ - (((v) << EMU_BUINACT_BUENTHRES_SHIFT) & EMU_BUINACT_BUENTHRES_MASK) - -/* EMU_BUACT */ -#define EMU_BUACT_PWRCON_SHIFT (5) -#define EMU_BUACT_PWRCON_MASK (0x3 << EMU_BUACT_PWRCON_SHIFT) -#define EMU_BUACT_PWRCON(v) \ - (((v) << EMU_BUACT_PWRCON_SHIFT) & EMU_BUACT_PWRCON_MASK) -#define EMU_BUACT_PWRCON_NONE EMU_BUACT_PWRCON(0) -#define EMU_BUACT_PWRCON_BUMAIN EMU_BUACT_PWRCON(1) -#define EMU_BUACT_PWRCON_MAINBU EMU_BUACT_PWRCON(2) -#define EMU_BUACT_PWRCON_NODIODE EMU_BUACT_PWRCON(3) - -#define EMU_BUACT_BUEXRANGE_SHIFT (3) -#define EMU_BUACT_BUEXRANGE_MASK (0x3 << EMU_BUACT_BUEXRANGE_SHIFT) -#define EMU_BUACT_BUEXRANGE(v) \ - (((v) << EMU_BUACT_BUEXRANGE_SHIFT) & EMU_BUACT_BUEXRANGE_MASK) - -#define EMU_BUACT_BUEXTHRES_SHIFT (0) -#define EMU_BUACT_BUEXTHRES_MASK (0x7 << EMU_BUACT_BUEXTHRES_SHIFT) -#define EMU_BUACT_BUEXTHRES(v) \ - (((v) << EMU_BUACT_BUEXTHRES_SHIFT) & EMU_BUACT_BUEXTHRES_MASK) - -/* EMU_STATUS */ -#define EMU_STATUS_BURDY (1 << 0) - -/* EMU_ROUTE */ -#define EMU_ROUTE_BUVINPEN (1 << 0) - -/* EMU_IF */ -#define EMU_IF_BURDY (1 << 0) - -/* EMU_IFS */ -#define EMU_IFS_BURDY (1 << 0) - -/* EMU_IFC */ -#define EMU_IFC_BURDY (1 << 0) - -/* EMU_IEN */ -#define EMU_IEN_BURDY (1 << 0) - -/* EMU_BUBODBUVINCAL */ -#define EMU_BUBODBUVINCAL_RANGE_SHIFT (3) -#define EMU_BUBODBUVINCAL_RANGE_MASK (0x3 << EMU_BUBODBUVINCAL_RANGE_SHIFT) -#define EMU_BUBODBUVINCAL_RANGE(v) \ - (((v) << EMU_BUBODBUVINCAL_RANGE_SHIFT) & \ - EMU_BUBODBUVINCAL_RANGE_MASK) - -#define EMU_BUBODBUVINCAL_THRES_SHIFT (0) -#define EMU_BUBODBUVINCAL_THRES_MASK (0x7 << EMU_BUBODBUVINCAL_THRES_SHIFT) -#define EMU_BUBODBUVINCAL_THRES(v) \ - (((v) << EMU_BUBODBUVINCAL_THRES_SHIFT) & \ - EMU_BUBODBUVINCAL_THRES_MASK) - -/* EMU_BUBODUNREGCAL */ -#define EMU_BUBODUNREGCAL_RANGE_SHIFT (3) -#define EMU_BUBODUNREGCAL_RANGE_MASK (0x3 << EMU_BUBODUNREGCAL_RANGE_SHIFT) -#define EMU_BUBODUNREGCAL_RANGE(v) \ - (((v) << EMU_BUBODUNREGCAL_RANGE_SHIFT) & \ - EMU_BUBODUNREGCAL_RANGE_MASK) - -#define EMU_BUBODUNREGCAL_THRES_SHIFT (0) -#define EMU_BUBODUNREGCAL_THRES_MASK (0x7 << EMU_BUBODUNREGCAL_THRES_SHIFT) -#define EMU_BUBODUNREGCAL_THRES(v) \ - (((v) << EMU_BUBODUNREGCAL_THRES_SHIFT) & \ - EMU_BUBODUNREGCAL_THRES_MASK) +#include #endif - diff --git a/include/libopencm3/efm32/lg/gpio.h b/include/libopencm3/efm32/lg/gpio.h index 5218af66..71bd54f6 100644 --- a/include/libopencm3/efm32/lg/gpio.h +++ b/include/libopencm3/efm32/lg/gpio.h @@ -18,6 +18,6 @@ #ifndef LIBOPENCM3_GPIO_H #define LIBOPENCM3_GPIO_H -#include +#include #endif diff --git a/include/libopencm3/efm32/lg/i2c.h b/include/libopencm3/efm32/lg/i2c.h index 04ab83a0..6d34803d 100644 --- a/include/libopencm3/efm32/lg/i2c.h +++ b/include/libopencm3/efm32/lg/i2c.h @@ -1,7 +1,7 @@ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2015 Kuldeep Singh Dhaka + * Copyright (C) 2016 Bob Miller * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -17,253 +17,9 @@ * along with this library. If not, see . */ -#ifndef LIBOPENCM3_EFM32_I2C_H -#define LIBOPENCM3_EFM32_I2C_H +#ifndef LIBOPENCM3_EFM32_LG_I2C_H +#define LIBOPENCM3_EFM32_LG_I2C_H -#include -#include - -#define I2C_CTRL(base) MMIO32((base) + 0x000) -#define I2C_CMD(base) MMIO32((base) + 0x004) -#define I2C_STATE(base) MMIO32((base) + 0x008) -#define I2C_STATUS(base) MMIO32((base) + 0x00C) -#define I2C_CLKDIV(base) MMIO32((base) + 0x010) -#define I2C_SADDR(base) MMIO32((base) + 0x014) -#define I2C_SADDRMASK(base) MMIO32((base) + 0x018) -#define I2C_RXDATA(base) MMIO32((base) + 0x01C) -#define I2C_RXDATAP(base) MMIO32((base) + 0x020) -#define I2C_TXDATA(base) MMIO32((base) + 0x024) -#define I2C_IF(base) MMIO32((base) + 0x028) -#define I2C_IFS(base) MMIO32((base) + 0x02C) -#define I2C_IFC(base) MMIO32((base) + 0x030) -#define I2C_IEN(base) MMIO32((base) + 0x034) -#define I2C_ROUTE(base) MMIO32((base) + 0x038) - -/* I2C_CTRL */ -#define I2C_CTRL_CLTO_SHIFT (16) -#define I2C_CTRL_CLTO_MASK (0x7 << I2C_CTRL_CLTO_SHIFT) -#define I2C_CTRL_CLTO(v) \ - (((v) << I2C_CTRL_CLTO_SHIFT) & I2C_CTRL_CLTO_MASK) -#define I2C_CTRL_CLTO_OFF I2C_CTRL_CLTO(0) -#define I2C_CTRL_CLTO_40PCC I2C_CTRL_CLTO(1) -#define I2C_CTRL_CLTO_80PCC I2C_CTRL_CLTO(2) -#define I2C_CTRL_CLTO_160PCC I2C_CTRL_CLTO(3) -#define I2C_CTRL_CLTO_320PPC I2C_CTRL_CLTO(4) -#define I2C_CTRL_CLTO_1024PPC I2C_CTRL_CLTO(5) - -#define I2C_CTRL_GIBITO (1 << 15) - -#define I2C_CTRL_BTO_SHIFT (12) -#define I2C_CTRL_BTO_MASK (0x3 << I2C_CTRL_BTO_SHIFT) -#define I2C_CTRL_BTO(v) \ - (((v) << I2C_CTRL_BTO_SHIFT) & I2C_CTRL_BTO_MASK) -#define I2C_CTRL_BTO_OFF I2C_CTRL_BTO(0) -#define I2C_CTRL_BTO_40PCC I2C_CTRL_BTO(1) -#define I2C_CTRL_BTO_80PCC I2C_CTRL_BTO(2) -#define I2C_CTRL_BTO_160PCC I2C_CTRL_BTO(3) - -#define I2C_CTRL_CLHR_SHIFT (12) -#define I2C_CTRL_CLHR_MASK (0x3 << I2C_CTRL_CLHR_SHIFT) -#define I2C_CTRL_CLHR(v) \ - (((v) << I2C_CTRL_CLHR_SHIFT) & I2C_CTRL_CLHR_MASK) -#define I2C_CTRL_CLHR_STANDARD I2C_CTRL_CLHR(0) -#define I2C_CTRL_CLHR_ASYMMETRIC I2C_CTRL_CLHR(1) -#define I2C_CTRL_CLHR_FAST I2C_CTRL_CLHR(2) - -#define I2C_CTRL_GCAMEN (1 << 6) -#define I2C_CTRL_ARBDIS (1 << 5) -#define I2C_CTRL_AUTOSN (1 << 4) -#define I2C_CTRL_AUTOSE (1 << 3) -#define I2C_CTRL_AUTOACK (1 << 2) -#define I2C_CTRL_SLAVE (1 << 1) -#define I2C_CTRL_EN (1 << 0) - -/* I2C_CMD */ -#define I2C_CMD_CLEARPC (1 << 7) -#define I2C_CMD_CLEARTX (1 << 6) -#define I2C_CMD_ABORT (1 << 5) -#define I2C_CMD_CONT (1 << 4) -#define I2C_CMD_NACK (1 << 3) -#define I2C_CMD_ACK (1 << 2) -#define I2C_CMD_STOP (1 << 1) -#define I2C_CMD_START (1 << 0) - -/* I2C_STATE */ -#define I2C_STATE_STATE_SHIFT (5) -#define I2C_STATE_STATE_MASK (0x7 << I2C_STATE_STATE_SHIFT) -#define I2C_STATE_STATE(v) \ - (((v) << I2C_STATE_STATE_SHIFT) & I2C_STATE_STATE_MASK) -#define I2C_STATE_STATE_IDLE I2C_STATE_STATE(0) -#define I2C_STATE_STATE_WAIT I2C_STATE_STATE(1) -#define I2C_STATE_STATE_START I2C_STATE_STATE(2) -#define I2C_STATE_STATE_ADDR I2C_STATE_STATE(3) -#define I2C_STATE_STATE_ADDRACK I2C_STATE_STATE(4) -#define I2C_STATE_STATE_DATA I2C_STATE_STATE(5) -#define I2C_STATE_STATE_DATAACK I2C_STATE_STATE(6) - -#define I2C_STATE_BUSHOLD (1 << 4) -#define I2C_STATE_NACKED (1 << 3) -#define I2C_STATE_TRANSMITTER (1 << 2) -#define I2C_STATE_MASTER (1 << 1) -#define I2C_STATE_BUSY (1 << 0) - -/* I2C_STATUS */ -#define I2C_STATUS_RXDATAV (1 << 8) -#define I2C_STATUS_TXBL (1 << 7) -#define I2C_STATUS_TXC (1 << 6) -#define I2C_STATUS_PABORT (1 << 5) -#define I2C_STATUS_PCONT (1 << 4) -#define I2C_STATUS_PNACK (1 << 3) -#define I2C_STATUS_PACK (1 << 2) -#define I2C_STATUS_PSTOP (1 << 1) -#define I2C_STATUS_PSTART (1 << 0) - -/* I2C_CLKDIV */ -#define I2C_CLKDIV_DIV_SHIFT (0) -#define I2C_CLKDIV_DIV_MASK (0xFF << I2C_CLKDIV_DIV_SHIFT) -#define I2C_CLKDIV_DIV(v) \ - (((v) << I2C_CLKDIV_DIV_SHIFT) & I2C_CLKDIV_DIV_MASK) - -/* I2C_SADDR */ -#define I2C_SADDR_ADDR_SHIFT (0) -#define I2C_SADDR_ADDR_MASK (0xFF << I2C_SADDR_ADDR_SHIFT) -#define I2C_SADDR_ADDR(v) \ - (((v) << I2C_SADDR_ADDR_SHIFT) & I2C_SADDR_ADDR_MASK) - -/* I2C_SADDRMASK */ -#define I2C_SADDRMASK_MASK_SHIFT (0) -#define I2C_SADDRMASK_MASK_MASK (0xFF << I2C_SADDRMASK_MASK_SHIFT) -#define I2C_SADDRMASK_MASK(v) \ - (((v) << I2C_SADDRMASK_MASK_SHIFT) & I2C_SADDRMASK_MASK_MASK) - -/* I2C_IF */ -#define I2C_IF_SSTOP (1 << 16) -#define I2C_IF_CLTO (1 << 15) -#define I2C_IF_BITO (1 << 14) -#define I2C_IF_RXUF (1 << 13) -#define I2C_IF_TXOF (1 << 12) -#define I2C_IF_BUSHOLD (1 << 11) -#define I2C_IF_BUSERR (1 << 10) -#define I2C_IF_ARBLOST (1 << 9) -#define I2C_IF_MSTOP (1 << 8) -#define I2C_IF_NACK (1 << 7) -#define I2C_IF_ACK (1 << 6) -#define I2C_IF_RXDATAV (1 << 5) -#define I2C_IF_TXBL (1 << 4) -#define I2C_IF_TXC (1 << 3) -#define I2C_IF_ADDR (1 << 2) -#define I2C_IF_RSTART (1 << 1) -#define I2C_IF_START (1 << 0) - -/* I2C_IFS */ -#define I2C_IFS_SSTOP (1 << 16) -#define I2C_IFS_CLTO (1 << 15) -#define I2C_IFS_BITO (1 << 14) -#define I2C_IFS_RXUF (1 << 13) -#define I2C_IFS_TXOF (1 << 12) -#define I2C_IFS_BUSHOLD (1 << 11) -#define I2C_IFS_BUSERR (1 << 10) -#define I2C_IFS_ARBLOST (1 << 9) -#define I2C_IFS_MSTOP (1 << 8) -#define I2C_IFS_NACK (1 << 7) -#define I2C_IFS_ACK (1 << 6) -#define I2C_IFS_RXDATAV (1 << 5) -#define I2C_IFS_TXBL (1 << 4) -#define I2C_IFS_TXC (1 << 3) -#define I2C_IFS_ADDR (1 << 2) -#define I2C_IFS_RSTART (1 << 1) -#define I2C_IFS_START (1 << 0) - -/* I2C_IFC */ -#define I2C_IFC_SSTOP (1 << 16) -#define I2C_IFC_CLTO (1 << 15) -#define I2C_IFC_BITO (1 << 14) -#define I2C_IFC_RXUF (1 << 13) -#define I2C_IFC_TXOF (1 << 12) -#define I2C_IFC_BUSHOLD (1 << 11) -#define I2C_IFC_BUSERR (1 << 10) -#define I2C_IFC_ARBLOST (1 << 9) -#define I2C_IFC_MSTOP (1 << 8) -#define I2C_IFC_NACK (1 << 7) -#define I2C_IFC_ACK (1 << 6) -#define I2C_IFC_RXDATAV (1 << 5) -#define I2C_IFC_TXBL (1 << 4) -#define I2C_IFC_TXC (1 << 3) -#define I2C_IFC_ADDR (1 << 2) -#define I2C_IFC_RSTART (1 << 1) -#define I2C_IFC_START (1 << 0) - -/* I2C_IEN */ -#define I2C_IEN_SSTOP (1 << 16) -#define I2C_IEN_CLTO (1 << 15) -#define I2C_IEN_BITO (1 << 14) -#define I2C_IEN_RXUF (1 << 13) -#define I2C_IEN_TXOF (1 << 12) -#define I2C_IEN_BUSHOLD (1 << 11) -#define I2C_IEN_BUSERR (1 << 10) -#define I2C_IEN_ARBLOST (1 << 9) -#define I2C_IEN_MSTOP (1 << 8) -#define I2C_IEN_NACK (1 << 7) -#define I2C_IEN_ACK (1 << 6) -#define I2C_IEN_RXDATAV (1 << 5) -#define I2C_IEN_TXBL (1 << 4) -#define I2C_IEN_TXC (1 << 3) -#define I2C_IEN_ADDR (1 << 2) -#define I2C_IEN_RSTART (1 << 1) -#define I2C_IEN_START (1 << 0) - -/* I2C_ROUTE */ -#define I2C_ROUTE_LOCATION_SHIFT (8) -#define I2C_ROUTE_LOCATION_MASK (0x7 << I2C_ROUTE_LOCATION_SHIFT) -#define I2C_ROUTE_LOCATION(v) \ - (((v) << I2C_ROUTE_LOCATION_SHIFT) & I2C_ROUTE_LOCATION_MASK) -#define I2C_ROUTE_LOCATION_LOCx(x) I2C_ROUTE_LOCATION(x) -#define I2C_ROUTE_LOCATION_LOC0 I2C_ROUTE_LOCATION_LOCx(0) -#define I2C_ROUTE_LOCATION_LOC1 I2C_ROUTE_LOCATION_LOCx(1) -#define I2C_ROUTE_LOCATION_LOC2 I2C_ROUTE_LOCATION_LOCx(2) -#define I2C_ROUTE_LOCATION_LOC3 I2C_ROUTE_LOCATION_LOCx(3) -#define I2C_ROUTE_LOCATION_LOC4 I2C_ROUTE_LOCATION_LOCx(4) -#define I2C_ROUTE_LOCATION_LOC5 I2C_ROUTE_LOCATION_LOCx(5) -#define I2C_ROUTE_LOCATION_LOC6 I2C_ROUTE_LOCATION_LOCx(6) - -#define I2C_ROUTE_SCLPEN (1 << 1) -#define I2C_ROUTE_SDAPEN (1 << 0) - -/* I2C0 */ -#define I2C0 I2C0_BASE -#define I2C0_CTRL I2C_CTRL(base) -#define I2C0_CMD I2C_CMD(base) -#define I2C0_STATE I2C_STATE(base) -#define I2C0_STATUS I2C_STATUS(base) -#define I2C0_CLKDIV I2C_CLKDIV(base) -#define I2C0_SADDR I2C_SADDR(base) -#define I2C0_SADDRMASK I2C_SADDRMASK(base) -#define I2C0_RXDATA I2C_RXDATA(base) -#define I2C0_RXDATAP I2C_RXDATAP(base) -#define I2C0_TXDATA I2C_TXDATA(base) -#define I2C0_IF I2C_IF(base) -#define I2C0_IFS I2C_IFS(base) -#define I2C0_IFC I2C_IFC(base) -#define I2C0_IEN I2C_IEN(base) -#define I2C0_ROUTE I2C_ROUTE(base) - -/* I2C1 */ -#define I2C1 I2C1_BASE -#define I2C1_CTRL I2C_CTRL(base) -#define I2C1_CMD I2C_CMD(base) -#define I2C1_STATE I2C_STATE(base) -#define I2C1_STATUS I2C_STATUS(base) -#define I2C1_CLKDIV I2C_CLKDIV(base) -#define I2C1_SADDR I2C_SADDR(base) -#define I2C1_SADDRMASK I2C_SADDRMASK(base) -#define I2C1_RXDATA I2C_RXDATA(base) -#define I2C1_RXDATAP I2C_RXDATAP(base) -#define I2C1_TXDATA I2C_TXDATA(base) -#define I2C1_IF I2C_IF(base) -#define I2C1_IFS I2C_IFS(base) -#define I2C1_IFC I2C_IFC(base) -#define I2C1_IEN I2C_IEN(base) -#define I2C1_ROUTE I2C_ROUTE(base) +#include #endif - diff --git a/include/libopencm3/efm32/lg/letimer.h b/include/libopencm3/efm32/lg/letimer.h index 3526c6ef..40c283f4 100644 --- a/include/libopencm3/efm32/lg/letimer.h +++ b/include/libopencm3/efm32/lg/letimer.h @@ -1,7 +1,7 @@ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2015 Kuldeep Singh Dhaka + * Copyright (C) 2016 Bob Miller * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -17,149 +17,9 @@ * along with this library. If not, see . */ -#ifndef LIBOPENCM3_EFM32_LETIMER_H -#define LIBOPENCM3_EFM32_LETIMER_H +#ifndef LIBOPENCM3_EFM32_LG_LETIMER_H +#define LIBOPENCM3_EFM32_LG_LETIMER_H -#include -#include - -#define LETIMER_CTRL(base) ((base) + 0x000) -#define LETIMER_CMD(base) ((base) + 0x004) -#define LETIMER_STATUS(base) ((base) + 0x008) -#define LETIMER_CNT(base) ((base) + 0x00C) -#define LETIMER_COMP0(base) ((base) + 0x010) -#define LETIMER_COMP1(base) ((base) + 0x014) -#define LETIMER_REP0(base) ((base) + 0x018) -#define LETIMER_REP1(base) ((base) + 0x01C) -#define LETIMER_IF(base) ((base) + 0x020) -#define LETIMER_IFS(base) ((base) + 0x024) -#define LETIMER_IFC(base) ((base) + 0x028) -#define LETIMER_IEN(base) ((base) + 0x02C) -#define LETIMER_FREEZE(base) ((base) + 0x030) -#define LETIMER_SYNCBUSY(base) ((base) + 0x034) -#define LETIMER_ROUTE(base) ((base) + 0x040) - -/* LETIMER_CTRL */ -#define LETIMER_CTRL_DEBUG (1 << 12) -#define LETIMER_CTRL_RTCC1TEN (1 << 11) -#define LETIMER_CTRL_RTCC0TEN (1 << 10) -#define LETIMER_CTRL_COMP0TOP (1 << 9) -#define LETIMER_CTRL_BUFTOP (1 << 8) -#define LETIMER_CTRL_OPOL1 (1 << 7) -#define LETIMER_CTRL_OPOL0 (1 << 6) - -#define LETIMER_CTRL_UFOA1_SHIFT (4) -#define LETIMER_CTRL_UFOA1_MASK (0x3 << LETIMER_CTRL_UFOA1_SHIFT) -#define LETIMER_CTRL_UFOA1(v) \ - (((v) << LETIMER_CTRL_UFOA1_SHIFT) & LETIMER_CTRL_UFOA1_MASK) -#define LETIMER_CTRL_UFOA1_NONE LETIMER_CTRL_UFOA1(0) -#define LETIMER_CTRL_UFOA1_TOGGLE LETIMER_CTRL_UFOA1(1) -#define LETIMER_CTRL_UFOA1_PULSE LETIMER_CTRL_UFOA1(2) -#define LETIMER_CTRL_UFOA1_PWM LETIMER_CTRL_UFOA1(3) - -#define LETIMER_CTRL_UFOA0_SHIFT (2) -#define LETIMER_CTRL_UFOA0_MASK (0x3 << LETIMER_CTRL_UFOA0_SHIFT) -#define LETIMER_CTRL_UFOA0(v) \ - (((v) << LETIMER_CTRL_UFOA0_SHIFT) & LETIMER_CTRL_UFOA0_MASK) -#define LETIMER_CTRL_UFOA0_NONE LETIMER_CTRL_UFOA0(0) -#define LETIMER_CTRL_UFOA0_TOGGLE LETIMER_CTRL_UFOA0(1) -#define LETIMER_CTRL_UFOA0_PULSE LETIMER_CTRL_UFOA0(2) -#define LETIMER_CTRL_UFOA0_PWM LETIMER_CTRL_UFOA0(3) - -#define LETIMER_CTRL_REPMODE_SHIFT (2) -#define LETIMER_CTRL_REPMODE_MASK (0x3 << LETIMER_CTRL_REPMODE_SHIFT) -#define LETIMER_CTRL_REPMODE(v) \ - (((v) << LETIMER_CTRL_REPMODE_SHIFT) & LETIMER_CTRL_REPMODE_MASK) -#define LETIMER_CTRL_REPMODE_FREE LETIMER_CTRL_REPMODE(0) -#define LETIMER_CTRL_REPMODE_ONESHOT LETIMER_CTRL_REPMODE(1) -#define LETIMER_CTRL_REPMODE_BUFFERED LETIMER_CTRL_REPMODE(2) -#define LETIMER_CTRL_REPMODE_DOUBLE LETIMER_CTRL_REPMODE(3) -#define LETIMER_CTRL_REPMODE_ONE_SHOT LETIMER_CTRL_REPMODE_ONESHOT - -/* LETIMER_CMD */ -#define LETIMER_CMD_CTO1 (1 << 4) -#define LETIMER_CMD_CTO0 (1 << 3) -#define LETIMER_CMD_CLEAR (1 << 2) -#define LETIMER_CMD_STOP (1 << 1) -#define LETIMER_CMD_START (1 << 0) - -/* LETIMER_STATUS */ -#define LETIMER_STATUS_RUNNING (1 << 0) - -/* LETIMER_IF */ -#define LETIMER_IF_REP1 (1 << 4) -#define LETIMER_IF_REP0 (1 << 3) -#define LETIMER_IF_UF (1 << 2) -#define LETIMER_IF_COMP1 (1 << 1) -#define LETIMER_IF_COMP0 (1 << 0) - -/* LETIMER_IFS */ -#define LETIMER_IFS_REP1 (1 << 4) -#define LETIMER_IFS_REP0 (1 << 3) -#define LETIMER_IFS_UF (1 << 2) -#define LETIMER_IFS_COMP1 (1 << 1) -#define LETIMER_IFS_COMP0 (1 << 0) - -/* LETIMER_IFC */ -#define LETIMER_IFC_REP1 (1 << 4) -#define LETIMER_IFC_REP0 (1 << 3) -#define LETIMER_IFC_UF (1 << 2) -#define LETIMER_IFC_COMP1 (1 << 1) -#define LETIMER_IFC_COMP0 (1 << 0) - -/* LETIMER_IFE */ -#define LETIMER_IFE_REP1 (1 << 4) -#define LETIMER_IFE_REP0 (1 << 3) -#define LETIMER_IFE_UF (1 << 2) -#define LETIMER_IFE_COMP1 (1 << 1) -#define LETIMER_IFE_COMP0 (1 << 0) - -/* LETIMER_FREEZE */ -#define LETIMER_FREEZE_REGFREEZE (1 << 0) - -/* LETIMER_SYNCBUSY */ -#define LETIMER_SYNCBUSY_REP1 (1 << 5) -#define LETIMER_SYNCBUSY_REP0 (1 << 4) -#define LETIMER_SYNCBUSY_COMP1 (1 << 3) -#define LETIMER_SYNCBUSY_COMP0 (1 << 2) -#define LETIMER_SYNCBUSY_CMD (1 << 1) -#define LETIMER_SYNCBUSY_CTRL (1 << 0) - -/* LETIMER_ROUTE */ -#define LETIMER_ROUTE_LOCATION_SHIFT (8) -#define LETIMER_ROUTE_LOCATION_MASK (0x7 << LETIMER_ROUTE_LOCATION_SHIFT) -#define LETIMER_ROUTE_LOCATION(v) \ - (((v) << LETIMER_ROUTE_LOCATION_SHIFT) & LETIMER_ROUTE_LOCATION_MASK) -#define LETIMER_ROUTE_LOCATION_LOCx(x) LETIMER_ROUTE_LOCATION(x) -#define LETIMER_ROUTE_LOCATION_LOC0 LETIMER_ROUTE_LOCATION_LOCx(0) -#define LETIMER_ROUTE_LOCATION_LOC1 LETIMER_ROUTE_LOCATION_LOCx(1) -#define LETIMER_ROUTE_LOCATION_LOC2 LETIMER_ROUTE_LOCATION_LOCx(2) -#define LETIMER_ROUTE_LOCATION_LOC3 LETIMER_ROUTE_LOCATION_LOCx(3) -#define LETIMER_ROUTE_LOCATION_LOC4 LETIMER_ROUTE_LOCATION_LOCx(4) -#define LETIMER_ROUTE_LOCATION_LOC5 LETIMER_ROUTE_LOCATION_LOCx(5) -#define LETIMER_ROUTE_LOCATION_LOC6 LETIMER_ROUTE_LOCATION_LOCx(6) -#define LETIMER_ROUTE_LOCATION_LOC7 LETIMER_ROUTE_LOCATION_LOCx(7) - -#define LETIMER_ROUTE_OUT1PEN (1 << 1) -#define LETIMER_ROUTE_OUT0PEN (1 << 0) - -/* LETIMER0 */ -#define LETIMER0 LETIMER0_BASE -#define LETIMER0_CTRL LETIMER_CTRL(LETIMER0) -#define LETIMER0_CMD LETIMER_CMD(LETIMER0) -#define LETIMER0_STATUS LETIMER_STATUS(LETIMER0) -#define LETIMER0_CNT LETIMER_CNT(LETIMER0) -#define LETIMER0_COMP0 LETIMER_COMP0(LETIMER0) -#define LETIMER0_COMP1 LETIMER_COMP1(LETIMER0) -#define LETIMER0_REP0 LETIMER_REP0(LETIMER0) -#define LETIMER0_REP1 LETIMER_REP1(LETIMER0) -#define LETIMER0_IF LETIMER_IF(LETIMER0) -#define LETIMER0_IFS LETIMER_IFS(LETIMER0) -#define LETIMER0_IFC LETIMER_IFC(LETIMER0) -#define LETIMER0_IEN LETIMER_IEN(LETIMER0) -#define LETIMER0_FREEZE LETIMER_FREEZE(LETIMER0) -#define LETIMER0_SYNCBUSY LETIMER_SYNCBUSY(LETIMER0) -#define LETIMER0_ROUTE LETIMER_ROUTE(LETIMER0) +#include #endif - diff --git a/include/libopencm3/efm32/lg/msc.h b/include/libopencm3/efm32/lg/msc.h index 168be572..83b99fdf 100644 --- a/include/libopencm3/efm32/lg/msc.h +++ b/include/libopencm3/efm32/lg/msc.h @@ -1,7 +1,7 @@ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2015 Kuldeep Singh Dhaka + * Copyright (C) 2016 Bob Miller * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -17,138 +17,9 @@ * along with this library. If not, see . */ -#ifndef LIBOPENCM3_EFM32_MSC_H -#define LIBOPENCM3_EFM32_MSC_H +#ifndef LIBOPENCM3_EFM32_LG_MSC_H +#define LIBOPENCM3_EFM32_LG_MSC_H -#include -#include - -#define MSC_CTRL MMIO32(MSC_BASE + 0x000) -#define MSC_READCTRL MMIO32(MSC_BASE + 0x004) -#define MSC_WRITECTRL MMIO32(MSC_BASE + 0x008) -#define MSC_WRITECMD MMIO32(MSC_BASE + 0x00C) -#define MSC_ADDRB MMIO32(MSC_BASE + 0x010) -#define MSC_WDATA MMIO32(MSC_BASE + 0x018) -#define MSC_STATUS MMIO32(MSC_BASE + 0x01C) -#define MSC_IF MMIO32(MSC_BASE + 0x02C) -#define MSC_IFS MMIO32(MSC_BASE + 0x030) -#define MSC_IFC MMIO32(MSC_BASE + 0x034) -#define MSC_IEN MMIO32(MSC_BASE + 0x038) -#define MSC_LOCK MMIO32(MSC_BASE + 0x03C) -#define MSC_CMD MMIO32(MSC_BASE + 0x040) -#define MSC_CACHEHITS MMIO32(MSC_BASE + 0x044) -#define MSC_CACHEMISSES MMIO32(MSC_BASE + 0x048) -#define MSC_TIMEBASE MMIO32(MSC_BASE + 0x050) -#define MSC_MASSLOCK MMIO32(MSC_BASE + 0x054) - -/* MSC_CTRL */ -#define MSC_CTRL_BUSFAULT (1 << 0) - -/* MSC_READCTRL */ -#define MSC_READCTRL_BUSSTRATEGY_SHIFT (16) -#define MSC_READCTRL_BUSSTRATEGY_MASK \ - (0x3 << MSC_READCTRL_BUSSTRATEGY_SHIFT) -#define MSC_READCTRL_BUSSTRATEGY(v) \ - (((v) << MSC_READCTRL_BUSSTRATEGY_SHIFT) & \ - MSC_READCTRL_BUSSTRATEGY_MASK) - -#define MSC_READCTRL_BUSSTRATEGY_CPU MSC_READCTRL_BUSSTRATEGY(0) -#define MSC_READCTRL_BUSSTRATEGY_DMA MSC_READCTRL_BUSSTRATEGY(1) -#define MSC_READCTRL_BUSSTRATEGY_DMAEM1 MSC_READCTRL_BUSSTRATEGY(2) -#define MSC_READCTRL_BUSSTRATEGY_NONE MSC_READCTRL_BUSSTRATEGY(3) - -#define MSC_READCTRL_RAMCEN (1 << 7) -#define MSC_READCTRL_EBICDIS (1 << 6) -#define MSC_READCTRL_ICCDIS (1 << 5) -#define MSC_READCTRL_AIDIS (1 << 4) -#define MSC_READCTRL_IFCDIS (1 << 3) - -#define MSC_READCTRL_MODE_SHIFT (0) -#define MSC_READCTRL_MODE_MASK (0x7 << MSC_READCTRL_MODE_SHIFT) -#define MSC_READCTRL_MODE(v) \ - (((v) << MSC_READCTRL_MODE_SHIFT) & MSC_READCTRL_MODE_MASK) -#define MSC_READCTRL_MODE_WS0 MSC_READCTRL_MODE(0) -#define MSC_READCTRL_MODE_WS1 MSC_READCTRL_MODE(1) -#define MSC_READCTRL_MODE_WS0SCBTP MSC_READCTRL_MODE(2) -#define MSC_READCTRL_MODE_WS1SCBTP MSC_READCTRL_MODE(3) -#define MSC_READCTRL_MODE_WS2 MSC_READCTRL_MODE(4) -#define MSC_READCTRL_MODE_WS2SCBTP MSC_READCTRL_MODE(5) - -/* MSC_WRITECTRL */ -#define MSC_WRITECTRL_IRQERASEABORT (1 << 1) -#define MSC_WRITECTRL_WREN (1 << 0) - -/* MSC_WRITECMD */ -#define MSC_WRITECMD_CLEARWDATA (1 << 12) -#define MSC_WRITECMD_ERASEMAIN0 (1 << 8) -#define MSC_WRITECMD_ERASEABORT (1 << 5) -#define MSC_WRITECMD_WRITETRIG (1 << 4) -#define MSC_WRITECMD_WRITEONCE (1 << 3) -#define MSC_WRITECMD_WRITEEND (1 << 2) -#define MSC_WRITECMD_ERASEPAGE (1 << 1) -#define MSC_WRITECMD_LADDRIM (1 << 0) - -/* MSC_STATUS */ -#define MSC_STATUS_PCRUNNING (1 << 6) -#define MSC_STATUS_ERASEABORTED (1 << 5) -#define MSC_STATUS_WORDTIMEOUT (1 << 4) -#define MSC_STATUS_WDATAREADY (1 << 3) -#define MSC_STATUS_INVADDR (1 << 2) -#define MSC_STATUS_LOCKED (1 << 1) -#define MSC_STATUS_BUSY (1 << 0) - -/* MSC_IF */ -#define MSC_IF_CMOF (1 << 3) -#define MSC_IF_CHOF (1 << 2) -#define MSC_IF_WRITE (1 << 1) -#define MSC_IF_ERASE (1 << 0) - -/* MSC_IFS */ -#define MSC_IFS_CMOF (1 << 3) -#define MSC_IFS_CHOF (1 << 2) -#define MSC_IFS_WRITE (1 << 1) -#define MSC_IFS_ERASE (1 << 0) - -/* MSC_IFC */ -#define MSC_IFC_CMOF (1 << 3) -#define MSC_IFC_CHOF (1 << 2) -#define MSC_IFC_WRITE (1 << 1) -#define MSC_IFC_ERASE (1 << 0) - -/* MSC_*IEN */ -#define MSC_IEN_CMOF (1 << 3) -#define MSC_IEN_CHOF (1 << 2) -#define MSC_IEN_WRITE (1 << 1) -#define MSC_IEN_ERASE (1 << 0) - -/* MSC_LOCK */ -#define MSC_LOCK_LOCKKEY_SHIFT (0) -#define MSC_LOCK_LOCKKEY(v) ((v) << MSC_LOCK_LOCKKEY_SHIFT) -#define MSC_LOCK_LOCKKEY_UNLOCKED MSC_LOCK_LOCKKEY(0) -#define MSC_LOCK_LOCKKEY_LOCKED MSC_LOCK_LOCKKEY(1) -#define MSC_LOCK_LOCKKEY_LOCK MSC_LOCK_LOCKKEY(0) -#define MSC_LOCK_LOCKKEY_UNLOCK MSC_LOCK_LOCKKEY(0x1B71) - -/* MSC_CMD */ -#define MSC_CMD_STOPPC (1 << 2) -#define MSC_CMD_STARTPC (1 << 1) -#define MSC_CMD_INVCACHE (1 << 0) - -/* MSC_TIMEBASE */ -#define MSC_TIMEBASE_PERIOD (1 << 16) - -#define MSC_TIMEBASE_BASE_SHIFT (0) -#define MSC_TIMEBASE_BASE_MASK (0x3F << MSC_TIMEBASE_BASE_SHIFT) -#define MSC_TIMEBASE_BASE(v) \ - (((v) << MSC_TIMEBASE_BASE_SHIFT) & MSC_TIMEBASE_BASE_MASK) - -/* MSC_MASSLOCK */ -#define MSC_MASSLOCK_LOCKKEY_SHIFT (0) -#define MSC_MASSLOCK_LOCKKEY(v) ((v) << MSC_MASSLOCK_LOCKKEY_SHIFT) -#define MSC_MASSLOCK_LOCKKEY_UNLOCKED MSC_MASSLOCK_LOCKKEY(0) -#define MSC_MASSLOCK_LOCKKEY_LOCKED MSC_MASSLOCK_LOCKKEY(1) -#define MSC_MASSLOCK_LOCKKEY_LOCK MSC_MASSLOCK_LOCKKEY(0) -#define MSC_MASSLOCK_LOCKKEY_UNLOCK MSC_MASSLOCK_LOCKKEY(0x631A) +#include #endif - diff --git a/include/libopencm3/efm32/lg/opamp.h b/include/libopencm3/efm32/lg/opamp.h index 29829098..fe2a1b14 100644 --- a/include/libopencm3/efm32/lg/opamp.h +++ b/include/libopencm3/efm32/lg/opamp.h @@ -1,7 +1,7 @@ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2015 Kuldeep Singh Dhaka + * Copyright (C) 2016 Bob Miller * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -17,5 +17,9 @@ * along with this library. If not, see . */ -/* OpAmp register are in dac.h */ -#include +#ifndef LIBOPENCM3_EFM32_LG_OPAMP_H +#define LIBOPENCM3_EFM32_LG_OPAMP_H + +#include + +#endif diff --git a/include/libopencm3/efm32/lg/prs.h b/include/libopencm3/efm32/lg/prs.h index d5560ba0..a2469457 100644 --- a/include/libopencm3/efm32/lg/prs.h +++ b/include/libopencm3/efm32/lg/prs.h @@ -1,7 +1,7 @@ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2015 Kuldeep Singh Dhaka + * Copyright (C) 2016 Bob Miller * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -17,347 +17,9 @@ * along with this library. If not, see . */ -#ifndef LIBOPENCM3_EFM32_PRS_H -#define LIBOPENCM3_EFM32_PRS_H +#ifndef LIBOPENCM3_EFM32_LG_PRS_H +#define LIBOPENCM3_EFM32_LG_PRS_H -#include -#include - -#define PRS_SWPULSE MMIO32(PRS_BASE + 0x000) -#define PRS_SWLEVEL MMIO32(PRS_BASE + 0x004) -#define PRS_ROUTE MMIO32(PRS_BASE + 0x008) -#define PRS_CHx_CTRL(x) MMIO32(PRS_BASE + 0x010 + (0x004 * (x))) -#define PRS_CH0_CTRL PRS_CHx_CTRL(0) -#define PRS_CH1_CTRL PRS_CHx_CTRL(1) -#define PRS_CH2_CTRL PRS_CHx_CTRL(2) -#define PRS_CH3_CTRL PRS_CHx_CTRL(3) -#define PRS_CH4_CTRL PRS_CHx_CTRL(4) -#define PRS_CH5_CTRL PRS_CHx_CTRL(5) -#define PRS_CH6_CTRL PRS_CHx_CTRL(6) -#define PRS_CH7_CTRL PRS_CHx_CTRL(71) -#define PRS_CH8_CTRL PRS_CHx_CTRL(8) -#define PRS_CH9_CTRL PRS_CHx_CTRL(9) -#define PRS_CH10_CTRL PRS_CHx_CTRL(10) -#define PRS_CH11_CTRL PRS_CHx_CTRL(11) - -/* PRS_SWPULSE */ -#define PRS_SWPULSE_CHxPULSE(x) (1 << (x)) -#define PRS_SWPULSE_CH0PULSE PRS_SWPULSE_CHxPULSE(0) -#define PRS_SWPULSE_CH1PULSE PRS_SWPULSE_CHxPULSE(1) -#define PRS_SWPULSE_CH2PULSE PRS_SWPULSE_CHxPULSE(2) -#define PRS_SWPULSE_CH3PULSE PRS_SWPULSE_CHxPULSE(3) -#define PRS_SWPULSE_CH4PULSE PRS_SWPULSE_CHxPULSE(4) -#define PRS_SWPULSE_CH5PULSE PRS_SWPULSE_CHxPULSE(5) -#define PRS_SWPULSE_CH6PULSE PRS_SWPULSE_CHxPULSE(6) -#define PRS_SWPULSE_CH7PULSE PRS_SWPULSE_CHxPULSE(7) -#define PRS_SWPULSE_CH8PULSE PRS_SWPULSE_CHxPULSE(8) -#define PRS_SWPULSE_CH9PULSE PRS_SWPULSE_CHxPULSE(9) -#define PRS_SWPULSE_CH10PULSE PRS_SWPULSE_CHxPULSE(10) -#define PRS_SWPULSE_CH11PULSE PRS_SWPULSE_CHxPULSE(11) - -/* PRS_SWLEVEL */ -#define PRS_SWLEVEL_CHxLEVEL(x) (1 << (x)) -#define PRS_SWLEVEL_CH0LEVEL PRS_SWLEVEL_CHxLEVEL(0) -#define PRS_SWLEVEL_CH1LEVEL PRS_SWLEVEL_CHxLEVEL(1) -#define PRS_SWLEVEL_CH2LEVEL PRS_SWLEVEL_CHxLEVEL(2) -#define PRS_SWLEVEL_CH3LEVEL PRS_SWLEVEL_CHxLEVEL(3) -#define PRS_SWLEVEL_CH4LEVEL PRS_SWLEVEL_CHxLEVEL(4) -#define PRS_SWLEVEL_CH5LEVEL PRS_SWLEVEL_CHxLEVEL(5) -#define PRS_SWLEVEL_CH6LEVEL PRS_SWLEVEL_CHxLEVEL(6) -#define PRS_SWLEVEL_CH7LEVEL PRS_SWLEVEL_CHxLEVEL(7) -#define PRS_SWLEVEL_CH8LEVEL PRS_SWLEVEL_CHxLEVEL(8) -#define PRS_SWLEVEL_CH9LEVEL PRS_SWLEVEL_CHxLEVEL(9) -#define PRS_SWLEVEL_CH10LEVEL PRS_SWLEVEL_CHxLEVEL(10) -#define PRS_SWLEVEL_CH11LEVEL PRS_SWLEVEL_CHxLEVEL(11) - -/* PRS_ROUTE */ -#define PRS_ROUTE_LOCATION_SHIFT (8) -#define PRS_ROUTE_LOCATION_MASK (0x7 << PRS_ROUTE_LOCATION_SHIFT) -#define PRS_ROUTE_LOCATION(v) \ - (((v) << PRS_ROUTE_LOCATION_SHIFT) & PRS_ROUTE_LOCATION_MASK) -#define PRS_ROUTE_LOCATION_LOCx(x) PRS_ROUTE_LOCATION(x) -#define PRS_ROUTE_LOCATION_LOC0 PRS_ROUTE_LOCATION_LOCx(0) -#define PRS_ROUTE_LOCATION_LOC1 PRS_ROUTE_LOCATION_LOCx(1) - -#define PRS_ROUTE_CHxPEN(x) (1 << (x)) -#define PRS_ROUTE_CH3PEN PRS_ROUTE_CHxPEN(3) -#define PRS_ROUTE_CH2PEN PRS_ROUTE_CHxPEN(2) -#define PRS_ROUTE_CH1PEN PRS_ROUTE_CHxPEN(1) -#define PRS_ROUTE_CH0PEN PRS_ROUTE_CHxPEN(0) - -/* PRS_CHx_CTRL */ -#define PRS_CH_CTRL_ASYNC (1 << 28) - -#define PRS_CH_CTRL_EDSEL_SHIFT (24) -#define PRS_CH_CTRL_EDSEL_MASK (0x3 << PRS_CH_CTRL_EDSEL_SHIFT) -#define PRS_CH_CTRL_EDSEL_OFF (0 << PRS_CH_CTRL_EDSEL_SHIFT) -#define PRS_CH_CTRL_EDSEL_POSEDGE (1 << PRS_CH_CTRL_EDSEL_SHIFT) -#define PRS_CH_CTRL_EDSEL_NEGEDGE (2 << PRS_CH_CTRL_EDSEL_SHIFT) -#define PRS_CH_CTRL_EDSEL_BOTHEDGES (3 << PRS_CH_CTRL_EDSEL_SHIFT) - -#define PRS_CH_CTRL_SOURCESEL_SHIFT (16) -#define PRS_CH_CTRL_SOURCESEL_MASK (0x3F << PRS_CH_CTRL_SOURCESEL_SHIFT) -#define PRS_CH_CTRL_SOURCESEL(v) \ - (((v) << PRS_CH_CTRL_SOURCESEL_SHIFT) & PRS_CH_CTRL_SOURCESEL_MASK) -#define PRS_CH_CTRL_SOURCESEL_NONE PRS_CH_CTRL_SOURCESEL(0b000000) -#define PRS_CH_CTRL_SOURCESEL_VCMP PRS_CH_CTRL_SOURCESEL(0b000001) -#define PRS_CH_CTRL_SOURCESEL_ACMP0 PRS_CH_CTRL_SOURCESEL(0b000010) -#define PRS_CH_CTRL_SOURCESEL_ACMP1 PRS_CH_CTRL_SOURCESEL(0b000011) -#define PRS_CH_CTRL_SOURCESEL_DAC0 PRS_CH_CTRL_SOURCESEL(0b000110) -#define PRS_CH_CTRL_SOURCESEL_ADC0 PRS_CH_CTRL_SOURCESEL(0b001000) -#define PRS_CH_CTRL_SOURCESEL_USART0 PRS_CH_CTRL_SOURCESEL(0b010000) -#define PRS_CH_CTRL_SOURCESEL_USART1 PRS_CH_CTRL_SOURCESEL(0b010001) -#define PRS_CH_CTRL_SOURCESEL_USART2 PRS_CH_CTRL_SOURCESEL(0b010010) -#define PRS_CH_CTRL_SOURCESEL_TIMER0 PRS_CH_CTRL_SOURCESEL(0b011100) -#define PRS_CH_CTRL_SOURCESEL_TIMER1 PRS_CH_CTRL_SOURCESEL(0b011101) -#define PRS_CH_CTRL_SOURCESEL_TIMER2 PRS_CH_CTRL_SOURCESEL(0b011110) -#define PRS_CH_CTRL_SOURCESEL_TIMER3 PRS_CH_CTRL_SOURCESEL(0b011111) -#define PRS_CH_CTRL_SOURCESEL_USB PRS_CH_CTRL_SOURCESEL(0b100100) -#define PRS_CH_CTRL_SOURCESEL_RTC PRS_CH_CTRL_SOURCESEL(0b101000) -#define PRS_CH_CTRL_SOURCESEL_UART0 PRS_CH_CTRL_SOURCESEL(0b101001) -#define PRS_CH_CTRL_SOURCESEL_UART1 PRS_CH_CTRL_SOURCESEL(0b101010) -#define PRS_CH_CTRL_SOURCESEL_GPIOL PRS_CH_CTRL_SOURCESEL(0b110000) -#define PRS_CH_CTRL_SOURCESEL_GPIOH PRS_CH_CTRL_SOURCESEL(0b110001) -#define PRS_CH_CTRL_SOURCESEL_LETIMER0 PRS_CH_CTRL_SOURCESEL(0b110100) -#define PRS_CH_CTRL_SOURCESEL_BURTC PRS_CH_CTRL_SOURCESEL(0b110111) -#define PRS_CH_CTRL_SOURCESEL_LESENSEL PRS_CH_CTRL_SOURCESEL(0b111001) -#define PRS_CH_CTRL_SOURCESEL_LESENSEH PRS_CH_CTRL_SOURCESEL(0b111010) -#define PRS_CH_CTRL_SOURCESEL_LESENSED PRS_CH_CTRL_SOURCESEL(0b111011) - -#define PRS_CH_CTRL_SIGSEL_SHIFT (0) -#define PRS_CH_CTRL_SIGSEL_MASK (0x7 << PRS_CH_CTRL_SIGSEL_SHIFT) -#define PRS_CH_CTRL_SIGSEL(v) \ - (((v) << PRS_CH_CTRL_SIGSEL_SHIFT) & PRS_CH_CTRL_SIGSEL_MASK) -#define PRS_CH_CTRL_SIGSEL_OFF PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_VCMPOUT PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_ACMP0OUT PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_ACMP1OUT PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_DAC0CH0 PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_DAC0CH1 PRS_CH_CTRL_SIGSEL(1) -#define PRS_CH_CTRL_SIGSEL_ADCSINGLE PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_ADCSCAN PRS_CH_CTRL_SIGSEL(1) -#define PRS_CH_CTRL_SIGSEL_USART0IRTX PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_USART0TXC PRS_CH_CTRL_SIGSEL(1) -#define PRS_CH_CTRL_SIGSEL_USART0RXDATA PRS_CH_CTRL_SIGSEL(2) -#define PRS_CH_CTRL_SIGSEL_USART1TXC PRS_CH_CTRL_SIGSEL(1) -#define PRS_CH_CTRL_SIGSEL_USART1RXDATAV PRS_CH_CTRL_SIGSEL(2) -#define PRS_CH_CTRL_SIGSEL_USART2TXC PRS_CH_CTRL_SIGSEL(1) -#define PRS_CH_CTRL_SIGSEL_USART2RXDATAV PRS_CH_CTRL_SIGSEL(2) -#define PRS_CH_CTRL_SIGSEL_TIMER0UF PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_TIMER0OF PRS_CH_CTRL_SIGSEL(1) -#define PRS_CH_CTRL_SIGSEL_TIMER0CC0 PRS_CH_CTRL_SIGSEL(2) -#define PRS_CH_CTRL_SIGSEL_TIMER0CC1 PRS_CH_CTRL_SIGSEL(3) -#define PRS_CH_CTRL_SIGSEL_TIMER0CC2 PRS_CH_CTRL_SIGSEL(4) -#define PRS_CH_CTRL_SIGSEL_TIMER1UF PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_TIMER1OF PRS_CH_CTRL_SIGSEL(1) -#define PRS_CH_CTRL_SIGSEL_TIMER1CC0 PRS_CH_CTRL_SIGSEL(2) -#define PRS_CH_CTRL_SIGSEL_TIMER1CC1 PRS_CH_CTRL_SIGSEL(3) -#define PRS_CH_CTRL_SIGSEL_TIMER1CC2 PRS_CH_CTRL_SIGSEL(4) -#define PRS_CH_CTRL_SIGSEL_TIMER2UF PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_TIMER2OF PRS_CH_CTRL_SIGSEL(1) -#define PRS_CH_CTRL_SIGSEL_TIMER2CC0 PRS_CH_CTRL_SIGSEL(2) -#define PRS_CH_CTRL_SIGSEL_TIMER2CC1 PRS_CH_CTRL_SIGSEL(3) -#define PRS_CH_CTRL_SIGSEL_TIMER2CC2 PRS_CH_CTRL_SIGSEL(4) -#define PRS_CH_CTRL_SIGSEL_TIMER3UF PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_TIMER3OF PRS_CH_CTRL_SIGSEL(1) -#define PRS_CH_CTRL_SIGSEL_TIMER3CC0 PRS_CH_CTRL_SIGSEL(2) -#define PRS_CH_CTRL_SIGSEL_TIMER3CC1 PRS_CH_CTRL_SIGSEL(3) -#define PRS_CH_CTRL_SIGSEL_TIMER3CC2 PRS_CH_CTRL_SIGSEL(4) -#define PRS_CH_CTRL_SIGSEL_USBSOF PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_USBSOFSR PRS_CH_CTRL_SIGSEL(1) -#define PRS_CH_CTRL_SIGSEL_RTCOF PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_RTCCOMP0 PRS_CH_CTRL_SIGSEL(1) -#define PRS_CH_CTRL_SIGSEL_RTCCOMP1 PRS_CH_CTRL_SIGSEL(2) -#define PRS_CH_CTRL_SIGSEL_UART0TXC PRS_CH_CTRL_SIGSEL(1) -#define PRS_CH_CTRL_SIGSEL_UART0RXDATAV PRS_CH_CTRL_SIGSEL(2) -#define PRS_CH_CTRL_SIGSEL_UART1TXC PRS_CH_CTRL_SIGSEL(1) -#define PRS_CH_CTRL_SIGSEL_UART1RXDATAV PRS_CH_CTRL_SIGSEL(2) -#define PRS_CH_CTRL_SIGSEL_GPIOPIN0 PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_GPIOPIN1 PRS_CH_CTRL_SIGSEL(1) -#define PRS_CH_CTRL_SIGSEL_GPIOPIN2 PRS_CH_CTRL_SIGSEL(2) -#define PRS_CH_CTRL_SIGSEL_GPIOPIN3 PRS_CH_CTRL_SIGSEL(3) -#define PRS_CH_CTRL_SIGSEL_GPIOPIN4 PRS_CH_CTRL_SIGSEL(4) -#define PRS_CH_CTRL_SIGSEL_GPIOPIN5 PRS_CH_CTRL_SIGSEL(5) -#define PRS_CH_CTRL_SIGSEL_GPIOPIN6 PRS_CH_CTRL_SIGSEL(6) -#define PRS_CH_CTRL_SIGSEL_GPIOPIN7 PRS_CH_CTRL_SIGSEL(7) -#define PRS_CH_CTRL_SIGSEL_GPIOPIN8 PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_GPIOPIN9 PRS_CH_CTRL_SIGSEL(1) -#define PRS_CH_CTRL_SIGSEL_GPIOPIN10 PRS_CH_CTRL_SIGSEL(2) -#define PRS_CH_CTRL_SIGSEL_GPIOPIN11 PRS_CH_CTRL_SIGSEL(3) -#define PRS_CH_CTRL_SIGSEL_GPIOPIN12 PRS_CH_CTRL_SIGSEL(4) -#define PRS_CH_CTRL_SIGSEL_GPIOPIN13 PRS_CH_CTRL_SIGSEL(5) -#define PRS_CH_CTRL_SIGSEL_GPIOPIN14 PRS_CH_CTRL_SIGSEL(6) -#define PRS_CH_CTRL_SIGSEL_GPIOPIN15 PRS_CH_CTRL_SIGSEL(7) -#define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 PRS_CH_CTRL_SIGSEL(1) -#define PRS_CH_CTRL_SIGSEL_BURTCOF PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 PRS_CH_CTRL_SIGSEL(1) -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 PRS_CH_CTRL_SIGSEL(1) -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 PRS_CH_CTRL_SIGSEL(2) -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 PRS_CH_CTRL_SIGSEL(3) -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 PRS_CH_CTRL_SIGSEL(4) -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 PRS_CH_CTRL_SIGSEL(5) -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 PRS_CH_CTRL_SIGSEL(6) -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 PRS_CH_CTRL_SIGSEL(7) -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 PRS_CH_CTRL_SIGSEL(1) -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 PRS_CH_CTRL_SIGSEL(2) -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 PRS_CH_CTRL_SIGSEL(3) -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 PRS_CH_CTRL_SIGSEL(4) -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 PRS_CH_CTRL_SIGSEL(5) -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 PRS_CH_CTRL_SIGSEL(6) -#define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 PRS_CH_CTRL_SIGSEL(7) -#define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 PRS_CH_CTRL_SIGSEL(1) -#define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 PRS_CH_CTRL_SIGSEL(2) - -/* generic of above */ -#define PRS_CH_CTRL_SIGSEL_VCMP_OUT PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_ACMP_OUT PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_DAC_CHx(x) PRS_CH_CTRL_SIGSEL(x) -#define PRS_CH_CTRL_SIGSEL_DAC_CH0 PRS_CH_CTRL_SIGSEL_DAC_CHx(0) -#define PRS_CH_CTRL_SIGSEL_DAC_CH1 PRS_CH_CTRL_SIGSEL_DAC_CHx(1) -#define PRS_CH_CTRL_SIGSEL_ADC_SINGLE PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_ADC_SCAN PRS_CH_CTRL_SIGSEL(1) -#define PRS_CH_CTRL_SIGSEL_USART_IRTX PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_USART_TXC PRS_CH_CTRL_SIGSEL(1) -#define PRS_CH_CTRL_SIGSEL_USART_RXDATAV PRS_CH_CTRL_SIGSEL(2) -#define PRS_CH_CTRL_SIGSEL_TIMER_UF PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_TIMER_OF PRS_CH_CTRL_SIGSEL(1) -#define PRS_CH_CTRL_SIGSEL_TIMER_CCx(x) PRS_CH_CTRL_SIGSEL((x) + 2) -#define PRS_CH_CTRL_SIGSEL_TIMER_CC0 PRS_CH_CTRL_SIGSEL_TIMER_CCx(0) -#define PRS_CH_CTRL_SIGSEL_TIMER_CC1 PRS_CH_CTRL_SIGSEL_TIMER_CCx(1) -#define PRS_CH_CTRL_SIGSEL_TIMER_CC2 PRS_CH_CTRL_SIGSEL_TIMER_CCx(2) -#define PRS_CH_CTRL_SIGSEL_USB_SOF PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_USB_SOFSR PRS_CH_CTRL_SIGSEL(1) -#define PRS_CH_CTRL_SIGSEL_RTC_OF PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_RTC_COMPx(x) PRS_CH_CTRL_SIGSEL((x) + 1) -#define PRS_CH_CTRL_SIGSEL_RTC_COMP0 PRS_CH_CTRL_SIGSEL_RTC_COMPx(0) -#define PRS_CH_CTRL_SIGSEL_RTC_COMP1 PRS_CH_CTRL_SIGSEL_RTC_COMPx(1) -#define PRS_CH_CTRL_SIGSEL_UART_TXC PRS_CH_CTRL_SIGSEL(1) -#define PRS_CH_CTRL_SIGSEL_UART_RXDATAV PRS_CH_CTRL_SIGSEL(2) -#define PRS_CH_CTRL_SIGSEL_GPIOL_PINx(x) PRS_CH_CTRL_SIGSEL(x) -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN0 \ - PRS_CH_CTRL_SIGSEL_GPIOL_PINx(0) -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN1 \ - PRS_CH_CTRL_SIGSEL_GPIOL_PINx(1) -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN2 \ - PRS_CH_CTRL_SIGSEL_GPIOL_PINx(2) -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN3 \ - PRS_CH_CTRL_SIGSEL_GPIOL_PINx(3) -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN4 \ - PRS_CH_CTRL_SIGSEL_GPIOL_PINx(4) -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN5 \ - PRS_CH_CTRL_SIGSEL_GPIOL_PINx(5) -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN6 \ - PRS_CH_CTRL_SIGSEL_GPIOL_PINx(6) -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN7 \ - PRS_CH_CTRL_SIGSEL_GPIOL_PINx(7) -#define PRS_CH_CTRL_SIGSEL_GPIOH_PINx(x) PRS_CH_CTRL_SIGSEL((x) - 8) -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN8 \ - PRS_CH_CTRL_SIGSEL_GPIOH_PINx(8) -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN9 \ - PRS_CH_CTRL_SIGSEL_GPIOH_PINx(9) -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN10 \ - PRS_CH_CTRL_SIGSEL_GPIOH_PINx(10) -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN11 \ - PRS_CH_CTRL_SIGSEL_GPIOH_PINx(11) -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN12 \ - PRS_CH_CTRL_SIGSEL_GPIOH_PINx(12) -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN13 \ - PRS_CH_CTRL_SIGSEL_GPIOH_PINx(13) -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN14 \ - PRS_CH_CTRL_SIGSEL_GPIOH_PINx(14) -#define PRS_CH_CTRL_SIGSEL_GPIO_PIN15 \ - PRS_CH_CTRL_SIGSEL_GPIOH_PINx(15) -#define PRS_CH_CTRL_SIGSEL_LETIMER_CHx(x) PRS_CH_CTRL_SIGSEL(x) -#define PRS_CH_CTRL_SIGSEL_LETIMER_CH0 \ - PRS_CH_CTRL_SIGSEL_LETIMER_CHx(0) -#define PRS_CH_CTRL_SIGSEL_LETIMER_CH1 \ - PRS_CH_CTRL_SIGSEL_LETIMER_CHx(1) -#define PRS_CH_CTRL_SIGSEL_BURTC_OF PRS_CH_CTRL_SIGSEL(0) -#define PRS_CH_CTRL_SIGSEL_BURTC_COMP0 PRS_CH_CTRL_SIGSEL(1) -#define PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(x) PRS_CH_CTRL_SIGSEL(x) -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES0 \ - PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(0) -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES1 \ - PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(1) -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES2 \ - PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(2) -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES3 \ - PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(3) -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES4 \ - PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(4) -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES5 \ - PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(5) -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES6 \ - PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(6) -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES7 \ - PRS_CH_CTRL_SIGSEL_LESENSEL_SCANRESx(7) -#define PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(x) \ - PRS_CH_CTRL_SIGSEL((x) - 8) -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES8 \ - PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(8) -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES9 \ - PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(9) -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES10 \ - PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(10) -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES11 \ - PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(11) -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES12 \ - PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(12) -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES13 \ - PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(13) -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES14 \ - PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(14) -#define PRS_CH_CTRL_SIGSEL_LESENSE_SCANRES15 \ - PRS_CH_CTRL_SIGSEL_LESENSEH_SCANRESx(15) -#define PRS_CH_CTRL_SIGSEL_LESENSED_DECx(x) PRS_CH_CTRL_SIGSEL(x) -#define PRS_CH_CTRL_SIGSEL_LESENSE_DEC0 \ - PRS_CH_CTRL_SIGSEL_LESENSED_DECx(0) -#define PRS_CH_CTRL_SIGSEL_LESENSE_DEC1 \ - PRS_CH_CTRL_SIGSEL_LESENSED_DECx(1) -#define PRS_CH_CTRL_SIGSEL_LESENSE_DEC2 \ - PRS_CH_CTRL_SIGSEL_LESENSED_DECx(2) - -/** @defgroup prs_ch PRS Channel Number -@ingroup prs_defines - -@{*/ -enum prs_ch { - PRS_CH0 = 0, - PRS_CH1, - PRS_CH2, - PRS_CH3, - PRS_CH4, - PRS_CH5, - PRS_CH6, - PRS_CH7, - PRS_CH8, - PRS_CH9, - PRS_CH10, - PRS_CH11 -}; -/**@}*/ - -BEGIN_DECLS - -void prs_enable_gpio_output(enum prs_ch ch); -void prs_disable_gpio_output(enum prs_ch ch); -void prs_set_output_loc(uint32_t loc); - -void prs_software_pulse(enum prs_ch ch); -void prs_software_level_high(enum prs_ch ch); -void prs_software_level_low(enum prs_ch ch); - -void prs_enable_async(enum prs_ch ch); -void prs_disable_async(enum prs_ch ch); -void prs_set_edge(enum prs_ch ch, uint32_t edge); -void prs_set_source(enum prs_ch ch, uint32_t source); -void prs_set_signal(enum prs_ch ch, uint32_t sig); - -END_DECLS +#include #endif - diff --git a/include/libopencm3/efm32/lg/rmu.h b/include/libopencm3/efm32/lg/rmu.h index 4a7e721a..21415073 100644 --- a/include/libopencm3/efm32/lg/rmu.h +++ b/include/libopencm3/efm32/lg/rmu.h @@ -1,7 +1,7 @@ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2015 Kuldeep Singh Dhaka + * Copyright (C) 2016 Bob Miller * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -17,40 +17,9 @@ * along with this library. If not, see . */ -#ifndef LIBOPENCM3_EFM32_RMU_H -#define LIBOPENCM3_EFM32_RMU_H +#ifndef LIBOPENCM3_EFM32_LG_RMU_H +#define LIBOPENCM3_EFM32_LG_RMU_H -#include -#include - -#define RMU_CTRL MMIO32(RMU_BASE + 0x00) -#define RMU_RSTCAUSE MMIO32(RMU_BASE + 0x04) -#define RMU_CMD MMIO32(RMU_BASE + 0x08) - -/* RMU_CTRL */ -#define RMU_CTRL_BURSTEN (1 << 1) -#define RMU_CTRL_LOCKUPRDIS (1 << 0) - -/* RMU_RSTCAUSE */ -#define RMU_RSTCAUSE_BUMODERST (1 << 15) -#define RMU_RSTCAUSE_BUBODREG (1 << 14) -#define RMU_RSTCAUSE_BUBODUNREG (1 << 13) -#define RMU_RSTCAUSE_BUBODBUVIN (1 << 12) -#define RMU_RSTCAUSE_BUBODVDDDREG (1 << 11) -#define RMU_RSTCAUSE_BODAVDD1 (1 << 10) -#define RMU_RSTCAUSE_BODAVDD0 (1 << 9) -#define RMU_RSTCAUSE_EM4WURST (1 << 8) -#define RMU_RSTCAUSE_EM4RST (1 << 7) -#define RMU_RSTCAUSE_SYSREQRST (1 << 6) -#define RMU_RSTCAUSE_LOCKUPRST (1 << 5) -#define RMU_RSTCAUSE_WDOGRST (1 << 4) -#define RMU_RSTCAUSE_EXTRST (1 << 3) -#define RMU_RSTCAUSE_BODREGRST (1 << 2) -#define RMU_RSTCAUSE_BODUNREGRST (1 << 1) -#define RMU_RSTCAUSE_PORST (1 << 0) - -/* RMU_CMD */ -#define RMU_CMD_RCCLR (1 << 0) +#include #endif - diff --git a/include/libopencm3/efm32/lg/rtc.h b/include/libopencm3/efm32/lg/rtc.h index ad50bcbd..49b2abaa 100644 --- a/include/libopencm3/efm32/lg/rtc.h +++ b/include/libopencm3/efm32/lg/rtc.h @@ -1,7 +1,7 @@ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2015 Kuldeep Singh Dhaka + * Copyright (C) 2016 Bob Miller * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -17,55 +17,9 @@ * along with this library. If not, see . */ -#ifndef LIBOPENCM3_EFM32_RTC_H -#define LIBOPENCM3_EFM32_RTC_H +#ifndef LIBOPENCM3_EFM32_LG_RTC_H +#define LIBOPENCM3_EFM32_LG_RTC_H -#include -#include - -#define RTC_CTRL (RTC_BASE + 0x000) -#define RTC_CNT (RTC_BASE + 0x004) -#define RTC_COMP0 (RTC_BASE + 0x008) -#define RTC_COMP1 (RTC_BASE + 0x00C) -#define RTC_IF (RTC_BASE + 0x010) -#define RTC_IFS (RTC_BASE + 0x014) -#define RTC_IFC (RTC_BASE + 0x018) -#define RTC_IEN (RTC_BASE + 0x01C) -#define RTC_FREEZE (RTC_BASE + 0x020) -#define RTC_SYNCBUSY (RTC_BASE + 0x024) - -/* RTC_CTRL */ -#define RTC_CTRL_COMP0TOP (1 << 2) -#define RTC_CTRL_DEBUGRUN (1 << 1) -#define RTC_CTRL_EN (1 << 0) - -/* RTC_IF */ -#define RTC_IF_COMP1 (1 << 2) -#define RTC_IF_COMP0 (1 << 1) -#define RTC_IF_OF (1 << 0) - -/* RTC_IFS */ -#define RTC_IFS_COMP1 (1 << 2) -#define RTC_IFS_COMP0 (1 << 1) -#define RTC_IFS_OF (1 << 0) - -/* RTC_IFC */ -#define RTC_IFC_COMP1 (1 << 2) -#define RTC_IFC_COMP0 (1 << 1) -#define RTC_IFC_OF (1 << 0) - -/* RTC_IFE */ -#define RTC_IFE_COMP1 (1 << 2) -#define RTC_IFE_COMP0 (1 << 1) -#define RTC_IFE_OF (1 << 0) - -/* RTC_FREEZE */ -#define RTC_FREEZE_REGFREEZE (1 << 0) - -/* RTC_SYNCBUSY */ -#define RTC_SYNCBUSY_COMP1 (1 << 2) -#define RTC_SYNCBUSY_COMP0 (1 << 1) -#define RTC_SYNCBUSY_CTRL (1 << 0) +#include #endif - diff --git a/include/libopencm3/efm32/lg/timer.h b/include/libopencm3/efm32/lg/timer.h index fc8f3513..83c6b20d 100644 --- a/include/libopencm3/efm32/lg/timer.h +++ b/include/libopencm3/efm32/lg/timer.h @@ -18,75 +18,6 @@ #ifndef LIBOPENCM3_TIMER_H #define LIBOPENCM3_TIMER_H -#include - -/* efm32lg specific registers */ - -/* TIMER_CCx_CTRL */ -#define TIMER_CC_CTRL_PRSSEL_SHIFT (16) -#define TIMER_CC_CTRL_PRSSEL_MASK (0xF << TIMER_CC_CTRL_PRSSEL_SHIFT) -#define TIMER_CC_CTRL_PRSSEL(v) \ - (((v) << TIMER_CC_CTRL_PRSSEL_SHIFT) & TIMER_CC_CTRL_PRSSEL_MASK) -#define TIMER_CC_CTRL_PRSSEL_PRSCHx(x) TIMER_CC_CTRL_PRSSEL(x) -#define TIMER_CC_CTRL_PRSSEL_PRSCH0 TIMER_CC_CTRL_PRSSEL_PRSCHx(0) -#define TIMER_CC_CTRL_PRSSEL_PRSCH1 TIMER_CC_CTRL_PRSSEL_PRSCHx(1) -#define TIMER_CC_CTRL_PRSSEL_PRSCH2 TIMER_CC_CTRL_PRSSEL_PRSCHx(2) -#define TIMER_CC_CTRL_PRSSEL_PRSCH3 TIMER_CC_CTRL_PRSSEL_PRSCHx(3) -#define TIMER_CC_CTRL_PRSSEL_PRSCH4 TIMER_CC_CTRL_PRSSEL_PRSCHx(4) -#define TIMER_CC_CTRL_PRSSEL_PRSCH5 TIMER_CC_CTRL_PRSSEL_PRSCHx(5) -#define TIMER_CC_CTRL_PRSSEL_PRSCH6 TIMER_CC_CTRL_PRSSEL_PRSCHx(6) -#define TIMER_CC_CTRL_PRSSEL_PRSCH7 TIMER_CC_CTRL_PRSSEL_PRSCHx(7) -#define TIMER_CC_CTRL_PRSSEL_PRSCH8 TIMER_CC_CTRL_PRSSEL_PRSCHx(8) -#define TIMER_CC_CTRL_PRSSEL_PRSCH9 TIMER_CC_CTRL_PRSSEL_PRSCHx(9) -#define TIMER_CC_CTRL_PRSSEL_PRSCH10 TIMER_CC_CTRL_PRSSEL_PRSCHx(10) -#define TIMER_CC_CTRL_PRSSEL_PRSCH11 TIMER_CC_CTRL_PRSSEL_PRSCHx(11) - -/* TIMER_DTCTRL */ -#define TIMER_DTCTRL_DTPRSSEL_SHIFT (4) -#define TIMER_DTCTRL_DTPRSSEL_MASK (0xF << TIMER_DTCTRL_DTPRSSEL_SHIFT) -#define TIMER_DTCTRL_DTPRSSEL(v) \ - (((v) << TIMER_DTCTRL_DTPRSSEL_SHIFT) & TIMER_DTCTRL_DTPRSSEL_MASK) -#define TIMER_DTCTRL_DTPRSSEL_PRSCHx(x) TIMER_DTCTRL_DTPRSSEL(x) -#define TIMER_DTCTRL_DTPRSSEL_PRSCH0 TIMER_DTCTRL_DTPRSSEL_PRSCHx(0) -#define TIMER_DTCTRL_DTPRSSEL_PRSCH1 TIMER_DTCTRL_DTPRSSEL_PRSCHx(1) -#define TIMER_DTCTRL_DTPRSSEL_PRSCH2 TIMER_DTCTRL_DTPRSSEL_PRSCHx(2) -#define TIMER_DTCTRL_DTPRSSEL_PRSCH3 TIMER_DTCTRL_DTPRSSEL_PRSCHx(3) -#define TIMER_DTCTRL_DTPRSSEL_PRSCH4 TIMER_DTCTRL_DTPRSSEL_PRSCHx(4) -#define TIMER_DTCTRL_DTPRSSEL_PRSCH5 TIMER_DTCTRL_DTPRSSEL_PRSCHx(5) -#define TIMER_DTCTRL_DTPRSSEL_PRSCH6 TIMER_DTCTRL_DTPRSSEL_PRSCHx(6) -#define TIMER_DTCTRL_DTPRSSEL_PRSCH7 TIMER_DTCTRL_DTPRSSEL_PRSCHx(7) -#define TIMER_DTCTRL_DTPRSSEL_PRSCH8 TIMER_DTCTRL_DTPRSSEL_PRSCHx(8) -#define TIMER_DTCTRL_DTPRSSEL_PRSCH9 TIMER_DTCTRL_DTPRSSEL_PRSCHx(9) -#define TIMER_DTCTRL_DTPRSSEL_PRSCH10 TIMER_DTCTRL_DTPRSSEL_PRSCHx(10) -#define TIMER_DTCTRL_DTPRSSEL_PRSCH11 TIMER_DTCTRL_DTPRSSEL_PRSCHx(11) - -/* TIMER3 */ -#define TIMER3 TIMER3_BASE -#define TIMER3_CTRL TIMER_CTRL(TIMER3) -#define TIMER3_CMD TIMER_CMD(TIMER3) -#define TIMER3_STATUS TIMER_STATUS(TIMER3) -#define TIMER3_IEN TIMER_IEN(TIMER3) -#define TIMER3_IF TIMER_IF(TIMER3) -#define TIMER3_IFS TIMER_IFS(TIMER3) -#define TIMER3_IFC TIMER_IFC(TIMER3) -#define TIMER3_TOP TIMER_TOP(TIMER3) -#define TIMER3_TOPB TIMER_TOPB(TIMER3) -#define TIMER3_CNT TIMER_CNT(TIMER3) -#define TIMER3_ROUTE TIMER_ROUTE(TIMER3) - -#define TIMER3_CC0_CTRL TIMER_CC0_CTRL(TIMER3) -#define TIMER3_CC0_CCV TIMER_CC0_CCV(TIMER3) -#define TIMER3_CC0_CCVP TIMER_CC0_CCVP(TIMER3) -#define TIMER3_CC0_CCVB TIMER_CC0_CCVB(TIMER3) - -#define TIMER3_CC1_CTRL TIMER_CC1_CTRL(TIMER3) -#define TIMER3_CC1_CCV TIMER_CC1_CCV(TIMER3) -#define TIMER3_CC1_CCVP TIMER_CC1_CCVP(TIMER3) -#define TIMER3_CC1_CCVB TIMER_CC1_CCVB(TIMER3) - -#define TIMER3_CC2_CTRL TIMER_CC2_CTRL(TIMER3) -#define TIMER3_CC2_CCV TIMER_CC2_CCV(TIMER3) -#define TIMER3_CC2_CCVP TIMER_CC2_CCVP(TIMER3) -#define TIMER3_CC2_CCVB TIMER_CC2_CCVB(TIMER3) +#include #endif diff --git a/include/libopencm3/efm32/lg/uart.h b/include/libopencm3/efm32/lg/uart.h index b69617ba..86b493fd 100644 --- a/include/libopencm3/efm32/lg/uart.h +++ b/include/libopencm3/efm32/lg/uart.h @@ -1,7 +1,7 @@ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2015 Kuldeep Singh Dhaka + * Copyright (C) 2016 Bob Miller * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -17,84 +17,9 @@ * along with this library. If not, see . */ -#ifndef LIBOPENCM3_EFM32_UART_H -#define LIBOPENCM3_EFM32_UART_H +#ifndef LIBOPENCM3_EFM32_LG_UART_H +#define LIBOPENCM3_EFM32_LG_UART_H -/** - * USART and UART registers are equivalent except [in UART registers]: - * - * USART_CTRL: SYNC, CSMA, SMSDELAY, SSSEARLY, CSINV, CPOL and CPHA [1] - * USART_STATUS: MASTEREN [1] - * [1] Synchronous operation not available. - * USART_CTRL: MSBF (transmission LSB first only) - * USART_CTRL: AUTOCS (chip-select not available) - * USART_CTRL: SCMODE (SmartCard mode not available) - * USART_FRAME: DATABITS (limited framsize. 8-9 databits only) - * USART_IRCTRL: IREN (IrDA not available) - * (except DATABITS, all the above are 0) - * - * full text: (p495, "d0183_Rev1.10" EFM32LG-RM) - * - "18.3 Functional Description", - * - "18.4 Register Description" - * - "18.5 Register Map" - * - * use USART macro's to manipulate UART registers. - */ -#include -#include - -/* UART0 */ -#define UART0 UART0_BASE -#define UART0_CTRL USART_CTRL(UART0) -#define UART0_FRAME USART_FRAME(UART0) -#define UART0_TRIGCTRL USART_TRIGCTRL(UART0) -#define UART0_CMD USART_CMD(UART0) -#define UART0_STATUS USART_STATUS(UART0) -#define UART0_CLKDIV USART_CLKDIV(UART0) -#define UART0_RXDATAX USART_RXDATAX(UART0) -#define UART0_RXDATA USART_RXDATA(UART0) -#define UART0_RXDOUBLEX USART_RXDOUBLEX(UART0) -#define UART0_RXDOUBLE USART_RXDOUBLE(UART0) -#define UART0_RXDATAXP USART_RXDATAXP(UART0) -#define UART0_RXDOUBLEXP USART_RXDOUBLEXP(UART0) -#define UART0_TXDATAX USART_TXDATAX(UART0) -#define UART0_TXDATA USART_TXDATA(UART0) -#define UART0_TXDOUBLEX USART_TXDOUBLEX(UART0) -#define UART0_TXDOUBLE USART_TXDOUBLE(UART0) -#define UART0_IF USART_IF(UART0) -#define UART0_IFS USART_IFS(UART0) -#define UART0_IFC USART_IFC(UART0) -#define UART0_IEN USART_IEN(UART0) -#define UART0_IRCTRL USART_IRCTRL(UART0) -#define UART0_ROUTE USART_ROUTE(UART0) -#define UART0_INPUT USART_INPUT(UART0) -#define UART0_I2SCTRL USART_I2SCTRL(UART0) - -/* UART1 */ -#define UART1 UART1_BASE -#define UART1_CTRL USART_CTRL(UART1) -#define UART1_FRAME USART_FRAME(UART1) -#define UART1_TRIGCTRL USART_TRIGCTRL(UART1) -#define UART1_CMD USART_CMD(UART1) -#define UART1_STATUS USART_STATUS(UART1) -#define UART1_CLKDIV USART_CLKDIV(UART1) -#define UART1_RXDATAX USART_RXDATAX(UART1) -#define UART1_RXDATA USART_RXDATA(UART1) -#define UART1_RXDOUBLEX USART_RXDOUBLEX(UART1) -#define UART1_RXDOUBLE USART_RXDOUBLE(UART1) -#define UART1_RXDATAXP USART_RXDATAXP(UART1) -#define UART1_RXDOUBLEXP USART_RXDOUBLEXP(UART1) -#define UART1_TXDATAX USART_TXDATAX(UART1) -#define UART1_TXDATA USART_TXDATA(UART1) -#define UART1_TXDOUBLEX USART_TXDOUBLEX(UART1) -#define UART1_TXDOUBLE USART_TXDOUBLE(UART1) -#define UART1_IF USART_IF(UART1) -#define UART1_IFS USART_IFS(UART1) -#define UART1_IFC USART_IFC(UART1) -#define UART1_IEN USART_IEN(UART1) -#define UART1_IRCTRL USART_IRCTRL(UART1) -#define UART1_ROUTE USART_ROUTE(UART1) -#define UART1_INPUT USART_INPUT(UART1) -#define UART1_I2SCTRL USART_I2SCTRL(UART1) +#include #endif diff --git a/include/libopencm3/efm32/lg/usart.h b/include/libopencm3/efm32/lg/usart.h index daafe598..41c1ec1a 100644 --- a/include/libopencm3/efm32/lg/usart.h +++ b/include/libopencm3/efm32/lg/usart.h @@ -1,7 +1,7 @@ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2015 Kuldeep Singh Dhaka + * Copyright (C) 2016 Bob Miller * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -17,496 +17,9 @@ * along with this library. If not, see . */ -#ifndef LIBOPENCM3_EFM32_USART_H -#define LIBOPENCM3_EFM32_USART_H +#ifndef LIBOPENCM3_EFM32_LG_USART_H +#define LIBOPENCM3_EFM32_LG_USART_H -#include -#include - -#define USART_CTRL(base) MMIO32((base) + 0x000) -#define USART_FRAME(base) MMIO32((base) + 0x004) -#define USART_TRIGCTRL(base) MMIO32((base) + 0x008) -#define USART_CMD(base) MMIO32((base) + 0x00C) -#define USART_STATUS(base) MMIO32((base) + 0x010) -#define USART_CLKDIV(base) MMIO32((base) + 0x014) -#define USART_RXDATAX(base) MMIO32((base) + 0x018) -#define USART_RXDATA(base) MMIO32((base) + 0x01C) -#define USART_RXDOUBLEX(base) MMIO32((base) + 0x020) -#define USART_RXDOUBLE(base) MMIO32((base) + 0x024) -#define USART_RXDATAXP(base) MMIO32((base) + 0x028) -#define USART_RXDOUBLEXP(base) MMIO32((base) + 0x02C) -#define USART_TXDATAX(base) MMIO32((base) + 0x030) -#define USART_TXDATA(base) MMIO32((base) + 0x034) -#define USART_TXDOUBLEX(base) MMIO32((base) + 0x038) -#define USART_TXDOUBLE(base) MMIO32((base) + 0x03C) -#define USART_IF(base) MMIO32((base) + 0x040) -#define USART_IFS(base) MMIO32((base) + 0x044) -#define USART_IFC(base) MMIO32((base) + 0x048) -#define USART_IEN(base) MMIO32((base) + 0x04C) -#define USART_IRCTRL(base) MMIO32((base) + 0x050) -#define USART_ROUTE(base) MMIO32((base) + 0x054) -#define USART_INPUT(base) MMIO32((base) + 0x058) -#define USART_I2SCTRL(base) MMIO32((base) + 0x05C) - -/* USART_CTRL */ -#define USART_CTRL_SMSDELAY (1 << 31) -#define USART_CTRL_MVDIS (1 << 30) -#define USART_CTRL_AUTOTX (1 << 29) -#define USART_CTRL_BYTESWAP (1 << 28) - -#define USART_CTRL_TXDELAY_SHIFT (26) -#define USART_CTRL_TXDELAY_MASK (0x3 << USART_CTRL_TXDELAY_SHIFT) -#define USART_CTRL_TXDELAY(v) \ - (((v) << USART_CTRL_TXDELAY_SHIFT) & USART_CTRL_TXDELAY_MASK) -#define USART_CTRL_TXDELAY_NONE USART_CTRL_TXDELAY(0) -#define USART_CTRL_TXDELAY_SINGLE USART_CTRL_TXDELAY(1) -#define USART_CTRL_TXDELAY_DOUBLE USART_CTRL_TXDELAY(2) -#define USART_CTRL_TXDELAY_TRIPLE USART_CTRL_TXDELAY(3) - -#define USART_CTRL_SSSEARLY (1 << 25) -#define USART_CTRL_ERRSTX (1 << 24) -#define USART_CTRL_ERRSRX (1 << 23) -#define USART_CTRL_ERRSDMA (1 << 22) -#define USART_CTRL_BIT8DV (1 << 21) -#define USART_CTRL_SKIPPERRF (1 << 20) -#define USART_CTRL_SCRETRANS (1 << 19) -#define USART_CTRL_SCMODE (1 << 18) -#define USART_CTRL_AUTOTRI (1 << 17) -#define USART_CTRL_AUTOCS (1 << 16) -#define USART_CTRL_CSINV (1 << 15) -#define USART_CTRL_TXINV (1 << 14) -#define USART_CTRL_RXINV (1 << 13) -#define USART_CTRL_TXBIL (1 << 12) -#define USART_CTRL_CSMA (1 << 11) -#define USART_CTRL_MSBF (1 << 10) -#define USART_CTRL_CLKPHA (1 << 9) -#define USART_CTRL_CLKPOL (1 << 8) - -#define USART_CTRL_OVS_SHIFT (5) -#define USART_CTRL_OVS_MASK (0x3 << USART_CTRL_OVS_SHIFT) -#define USART_CTRL_OVS(v) \ - (((v) << USART_CTRL_OVS_SHIFT) & USART_CTRL_OVS_MASK) -#define USART_CTRL_OVS_X16 USART_CTRL_OVS(0) -#define USART_CTRL_OVS_X8 USART_CTRL_OVS(1) -#define USART_CTRL_OVS_X6 USART_CTRL_OVS(2) -#define USART_CTRL_OVS_X4 USART_CTRL_OVS(3) - -#define USART_CTRL_MPAB (1 << 4) -#define USART_CTRL_MPM (1 << 3) -#define USART_CTRL_CCEN (1 << 2) -#define USART_CTRL_LOOPBK (1 << 1) -#define USART_CTRL_SYNC (1 << 0) - -/* USART_FRAME */ - -#define USART_FRAME_STOPBITS_SHIFT (12) -#define USART_FRAME_STOPBITS_MASK (0x3 << USART_FRAME_STOPBITS_SHIFT) -#define USART_FRAME_STOPBITS(v) \ - (((v) << USART_FRAME_STOPBITS_SHIFT) & USART_FRAME_STOPBITS_MASK) -#define USART_FRAME_STOPBITS_HALF USART_FRAME_STOPBITS(0) -#define USART_FRAME_STOPBITS_ONE USART_FRAME_STOPBITS(1) -#define USART_FRAME_STOPBITS_ONEANDAHALF USART_FRAME_STOPBITS(2) -#define USART_FRAME_STOPBITS_ONE_AND_A_HALF \ - USART_FRAME_STOPBITS_ONEANDAHALF -#define USART_FRAME_STOPBITS_TWO USART_FRAME_STOPBITS(3) - -#define USART_FRAME_PARITY_SHIFT (8) -#define USART_FRAME_PARITY_MASK (0x3 << USART_FRAME_PARITY_SHIFT) -#define USART_FRAME_PARITY(v) \ - (((v) << USART_FRAME_PARITY_SHIFT) & USART_FRAME_PARITY_MASK) -#define USART_FRAME_PARITY_NONE USART_FRAME_PARITY(0) -#define USART_FRAME_PARITY_EVEN USART_FRAME_PARITY(2) -#define USART_FRAME_PARITY_ODD USART_FRAME_PARITY(3) - -#define USART_FRAME_DATABITS_SHIFT (0) -#define USART_FRAME_DATABITS_MASK (0xF << USART_FRAME_DATABITS_SHIFT) -#define USART_FRAME_DATABITS(v) \ - (((v) << USART_FRAME_DATABITS_SHIFT) & USART_FRAME_DATABITS_MASK) -#define USART_FRAME_DATABITS_FOUR USART_FRAME_DATABITS(1) -#define USART_FRAME_DATABITS_FIVE USART_FRAME_DATABITS(2) -#define USART_FRAME_DATABITS_SIX USART_FRAME_DATABITS(3) -#define USART_FRAME_DATABITS_SEVEN USART_FRAME_DATABITS(4) -#define USART_FRAME_DATABITS_EIGHT USART_FRAME_DATABITS(5) -#define USART_FRAME_DATABITS_NINE USART_FRAME_DATABITS(6) -#define USART_FRAME_DATABITS_TEN USART_FRAME_DATABITS(7) -#define USART_FRAME_DATABITS_ELEVEN USART_FRAME_DATABITS(8) -#define USART_FRAME_DATABITS_TWELVE USART_FRAME_DATABITS(9) -#define USART_FRAME_DATABITS_THIRTEEN USART_FRAME_DATABITS(10) -#define USART_FRAME_DATABITS_FOURTEEN USART_FRAME_DATABITS(11) -#define USART_FRAME_DATABITS_FIFTEEN USART_FRAME_DATABITS(12) -#define USART_FRAME_DATABITS_SIXTEEN USART_FRAME_DATABITS(13) - -/* USART_TRIGCTRL */ -#define USART_TRIGCTRL_AUTOTXTEN (1 << 6) -#define USART_TRIGCTRL_TXTEN (1 << 5) -#define USART_TRIGCTRL_RXTEN (1 << 4) - -#define USART_TRIGCTRL_TSEL_SHIFT (8) -#define USART_TRIGCTRL_TSEL_MASK (0x3 << USART_TRIGCTRL_TSEL_SHIFT) -#define USART_TRIGCTRL_TSEL_PRSCHx(v) \ - (((v) << USART_TRIGCTRL_TSEL_SHIFT) & USART_TRIGCTRL_TSEL_MASK) -#define USART_TRIGCTRL_TSEL_PRSCH0 USART_TRIGCTRL_TSEL_PRSCHx(0) -#define USART_TRIGCTRL_TSEL_PRSCH1 USART_TRIGCTRL_TSEL_PRSCHx(1) -#define USART_TRIGCTRL_TSEL_PRSCH2 USART_TRIGCTRL_TSEL_PRSCHx(2) -#define USART_TRIGCTRL_TSEL_PRSCH3 USART_TRIGCTRL_TSEL_PRSCHx(3) -#define USART_TRIGCTRL_TSEL_PRSCH4 USART_TRIGCTRL_TSEL_PRSCHx(4) -#define USART_TRIGCTRL_TSEL_PRSCH5 USART_TRIGCTRL_TSEL_PRSCHx(5) -#define USART_TRIGCTRL_TSEL_PRSCH6 USART_TRIGCTRL_TSEL_PRSCHx(6) -#define USART_TRIGCTRL_TSEL_PRSCH7 USART_TRIGCTRL_TSEL_PRSCHx(7) - -/* USART_CMD */ -#define USART_CMD_CLEARRX (1 << 11) -#define USART_CMD_CLEARTX (1 << 10) -#define USART_CMD_TXTRIDIS (1 << 9) -#define USART_CMD_TXTRIEN (1 << 8) -#define USART_CMD_RXBLOCKDIS (1 << 7) -#define USART_CMD_RXBLOCKEN (1 << 6) -#define USART_CMD_MASTERDIS (1 << 5) -#define USART_CMD_MASTEREN (1 << 4) -#define USART_CMD_TXDIS (1 << 3) -#define USART_CMD_TXEN (1 << 2) -#define USART_CMD_RXDIS (1 << 1) -#define USART_CMD_RXEN (1 << 0) - -/* USART_STATUS */ -#define USART_STATUS_RXFULLRIGHT (1 << 12) -#define USART_STATUS_RXDATAVRIGHT (1 << 11) -#define USART_STATUS_TXBSRIGHT (1 << 10) -#define USART_STATUS_TXBDRIGHT (1 << 9) -#define USART_STATUS_RXFULL (1 << 8) -#define USART_STATUS_RXDATAV (1 << 7) -#define USART_STATUS_TXBL (1 << 6) -#define USART_STATUS_TXC (1 << 5) -#define USART_STATUS_TXTRI (1 << 4) -#define USART_STATUS_RXBLOCK (1 << 3) -#define USART_STATUS_MASTER (1 << 2) -#define USART_STATUS_TXENS (1 << 1) -#define USART_STATUS_RXENS (1 << 0) - -/* USART_CLKDIV */ -#define USART_CLKDIV_DIV_SHIFT (6) -#define USART_CLKDIV_DIV_MASK (0x7FFF << USART_CLKDIV_DIV_SHIFT) -#define USART_CLKDIV_DIV(v) \ - (((v) << USART_CLKDIV_DIV_SHIFT) & USART_CLKDIV_DIV_MASK) - -/* USART_RXDATAX */ -#define USART_RXDATAX_FERR (1 << 15) -#define USART_RXDATAX_PERR (1 << 14) - -#define USART_RXDATAX_RXDATA_SHIFT (0) -#define USART_RXDATAX_RXDATA_MASK (0x1FF << USART_RXDATAX_RXDATA_SHIFT) - -/* USART_RXDOUBLEX */ -#define USART_RXDOUBLEX_FERR1 (1 << 31) -#define USART_RXDOUBLEX_PERR1 (1 << 30) - -#define USART_RXDOUBLEX_RXDATA1_SHIFT (16) -#define USART_RXDOUBLEX_RXDATA1_MASK \ - (0x1FF << USART_RXDOUBLEX_RXDATA1_SHIFT) - -#define USART_RXDOUBLEX_FERR0 (1 << 15) -#define USART_RXDOUBLEX_PERR0 (1 << 14) - -#define USART_RXDOUBLEX_RXDATA0_SHIFT (0) -#define USART_RXDOUBLEX_RXDATA0_MASK \ - (0x1FF << USART_RXDOUBLEX_RXDATA1_SHIFT) - -/* USART_RXDOUBLE */ -#define USART_RXDOUBLE_RXDATA1_SHIFT (8) -#define USART_RXDOUBLE_RXDATA1_MASK (0xFF << USART_RXDOUBLE_RXDATA1_SHIFT) - -#define USART_RXDOUBLE_RXDATA0_SHIFT (0) -#define USART_RXDOUBLE_RXDATA0_MASK (0xFF << USART_RXDOUBLE_RXDATA0_SHIFT) - -/* USART_RXDATAXP */ -#define USART_RXDATAXP_FERRP (1 << 15) -#define USART_RXDATAXP_PERRP (1 << 14) - -#define USART_RXDATAXP_RXDATAP_SHIFT (0) -#define USART_RXDATAXP_RXDATAP_MASK (0x1FF << USART_RXDATAXP_RXDATAP_SHIFT) - -/* USART_RXDOUBLEXP */ -#define USART_RXDOUBLEXP_FERR1 (1 << 31) -#define USART_RXDOUBLEXP_PERR1 (1 << 30) - -#define USART_RXDOUBLEXP_RXDATA1_SHIFT (16) -#define USART_RXDOUBLEXP_RXDATA1_MASK \ - (0x1FF << USART_RXDOUBLEXP_RXDATA1_SHIFT) - -#define USART_RXDOUBLEXP_FERR0 (1 << 15) -#define USART_RXDOUBLEXP_PERR0 (1 << 14) - -#define USART_RXDOUBLEXP_RXDATA0_SHIFT (0) -#define USART_RXDOUBLEXP_RXDATA0_MASK \ - (0x1FF << USART_RXDOUBLEXP_RXDATA1_SHIFT) - -/* USART_TXDATAX */ -#define USART_TXDATAX_RXENAT (1 << 15) -#define USART_TXDATAX_TXDISAT (1 << 14) -#define USART_TXDATAX_TXBREAK (1 << 13) -#define USART_TXDATAX_TXTRIAT (1 << 12) -#define USART_TXDATAX_UBRXAT (1 << 11) - -#define USART_TXDATAX_TXDATAX_SHIFT (0) -#define USART_TXDATAX_TXDATAX_MASK (0x1FF << USART_TXDATAX_TXDATAX_SHIFT) - -/* USART_TXDOUBLEX */ -#define USART_TXDOUBLEX_RXENAT1 (1 << 31) -#define USART_TXDOUBLEX_TXDISAT1 (1 << 30) -#define USART_TXDOUBLEX_TXBREAK1 (1 << 29) -#define USART_TXDOUBLEX_TXTRIAT1 (1 << 28) -#define USART_TXDOUBLEX_UBRXAT1 (1 << 27) - -#define USART_TXDOUBLEX_TXDATA1_SHIFT (16) -#define USART_TXDOUBLEX_TXDATA1_MASK \ - (0x1FF << USART_TXDOUBLEX_TXDATA1_SHIFT) - -#define USART_TXDOUBLEX_RXENAT0 (1 << 15) -#define USART_TXDOUBLEX_TXDISAT0 (1 << 14) -#define USART_TXDOUBLEX_TXBREAK0 (1 << 13) -#define USART_TXDOUBLEX_TXTRIAT0 (1 << 12) -#define USART_TXDOUBLEX_UBRXAT0 (1 << 11) - -#define USART_TXDOUBLEX_TXDATA0_SHIFT (0) -#define USART_TXDOUBLEX_TXDATA0_MASK \ - (0x1FF << USART_TXDOUBLEX_TXDATA0_SHIFT) - -/* USART_TXDOUBLE */ -#define USART_TXDOUBLE_TXDATA1_SHIFT (8) -#define USART_TXDOUBLE_TXDATA1_MASK (0xFF << USART_TXDOUBLE_TXDATA1_SHIFT) - -#define USART_TXDOUBLE_TXDATA0_SHIFT (0) -#define USART_TXDOUBLE_TXDATA0_MASK (0xFF << USART_TXDOUBLE_TXDATA0_SHIFT) - -/* USART_IF */ -#define USART_IF_CCF (1 << 12) -#define USART_IF_SSM (1 << 11) -#define USART_IF_MPAF (1 << 10) -#define USART_IF_FERR (1 << 9) -#define USART_IF_PERR (1 << 8) -#define USART_IF_TXUF (1 << 7) -#define USART_IF_TXOF (1 << 6) -#define USART_IF_RXUF (1 << 5) -#define USART_IF_RXOF (1 << 4) -#define USART_IF_RXFULL (1 << 3) -#define USART_IF_RXDATAV (1 << 2) -#define USART_IF_TXBL (1 << 1) -#define USART_IF_TXC (1 << 0) - -/* USART_IFS */ -#define USART_IFS_CCF (1 << 12) -#define USART_IFS_SSM (1 << 11) -#define USART_IFS_MPAF (1 << 10) -#define USART_IFS_FERR (1 << 9) -#define USART_IFS_PERR (1 << 8) -#define USART_IFS_TXUF (1 << 7) -#define USART_IFS_TXOF (1 << 6) -#define USART_IFS_RXUF (1 << 5) -#define USART_IFS_RXOF (1 << 4) -#define USART_IFS_RXFULL (1 << 3) -#define USART_IFS_RXDATAV (1 << 2) -#define USART_IFS_TXBL (1 << 1) -#define USART_IFS_TXC (1 << 0) - -/* USART_IFC */ -#define USART_IFC_CCF (1 << 12) -#define USART_IFC_SSM (1 << 11) -#define USART_IFC_MPAF (1 << 10) -#define USART_IFC_FERR (1 << 9) -#define USART_IFC_PERR (1 << 8) -#define USART_IFC_TXUF (1 << 7) -#define USART_IFC_TXOF (1 << 6) -#define USART_IFC_RXUF (1 << 5) -#define USART_IFC_RXOF (1 << 4) -#define USART_IFC_RXFULL (1 << 3) -#define USART_IFC_RXDATAV (1 << 2) -#define USART_IFC_TXBL (1 << 1) -#define USART_IFC_TXC (1 << 0) - -/* USART_IEN */ -#define USART_IEN_CCF (1 << 12) -#define USART_IEN_SSM (1 << 11) -#define USART_IEN_MPAF (1 << 10) -#define USART_IEN_FERR (1 << 9) -#define USART_IEN_PERR (1 << 8) -#define USART_IEN_TXUF (1 << 7) -#define USART_IEN_TXOF (1 << 6) -#define USART_IEN_RXUF (1 << 5) -#define USART_IEN_RXOF (1 << 4) -#define USART_IEN_RXFULL (1 << 3) -#define USART_IEN_RXDATAV (1 << 2) -#define USART_IEN_TXBL (1 << 1) -#define USART_IEN_TXC (1 << 0) - -/* USART_IRCTRL */ -#define USART_IRCTRL_IRPRSEN (1 << 7) - -#define USART_IRCTRL_IRPRSSEL_SHIFT (4) -#define USART_IRCTRL_IRPRSSEL_MASK (0x7 << USART_IRCTRL_IRPRSSEL_SHIFT) -#define USART_IRCTRL_IRPRSSEL(v) \ - (((v) << USART_IRCTRL_IRPRSSEL_SHIFT) & USART_IRCTRL_IRPRSSEL_MASK) -#define USART_IRCTRL_IRPRSSEL_PRSCHx(x) USART_IRCTRL_IRPRSSEL(x) -#define USART_IRCTRL_IRPRSSEL_PRSCH0 USART_IRCTRL_IRPRSSEL_PRSCHx(0) -#define USART_IRCTRL_IRPRSSEL_PRSCH1 USART_IRCTRL_IRPRSSEL_PRSCHx(1) -#define USART_IRCTRL_IRPRSSEL_PRSCH2 USART_IRCTRL_IRPRSSEL_PRSCHx(2) -#define USART_IRCTRL_IRPRSSEL_PRSCH3 USART_IRCTRL_IRPRSSEL_PRSCHx(3) -#define USART_IRCTRL_IRPRSSEL_PRSCH4 USART_IRCTRL_IRPRSSEL_PRSCHx(4) -#define USART_IRCTRL_IRPRSSEL_PRSCH5 USART_IRCTRL_IRPRSSEL_PRSCHx(5) -#define USART_IRCTRL_IRPRSSEL_PRSCH6 USART_IRCTRL_IRPRSSEL_PRSCHx(6) -#define USART_IRCTRL_IRPRSSEL_PRSCH7 USART_IRCTRL_IRPRSSEL_PRSCHx(7) - -#define USART_IRCTRL_IRFILT (1 << 3) - -#define USART_IRCTRL_IRPW_SHIFT (1) -#define USART_IRCTRL_IRPW_MASK (0x3 << USART_IRCTRL_IRPW_SHIFT) -#define USART_IRCTRL_IRPW(v) \ - (((v) << USART_IRCTRL_IRPW_SHIFT) & USART_IRCTRL_IRPW_MASK) -#define USART_IRCTRL_IRPW_ONE USART_IRCTRL_IRPW(0) -#define USART_IRCTRL_IRPW_TWO USART_IRCTRL_IRPW(1) -#define USART_IRCTRL_IRPW_THREE USART_IRCTRL_IRPW(2) -#define USART_IRCTRL_IRPW_FOUR USART_IRCTRL_IRPW(3) - -#define USART_IRCTRL_IREN (1 << 0) - -/* USART_ROUTE */ -#define USART_ROUTE_LOCATION_SHIFT (8) -#define USART_ROUTE_LOCATION_MASK (0x7 << USART_ROUTE_LOCATION_SHIFT) -#define USART_ROUTE_LOCATION(v) \ - (((v) << USART_ROUTE_LOCATION_SHIFT) & USART_ROUTE_LOCATION_MASK) -#define USART_ROUTE_LOCATION_LOCx(x) USART_ROUTE_LOCATION(x) -#define USART_ROUTE_LOCATION_LOC0 USART_ROUTE_LOCATION_LOCx(0) -#define USART_ROUTE_LOCATION_LOC1 USART_ROUTE_LOCATION_LOCx(1) -#define USART_ROUTE_LOCATION_LOC2 USART_ROUTE_LOCATION_LOCx(2) -#define USART_ROUTE_LOCATION_LOC3 USART_ROUTE_LOCATION_LOCx(3) -#define USART_ROUTE_LOCATION_LOC4 USART_ROUTE_LOCATION_LOCx(4) -#define USART_ROUTE_LOCATION_LOC5 USART_ROUTE_LOCATION_LOCx(5) - -#define USART_ROUTE_CLKPEN (1 << 3) -#define USART_ROUTE_CSPEN (1 << 2) -#define USART_ROUTE_TXPEN (1 << 1) -#define USART_ROUTE_RXPEN (1 << 0) - -/* USART_INPUT */ -#define USART_INPUT_RXPRS (1 << 4) - -#define USART_INPUT_RXPRSSEL_SHIFT (0) -#define USART_INPUT_RXPRSSEL_MASK (0xF << USART_INPUT_RXPRSSEL_SHIFT) -#define USART_INPUT_RXPRSSEL(v) \ - (((v) << USART_INPUT_RXPRSSEL_SHIFT) & USART_INPUT_RXPRSSEL_MASK) -#define USART_INPUT_RXPRSSEL_PRSCHx(x) USART_INPUT_RXPRSSEL(x) -#define USART_INPUT_RXPRSSEL_PRSCH0 USART_INPUT_RXPRSSEL_PRSCHx(0) -#define USART_INPUT_RXPRSSEL_PRSCH1 USART_INPUT_RXPRSSEL_PRSCHx(1) -#define USART_INPUT_RXPRSSEL_PRSCH2 USART_INPUT_RXPRSSEL_PRSCHx(2) -#define USART_INPUT_RXPRSSEL_PRSCH3 USART_INPUT_RXPRSSEL_PRSCHx(3) -#define USART_INPUT_RXPRSSEL_PRSCH4 USART_INPUT_RXPRSSEL_PRSCHx(4) -#define USART_INPUT_RXPRSSEL_PRSCH5 USART_INPUT_RXPRSSEL_PRSCHx(5) -#define USART_INPUT_RXPRSSEL_PRSCH6 USART_INPUT_RXPRSSEL_PRSCHx(6) -#define USART_INPUT_RXPRSSEL_PRSCH7 USART_INPUT_RXPRSSEL_PRSCHx(7) -#define USART_INPUT_RXPRSSEL_PRSCH8 USART_INPUT_RXPRSSEL_PRSCHx(8) -#define USART_INPUT_RXPRSSEL_PRSCH9 USART_INPUT_RXPRSSEL_PRSCHx(9) -#define USART_INPUT_RXPRSSEL_PRSCH10 USART_INPUT_RXPRSSEL_PRSCHx(10) -#define USART_INPUT_RXPRSSEL_PRSCH11 USART_INPUT_RXPRSSEL_PRSCHx(11) - -/* USART_I2SCTRL */ -#define USART_I2SCTRL_FORMAT_SHIFT (8) -#define USART_I2SCTRL_FORMAT_MASK (0x7 << USART_I2SCTRL_FORMAT_SHIFT) -#define USART_I2SCTRL_FORMAT(v) \ - (((v) << USART_I2SCTRL_FORMAT_SHIFT) & USART_I2SCTRL_FORMAT_MASK) -#define USART_I2SCTRL_FORMAT_W32D32 USART_I2SCTRL_FORMAT(0) -#define USART_I2SCTRL_FORMAT_W32D24M USART_I2SCTRL_FORMAT(1) -#define USART_I2SCTRL_FORMAT_W32D24 USART_I2SCTRL_FORMAT(2) -#define USART_I2SCTRL_FORMAT_W32D16 USART_I2SCTRL_FORMAT(3) -#define USART_I2SCTRL_FORMAT_W32D8 USART_I2SCTRL_FORMAT(4) -#define USART_I2SCTRL_FORMAT_W16D16 USART_I2SCTRL_FORMAT(5) -#define USART_I2SCTRL_FORMAT_W16D8 USART_I2SCTRL_FORMAT(6) -#define USART_I2SCTRL_FORMAT_W8D8 USART_I2SCTRL_FORMAT(7) - -#define USART_I2SCTRL_DELAY (1 << 4) -#define USART_I2SCTRL_DMASPLIT (1 << 3) -#define USART_I2SCTRL_JUSTIFY (1 << 2) -#define USART_I2SCTRL_MONO (1 << 1) -#define USART_I2SCTRL_EN (1 << 0) - -/* USART0 */ -#define USART0 USART0_BASE -#define USART0_CTRL USART_CTRL(USART0) -#define USART0_FRAME USART_FRAME(USART0) -#define USART0_TRIGCTRL USART_TRIGCTRL(USART0) -#define USART0_CMD USART_CMD(USART0) -#define USART0_STATUS USART_STATUS(USART0) -#define USART0_CLKDIV USART_CLKDIV(USART0) -#define USART0_RXDATAX USART_RXDATAX(USART0) -#define USART0_RXDATA USART_RXDATA(USART0) -#define USART0_RXDOUBLEX USART_RXDOUBLEX(USART0) -#define USART0_RXDOUBLE USART_RXDOUBLE(USART0) -#define USART0_RXDATAXP USART_RXDATAXP(USART0) -#define USART0_RXDOUBLEXP USART_RXDOUBLEXP(USART0) -#define USART0_TXDATAX USART_TXDATAX(USART0) -#define USART0_TXDATA USART_TXDATA(USART0) -#define USART0_TXDOUBLEX USART_TXDOUBLEX(USART0) -#define USART0_TXDOUBLE USART_TXDOUBLE(USART0) -#define USART0_IF USART_IF(USART0) -#define USART0_IFS USART_IFS(USART0) -#define USART0_IFC USART_IFC(USART0) -#define USART0_IEN USART_IEN(USART0) -#define USART0_IRCTRL USART_IRCTRL(USART0) -#define USART0_ROUTE USART_ROUTE(USART0) -#define USART0_INPUT USART_INPUT(USART0) -#define USART0_I2SCTRL USART_I2SCTRL(USART0) - -/* USART1 */ -#define USART1 USART1_BASE -#define USART1_CTRL USART_CTRL(USART1) -#define USART1_FRAME USART_FRAME(USART1) -#define USART1_TRIGCTRL USART_TRIGCTRL(USART1) -#define USART1_CMD USART_CMD(USART1) -#define USART1_STATUS USART_STATUS(USART1) -#define USART1_CLKDIV USART_CLKDIV(USART1) -#define USART1_RXDATAX USART_RXDATAX(USART1) -#define USART1_RXDATA USART_RXDATA(USART1) -#define USART1_RXDOUBLEX USART_RXDOUBLEX(USART1) -#define USART1_RXDOUBLE USART_RXDOUBLE(USART1) -#define USART1_RXDATAXP USART_RXDATAXP(USART1) -#define USART1_RXDOUBLEXP USART_RXDOUBLEXP(USART1) -#define USART1_TXDATAX USART_TXDATAX(USART1) -#define USART1_TXDATA USART_TXDATA(USART1) -#define USART1_TXDOUBLEX USART_TXDOUBLEX(USART1) -#define USART1_TXDOUBLE USART_TXDOUBLE(USART1) -#define USART1_IF USART_IF(USART1) -#define USART1_IFS USART_IFS(USART1) -#define USART1_IFC USART_IFC(USART1) -#define USART1_IEN USART_IEN(USART1) -#define USART1_IRCTRL USART_IRCTRL(USART1) -#define USART1_ROUTE USART_ROUTE(USART1) -#define USART1_INPUT USART_INPUT(USART1) -#define USART1_I2SCTRL USART_I2SCTRL(USART1) - -/* USART2 */ -#define USART2 USART2_BASE -#define USART2_CTRL USART_CTRL(USART2) -#define USART2_FRAME USART_FRAME(USART2) -#define USART2_TRIGCTRL USART_TRIGCTRL(USART2) -#define USART2_CMD USART_CMD(USART2) -#define USART2_STATUS USART_STATUS(USART2) -#define USART2_CLKDIV USART_CLKDIV(USART2) -#define USART2_RXDATAX USART_RXDATAX(USART2) -#define USART2_RXDATA USART_RXDATA(USART2) -#define USART2_RXDOUBLEX USART_RXDOUBLEX(USART2) -#define USART2_RXDOUBLE USART_RXDOUBLE(USART2) -#define USART2_RXDATAXP USART_RXDATAXP(USART2) -#define USART2_RXDOUBLEXP USART_RXDOUBLEXP(USART2) -#define USART2_TXDATAX USART_TXDATAX(USART2) -#define USART2_TXDATA USART_TXDATA(USART2) -#define USART2_TXDOUBLEX USART_TXDOUBLEX(USART2) -#define USART2_TXDOUBLE USART_TXDOUBLE(USART2) -#define USART2_IF USART_IF(USART2) -#define USART2_IFS USART_IFS(USART2) -#define USART2_IFC USART_IFC(USART2) -#define USART2_IEN USART_IEN(USART2) -#define USART2_IRCTRL USART_IRCTRL(USART2) -#define USART2_ROUTE USART_ROUTE(USART2) -#define USART2_INPUT USART_INPUT(USART2) -#define USART2_I2SCTRL USART_I2SCTRL(USART2) +#include #endif - diff --git a/include/libopencm3/efm32/lg/usb.h b/include/libopencm3/efm32/lg/usb.h index 891edbfb..1bb0a7b8 100644 --- a/include/libopencm3/efm32/lg/usb.h +++ b/include/libopencm3/efm32/lg/usb.h @@ -1,7 +1,7 @@ /* * This file is part of the libopencm3 project. * - * Copyright (C) 2015 Kuldeep Singh Dhaka + * Copyright (C) 2016 Bob Miller * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published by @@ -17,353 +17,9 @@ * along with this library. If not, see . */ -#ifndef LIBOPENCM3_EFM32_USB_H -#define LIBOPENCM3_EFM32_USB_H +#ifndef LIBOPENCM3_EFM32_LG_USB_H +#define LIBOPENCM3_EFM32_LG_USB_H -#include -#include - -#define USB_CTRL MMIO32(USB_BASE + 0x000) -#define USB_STATUS MMIO32(USB_BASE + 0x004) -#define USB_IF MMIO32(USB_BASE + 0x008) -#define USB_IFS MMIO32(USB_BASE + 0x00C) -#define USB_IFC MMIO32(USB_BASE + 0x010) -#define USB_IEN MMIO32(USB_BASE + 0x014) -#define USB_ROUTE MMIO32(USB_BASE + 0x018) - -/* USB_CTRL */ -#define USB_CTRL_DMPUAP (1 << 1) - -/* USB_ROUTE */ -#define USB_ROUTE_DMPUPEN (1 << 2) -#define USB_ROUTE_VBUSENPEN (1 << 1) -#define USB_ROUTE_PHYPEN (1 << 0) - -/* Core Global Control and Status Registers */ -#define USB_OTG_BASE (USB_BASE + 0x3C000) -#define USB_GOTGCTL MMIO32(USB_OTG_BASE + 0x000) -#define USB_GOTGINT MMIO32(USB_OTG_BASE + 0x004) -#define USB_GAHBCFG MMIO32(USB_OTG_BASE + 0x008) -#define USB_GUSBCFG MMIO32(USB_OTG_BASE + 0x00C) -#define USB_GRSTCTL MMIO32(USB_OTG_BASE + 0x010) -#define USB_GINTSTS MMIO32(USB_OTG_BASE + 0x014) -#define USB_GINTMSK MMIO32(USB_OTG_BASE + 0x018) -#define USB_GRXSTSR MMIO32(USB_OTG_BASE + 0x01C) -#define USB_GRXSTSP MMIO32(USB_OTG_BASE + 0x020) -#define USB_GRXFSIZ MMIO32(USB_OTG_BASE + 0x024) -#define USB_GNPTXFSIZ MMIO32(USB_OTG_BASE + 0x028) -#define USB_GNPTXSTS MMIO32(USB_OTG_BASE + 0x02C) -#define USB_GDFIFOCFG MMIO32(USB_OTG_BASE + 0x05C) -#define USB_HPTXFSIZ MMIO32(USB_OTG_BASE + 0x100) -#define USB_DIEPTXF(x) \ - MMIO32(USB_OTG_BASE + 0x104 + (4 * ((x) - 1))) - -/* Host-mode Control and Status Registers */ -#define USB_HCFG MMIO32(USB_OTG_BASE + 0x400) -#define USB_HFIR MMIO32(USB_OTG_BASE + 0x404) -#define USB_HFNUM MMIO32(USB_OTG_BASE + 0x408) -#define USB_HPTXSTS MMIO32(USB_OTG_BASE + 0x410) -#define USB_HAINT MMIO32(USB_OTG_BASE + 0x414) -#define USB_HAINTMSK MMIO32(USB_OTG_BASE + 0x418) -#define USB_HPRT MMIO32(USB_OTG_BASE + 0x440) -#define USB_HCx_CHAR(x) \ - MMIO32(USB_OTG_BASE + 0x500 + ((x) * 0x20)) -#define USB_HCx_INT(x) \ - MMIO32(USB_OTG_BASE + 0x508 + ((x) * 0x20)) -#define USB_HCx_INTMSK(x) \ - MMIO32(USB_OTG_BASE + 0x50C + ((x) * 0x20)) -#define USB_HCx_TSIZ(x) \ - MMIO32(USB_OTG_BASE + 0x510 + ((x) * 0x20)) -#define USB_HCx_DMAADDR(x) \ - MMIO32(USB_OTG_BASE + 0x514 + ((x) * 0x20)) - -/* Device-mode Control and Status Registers */ -#define USB_DCFG MMIO32(USB_OTG_BASE + 0x800) -#define USB_DCTL MMIO32(USB_OTG_BASE + 0x804) -#define USB_DSTS MMIO32(USB_OTG_BASE + 0x808) -#define USB_DIEPMSK MMIO32(USB_OTG_BASE + 0x810) -#define USB_DOEPMSK MMIO32(USB_OTG_BASE + 0x814) -#define USB_DAINT MMIO32(USB_OTG_BASE + 0x818) -#define USB_DAINTMSK MMIO32(USB_OTG_BASE + 0x81C) -#define USB_DVBUSDIS MMIO32(USB_OTG_BASE + 0x828) -#define USB_DVBUSPULSE MMIO32(USB_OTG_BASE + 0x82C) -#define USB_DIEPEMPMSK MMIO32(USB_OTG_BASE + 0x834) - -#define USB_DIEPx_CTL(x) \ - MMIO32(USB_OTG_BASE + 0x900 + ((x) * 0x20)) -#define USB_DIEPx_INT(x) \ - MMIO32(USB_OTG_BASE + 0x908 + ((x) * 0x20)) -#define USB_DIEPx_TSIZ(x) \ - MMIO32(USB_OTG_BASE + 0x910 + ((x) * 0x20)) -#define USB_DIEP0CTL USB_DIEPx_CTL(0) -#define USB_DIEP0TSIZ USB_DIEPx_TSIZ(0) -#define USB_DIEP0INT USB_DIEPx_INT(0) - -#define USB_DOEPx_CTL(x) \ - MMIO32(USB_OTG_BASE + 0xB00 + ((x) * 0x20)) -#define USB_DOEPx_INT(x) \ - MMIO32(USB_OTG_BASE + 0xB08 + ((x) * 0x20)) -#define USB_DOEPx_TSIZ(x) \ - MMIO32(USB_OTG_BASE + 0xB10 + ((x) * 0x20)) -#define USB_DOEP0CTL USB_DOEPx_CTL(0) -#define USB_DOEP0TSIZ USB_DOEPx_TSIZ(0) -#define USB_DOEP0INT USB_DOEPx_INT(0) - -/* Power and clock gating control and status register */ -#define USB_PCGCCTL MMIO32(USB_OTG_BASE + 0xE00) - -/* Data FIFO */ -#define USB_FIFOxD(x) \ - (&MMIO32(USB_OTG_BASE + (((x) + 1) << 12))) - -/* Global CSRs */ -/* USB control registers (OTG_HS_GOTGCTL) */ -#define USB_GOTGCTL_BSVLD (1 << 19) -#define USB_GOTGCTL_ASVLD (1 << 18) -#define USB_GOTGCTL_DBCT (1 << 17) -#define USB_GOTGCTL_CIDSTS (1 << 16) -#define USB_GOTGCTL_DHNPEN (1 << 11) -#define USB_GOTGCTL_HSHNPEN (1 << 10) -#define USB_GOTGCTL_HNPRQ (1 << 9) -#define USB_GOTGCTL_HNGSCS (1 << 8) -#define USB_GOTGCTL_SRQ (1 << 1) -#define USB_GOTGCTL_SRQSCS (1 << 0) - -/* AHB configuration register (USB_GAHBCFG) */ -#define USB_GAHBCFG_GLBLINTRMSK 0x0001 -#define USB_GAHBCFG_TXFELVL 0x0080 -#define USB_GAHBCFG_PTXFELVL 0x0100 - -/* USB configuration register (USB_GUSBCFG) */ -#define USB_GUSBCFG_TOCAL 0x00000003 -#define USB_GUSBCFG_SRPCAP 0x00000100 -#define USB_GUSBCFG_HNPCAP 0x00000200 -#define USB_GUSBCFG_TRDT_MASK (0xf << 10) -#define USB_GUSBCFG_TRDT_16BIT (0x5 << 10) -#define USB_GUSBCFG_TRDT_8BIT (0x9 << 10) -#define USB_GUSBCFG_NPTXRWEN 0x00004000 -#define USB_GUSBCFG_FHMOD 0x20000000 -#define USB_GUSBCFG_FDMOD 0x40000000 -#define USB_GUSBCFG_CTXPKT 0x80000000 -#define USB_GUSBCFG_PHYSEL (1 << 7) - -/* reset register (USB_GRSTCTL) */ -#define USB_GRSTCTL_AHBIDL (1 << 31) -/* Bits 30:11 - Reserved */ -#define USB_GRSTCTL_TXFNUM_MASK (0x1f << 6) -#define USB_GRSTCTL_TXFFLSH (1 << 5) -#define USB_GRSTCTL_RXFFLSH (1 << 4) -/* Bit 3 - Reserved */ -#define USB_GRSTCTL_FCRST (1 << 2) -#define USB_GRSTCTL_HSRST (1 << 1) -#define USB_GRSTCTL_CSRST (1 << 0) - -/* interrupt status register (USB_GINTSTS) */ -#define USB_GINTSTS_WKUPINT (1 << 31) -#define USB_GINTSTS_SRQINT (1 << 30) -#define USB_GINTSTS_DISCINT (1 << 29) -#define USB_GINTSTS_CIDSCHG (1 << 28) -/* Bit 27 - Reserved */ -#define USB_GINTSTS_PTXFE (1 << 26) -#define USB_GINTSTS_HCINT (1 << 25) -#define USB_GINTSTS_HPRTINT (1 << 24) -/* Bits 23:22 - Reserved */ -#define USB_GINTSTS_IPXFR (1 << 21) -#define USB_GINTSTS_INCOMPISOOUT (1 << 21) -#define USB_GINTSTS_IISOIXFR (1 << 20) -#define USB_GINTSTS_OEPINT (1 << 19) -#define USB_GINTSTS_IEPINT (1 << 18) -/* Bits 17:16 - Reserved */ -#define USB_GINTSTS_EOPF (1 << 15) -#define USB_GINTSTS_ISOODRP (1 << 14) -#define USB_GINTSTS_ENUMDNE (1 << 13) -#define USB_GINTSTS_USBRST (1 << 12) -#define USB_GINTSTS_USBSUSP (1 << 11) -#define USB_GINTSTS_ESUSP (1 << 10) -/* Bits 9:8 - Reserved */ -#define USB_GINTSTS_GONAKEFF (1 << 7) -#define USB_GINTSTS_GINAKEFF (1 << 6) -#define USB_GINTSTS_NPTXFE (1 << 5) -#define USB_GINTSTS_RXFLVL (1 << 4) -#define USB_GINTSTS_SOF (1 << 3) -#define USB_GINTSTS_OTGINT (1 << 2) -#define USB_GINTSTS_MMIS (1 << 1) -#define USB_GINTSTS_CMOD (1 << 0) - -/* interrupt mask register (USB_GINTMSK) */ -#define USB_GINTMSK_MMISM 0x00000002 -#define USB_GINTMSK_OTGINT 0x00000004 -#define USB_GINTMSK_SOFM 0x00000008 -#define USB_GINTMSK_RXFLVLM 0x00000010 -#define USB_GINTMSK_NPTXFEM 0x00000020 -#define USB_GINTMSK_GINAKEFFM 0x00000040 -#define USB_GINTMSK_GONAKEFFM 0x00000080 -#define USB_GINTMSK_ESUSPM 0x00000400 -#define USB_GINTMSK_USBSUSPM 0x00000800 -#define USB_GINTMSK_USBRST 0x00001000 -#define USB_GINTMSK_ENUMDNEM 0x00002000 -#define USB_GINTMSK_ISOODRPM 0x00004000 -#define USB_GINTMSK_EOPFM 0x00008000 -#define USB_GINTMSK_EPMISM 0x00020000 -#define USB_GINTMSK_IEPINT 0x00040000 -#define USB_GINTMSK_OEPINT 0x00080000 -#define USB_GINTMSK_IISOIXFRM 0x00100000 -#define USB_GINTMSK_IISOOXFRM 0x00200000 -#define USB_GINTMSK_IPXFRM 0x00200000 -#define USB_GINTMSK_PRTIM 0x01000000 -#define USB_GINTMSK_HCIM 0x02000000 -#define USB_GINTMSK_PTXFEM 0x04000000 -#define USB_GINTMSK_CIDSCHGM 0x10000000 -#define USB_GINTMSK_DISCINT 0x20000000 -#define USB_GINTMSK_SRQIM 0x40000000 -#define USB_GINTMSK_WUIM 0x80000000 - -/* Receive Status Pop Register (USB_GRXSTSP) */ -/* Bits 31:25 - Reserved */ -#define USB_GRXSTSP_FRMNUM_MASK (0xf << 21) -#define USB_GRXSTSP_PKTSTS_MASK (0xf << 17) -#define USB_GRXSTSP_PKTSTS_GOUTNAK (0x1 << 17) -#define USB_GRXSTSP_PKTSTS_OUT (0x2 << 17) -#define USB_GRXSTSP_PKTSTS_OUT_COMP (0x3 << 17) -#define USB_GRXSTSP_PKTSTS_SETUP_COMP (0x4 << 17) -#define USB_GRXSTSP_PKTSTS_SETUP (0x6 << 17) -#define USB_GRXSTSP_DPID_MASK (0x3 << 15) -#define USB_GRXSTSP_DPID_DATA0 (0x0 << 15) -#define USB_GRXSTSP_DPID_DATA1 (0x2 << 15) -#define USB_GRXSTSP_DPID_DATA2 (0x1 << 15) -#define USB_GRXSTSP_DPID_MDATA (0x3 << 15) -#define USB_GRXSTSP_BCNT_MASK (0x7ff << 4) -#define USB_GRXSTSP_EPNUM_MASK (0xf << 0) - -/* general core configuration register (USB_GCCFG) */ -/* Bits 31:22 - Reserved */ -#define USB_GCCFG_NOVBUSSENS (1 << 21) -#define USB_GCCFG_SOFOUTEN (1 << 20) -#define USB_GCCFG_VBUSBSEN (1 << 19) -#define USB_GCCFG_VBUSASEN (1 << 18) -/* Bit 17 - Reserved */ -#define USB_GCCFG_PWRDWN (1 << 16) -/* Bits 15:0 - Reserved */ - - -/* Device-mode CSRs */ -/* device control register (USB_DCTL) */ -/* Bits 31:12 - Reserved */ -#define USB_DCTL_POPRGDNE (1 << 11) -#define USB_DCTL_CGONAK (1 << 10) -#define USB_DCTL_SGONAK (1 << 9) -#define USB_DCTL_SGINAK (1 << 8) -#define USB_DCTL_TCTL_MASK (7 << 4) -#define USB_DCTL_GONSTS (1 << 3) -#define USB_DCTL_GINSTS (1 << 2) -#define USB_DCTL_SDIS (1 << 1) -#define USB_DCTL_RWUSIG (1 << 0) - -/* device configuration register (USB_DCFG) */ -#define USB_DCFG_DSPD 0x0003 -#define USB_DCFG_NZLSOHSK 0x0004 -#define USB_DCFG_DAD 0x07F0 -#define USB_DCFG_PFIVL 0x1800 - -/* Device IN Endpoint Common Interrupt Mask Register (USB_DIEPMSK) */ -/* Bits 31:10 - Reserved */ -#define USB_DIEPMSK_BIM (1 << 9) -#define USB_DIEPMSK_TXFURM (1 << 8) -/* Bit 7 - Reserved */ -#define USB_DIEPMSK_INEPNEM (1 << 6) -#define USB_DIEPMSK_INEPNMM (1 << 5) -#define USB_DIEPMSK_ITTXFEMSK (1 << 4) -#define USB_DIEPMSK_TOM (1 << 3) -/* Bit 2 - Reserved */ -#define USB_DIEPMSK_EPDM (1 << 1) -#define USB_DIEPMSK_XFRCM (1 << 0) - -/* Device OUT Endpoint Common Interrupt Mask Register (USB_DOEPMSK) */ -/* Bits 31:10 - Reserved */ -#define USB_DOEPMSK_BOIM (1 << 9) -#define USB_DOEPMSK_OPEM (1 << 8) -/* Bit 7 - Reserved */ -#define USB_DOEPMSK_B2BSTUP (1 << 6) -/* Bit 5 - Reserved */ -#define USB_DOEPMSK_OTEPDM (1 << 4) -#define USB_DOEPMSK_STUPM (1 << 3) -/* Bit 2 - Reserved */ -#define USB_DOEPMSK_EPDM (1 << 1) -#define USB_DOEPMSK_XFRCM (1 << 0) - -/* Device Control IN Endpoint 0 Control Register (USB_DIEP0CTL) */ -#define USB_DIEP0CTL_EPENA (1 << 31) -#define USB_DIEP0CTL_EPDIS (1 << 30) -/* Bits 29:28 - Reserved */ -#define USB_DIEP0CTL_SD0PID (1 << 28) -#define USB_DIEP0CTL_SNAK (1 << 27) -#define USB_DIEP0CTL_CNAK (1 << 26) -#define USB_DIEP0CTL_TXFNUM_MASK (0xf << 22) -#define USB_DIEP0CTL_STALL (1 << 21) -/* Bit 20 - Reserved */ -#define USB_DIEP0CTL_EPTYP_MASK (0x3 << 18) -#define USB_DIEP0CTL_NAKSTS (1 << 17) -/* Bit 16 - Reserved */ -#define USB_DIEP0CTL_USBAEP (1 << 15) -/* Bits 14:2 - Reserved */ -#define USB_DIEP0CTL_MPSIZ_MASK (0x3 << 0) -#define USB_DIEP0CTL_MPSIZ_64 (0x0 << 0) -#define USB_DIEP0CTL_MPSIZ_32 (0x1 << 0) -#define USB_DIEP0CTL_MPSIZ_16 (0x2 << 0) -#define USB_DIEP0CTL_MPSIZ_8 (0x3 << 0) - -/* Device Control OUT Endpoint 0 Control Register (USB_DOEP0CTL) */ -#define USB_DOEP0CTL_EPENA (1 << 31) -#define USB_DOEP0CTL_EPDIS (1 << 30) -/* Bits 29:28 - Reserved */ -#define USB_DOEP0CTL_SD0PID (1 << 28) -#define USB_DOEP0CTL_SNAK (1 << 27) -#define USB_DOEP0CTL_CNAK (1 << 26) -/* Bits 25:22 - Reserved */ -#define USB_DOEP0CTL_STALL (1 << 21) -#define USB_DOEP0CTL_SNPM (1 << 20) -#define USB_DOEP0CTL_EPTYP_MASK (0x3 << 18) -#define USB_DOEP0CTL_NAKSTS (1 << 17) -/* Bit 16 - Reserved */ -#define USB_DOEP0CTL_USBAEP (1 << 15) -/* Bits 14:2 - Reserved */ -#define USB_DOEP0CTL_MPSIZ_MASK (0x3 << 0) -#define USB_DOEP0CTL_MPSIZ_64 (0x0 << 0) -#define USB_DOEP0CTL_MPSIZ_32 (0x1 << 0) -#define USB_DOEP0CTL_MPSIZ_16 (0x2 << 0) -#define USB_DOEP0CTL_MPSIZ_8 (0x3 << 0) - -/* Device IN Endpoint Interrupt Register (USB_DIEPINTx) */ -/* Bits 31:8 - Reserved */ -#define USB_DIEP_INT_TXFE (1 << 7) -#define USB_DIEP_INT_INEPNE (1 << 6) -/* Bit 5 - Reserved */ -#define USB_DIEP_INT_ITTXFE (1 << 4) -#define USB_DIEP_INT_TOC (1 << 3) -/* Bit 2 - Reserved */ -#define USB_DIEP_INT_EPDISD (1 << 1) -#define USB_DIEP_INT_XFRC (1 << 0) - -/* Device IN Endpoint Interrupt Register (USB_DOEPINTx) */ -/* Bits 31:7 - Reserved */ -#define USB_DOEP_INT_B2BSTUP (1 << 6) -/* Bit 5 - Reserved */ -#define USB_DOEP_INT_OTEPDIS (1 << 4) -#define USB_DOEP_INT_SETUP (1 << 3) -/* Bit 2 - Reserved */ -#define USB_DOEP_INT_EPDISD (1 << 1) -#define USB_DOEP_INT_XFRC (1 << 0) - -/* Device OUT Endpoint 0 Transfer Size Register (USB_DOEP0TSIZ) */ -/* Bit 31 - Reserved */ -#define USB_DIEP0TSIZ_STUPCNT_1 (0x1 << 29) -#define USB_DIEP0TSIZ_STUPCNT_2 (0x2 << 29) -#define USB_DIEP0TSIZ_STUPCNT_3 (0x3 << 29) -#define USB_DIEP0TSIZ_STUPCNT_MASK (0x3 << 29) -/* Bits 28:20 - Reserved */ -#define USB_DIEP0TSIZ_PKTCNT (1 << 19) -/* Bits 18:7 - Reserved */ -#define USB_DIEP0TSIZ_XFRSIZ_MASK (0x7f << 0) +#include #endif - diff --git a/include/libopencm3/efm32/lg/wdog.h b/include/libopencm3/efm32/lg/wdog.h index 2eb8a478..ea9a4812 100644 --- a/include/libopencm3/efm32/lg/wdog.h +++ b/include/libopencm3/efm32/lg/wdog.h @@ -18,6 +18,6 @@ #ifndef LIBOPENCM3_WDOG_H #define LIBOPENCM3_WDOG_H -#include +#include #endif diff --git a/lib/efm32/lg/adc.c b/lib/efm32/common/adc_common.c similarity index 100% rename from lib/efm32/lg/adc.c rename to lib/efm32/common/adc_common.c diff --git a/lib/efm32/lg/cmu.c b/lib/efm32/common/cmu_common.c similarity index 100% rename from lib/efm32/lg/cmu.c rename to lib/efm32/common/cmu_common.c diff --git a/lib/efm32/lg/dac.c b/lib/efm32/common/dac_common.c similarity index 100% rename from lib/efm32/lg/dac.c rename to lib/efm32/common/dac_common.c diff --git a/lib/efm32/lg/dma.c b/lib/efm32/common/dma_common.c similarity index 100% rename from lib/efm32/lg/dma.c rename to lib/efm32/common/dma_common.c diff --git a/lib/efm32/common/gpio_common_hglg.c b/lib/efm32/common/gpio_common.c similarity index 100% rename from lib/efm32/common/gpio_common_hglg.c rename to lib/efm32/common/gpio_common.c diff --git a/lib/efm32/lg/prs.c b/lib/efm32/common/prs_common.c similarity index 100% rename from lib/efm32/lg/prs.c rename to lib/efm32/common/prs_common.c diff --git a/lib/efm32/common/timer_common_hglg.c b/lib/efm32/common/timer_common.c similarity index 98% rename from lib/efm32/common/timer_common_hglg.c rename to lib/efm32/common/timer_common.c index 0a67b6b8..22664954 100644 --- a/lib/efm32/common/timer_common_hglg.c +++ b/lib/efm32/common/timer_common.c @@ -47,7 +47,7 @@ void timer_stop(uint32_t timer) void timer_set_clock_prescaler(uint32_t timer, uint32_t presc) { TIMER_CTRL(timer) = (TIMER_CTRL(timer) & ~TIMER_CTRL_PRESC_MASK) - | presc; + | TIMER_CTRL_PRESC(presc); } /** diff --git a/lib/efm32/hg/Makefile b/lib/efm32/hg/Makefile index 8628a1a5..f5b897d8 100644 --- a/lib/efm32/hg/Makefile +++ b/lib/efm32/hg/Makefile @@ -40,7 +40,7 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs -OBJS = cmu.o gpio_common_hglg.o timer_common_hglg.o +OBJS = cmu.o gpio_common.o timer_common.o OBJS += usb.o usb_control.o usb_standard.o usb_msc.o \ usb_dwc_common.o usb_efm32hg.o diff --git a/lib/efm32/lg/Makefile b/lib/efm32/lg/Makefile index fc301176..0d4bf4a1 100644 --- a/lib/efm32/lg/Makefile +++ b/lib/efm32/lg/Makefile @@ -40,8 +40,12 @@ TGT_CFLAGS += $(STANDARD_FLAGS) ARFLAGS = rcs OBJS = -OBJS = gpio_common_hglg.o timer_common_hglg.o cmu.o prs.o adc.o dma.o dac.o -OBJS += usb.o usb_control.o usb_standard.o usb_efm32lg.o +OBJS = gpio_common.o cmu_common.o prs_common.o +OBJS += adc_common.o dma_common.o timer_common.o +OBJS += dac_common.o + +OBJS += usb.o usb_control.o usb_standard.o +OBJS += usb_efm32.o VPATH += ../../usb:../:../../cm3:../common diff --git a/lib/usb/usb_efm32lg.c b/lib/usb/usb_efm32.c similarity index 100% rename from lib/usb/usb_efm32lg.c rename to lib/usb/usb_efm32.c