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Fixed typo in SGPIO_MUX_CFGx CLK_SOURCE_SLICE_MODE bit offset and width.

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This commit is contained in:
Jared Boone 2012-10-11 16:28:56 -07:00 committed by Piotr Esden-Tempski
parent 18d72099a5
commit 5359dd245e
1 changed files with 16 additions and 16 deletions
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32
scripts/data/lpc43xx/sgpio.csv
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@ -32,7 +32,7 @@ SGPIO_OUT_MUX_CFG15,0,4,P_OUT_CFG,Output control of output SGPIOn,0,rw
SGPIO_OUT_MUX_CFG15,4,3,P_OE_CFG,Output enable source,0,rw
SGPIO_MUX_CFG0,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG0,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG0,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG0,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG0,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG0,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG0,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
@ -40,7 +40,7 @@ SGPIO_MUX_CFG0,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG0,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG1,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG1,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG1,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG1,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG1,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG1,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG1,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
@ -48,7 +48,7 @@ SGPIO_MUX_CFG1,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG1,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG2,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG2,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG2,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG2,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG2,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG2,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG2,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
@ -56,7 +56,7 @@ SGPIO_MUX_CFG2,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG2,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG3,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG3,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG3,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG3,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG3,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG3,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG3,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
@ -64,7 +64,7 @@ SGPIO_MUX_CFG3,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG3,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG4,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG4,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG4,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG4,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG4,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG4,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG4,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
@ -72,7 +72,7 @@ SGPIO_MUX_CFG4,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG4,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG5,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG5,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG5,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG5,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG5,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG5,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG5,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
@ -80,7 +80,7 @@ SGPIO_MUX_CFG5,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG5,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG6,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG6,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG6,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG6,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG6,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG6,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG6,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
@ -88,7 +88,7 @@ SGPIO_MUX_CFG6,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG6,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG7,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG7,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG7,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG7,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG7,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG7,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG7,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
@ -96,7 +96,7 @@ SGPIO_MUX_CFG7,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG7,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG8,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG8,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG8,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG8,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG8,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG8,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG8,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
@ -104,7 +104,7 @@ SGPIO_MUX_CFG8,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG8,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG9,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG9,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG9,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG9,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG9,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG9,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG9,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
@ -112,7 +112,7 @@ SGPIO_MUX_CFG9,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG9,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG10,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG10,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG10,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG10,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG10,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG10,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG10,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
@ -120,7 +120,7 @@ SGPIO_MUX_CFG10,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG10,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG11,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG11,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG11,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG11,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG11,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG11,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG11,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
@ -128,7 +128,7 @@ SGPIO_MUX_CFG11,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG11,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG12,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG12,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG12,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG12,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG12,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG12,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG12,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
@ -136,7 +136,7 @@ SGPIO_MUX_CFG12,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG12,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG13,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG13,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG13,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG13,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG13,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG13,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG13,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
@ -144,7 +144,7 @@ SGPIO_MUX_CFG13,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG13,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG14,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG14,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG14,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG14,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG14,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG14,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG14,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw
@ -152,7 +152,7 @@ SGPIO_MUX_CFG14,11,1,CONCAT_ENABLE,Enable concatenation,0,rw
SGPIO_MUX_CFG14,12,2,CONCAT_ORDER,Select concatenation order,0,rw
SGPIO_MUX_CFG15,0,1,EXT_CLK_ENABLE,Select clock signal,0,rw
SGPIO_MUX_CFG15,1,2,CLK_SOURCE_PIN_MODE,Select source clock pin,0,rw
SGPIO_MUX_CFG15,4,3,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG15,3,2,CLK_SOURCE_SLICE_MODE,Select clock source slice,0,rw
SGPIO_MUX_CFG15,5,2,QUALIFIER_MODE,Select qualifier mode,0,rw
SGPIO_MUX_CFG15,7,2,QUALIFIER_PIN_MODE,Select qualifier pin,0,rw
SGPIO_MUX_CFG15,9,2,QUALIFIER_SLICE_MODE,Select qualifier slice,0,rw

1 SGPIO_OUT_MUX_CFG0 0 4 P_OUT_CFG Output control of output SGPIOn 0 rw
32 SGPIO_OUT_MUX_CFG15 4 3 P_OE_CFG Output enable source 0 rw
33 SGPIO_MUX_CFG0 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
34 SGPIO_MUX_CFG0 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
35 SGPIO_MUX_CFG0 4 3 3 2 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
36 SGPIO_MUX_CFG0 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
37 SGPIO_MUX_CFG0 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
38 SGPIO_MUX_CFG0 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
40 SGPIO_MUX_CFG0 12 2 CONCAT_ORDER Select concatenation order 0 rw
41 SGPIO_MUX_CFG1 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
42 SGPIO_MUX_CFG1 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
43 SGPIO_MUX_CFG1 4 3 3 2 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
44 SGPIO_MUX_CFG1 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
45 SGPIO_MUX_CFG1 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
46 SGPIO_MUX_CFG1 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
48 SGPIO_MUX_CFG1 12 2 CONCAT_ORDER Select concatenation order 0 rw
49 SGPIO_MUX_CFG2 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
50 SGPIO_MUX_CFG2 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
51 SGPIO_MUX_CFG2 4 3 3 2 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
52 SGPIO_MUX_CFG2 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
53 SGPIO_MUX_CFG2 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
54 SGPIO_MUX_CFG2 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
56 SGPIO_MUX_CFG2 12 2 CONCAT_ORDER Select concatenation order 0 rw
57 SGPIO_MUX_CFG3 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
58 SGPIO_MUX_CFG3 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
59 SGPIO_MUX_CFG3 4 3 3 2 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
60 SGPIO_MUX_CFG3 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
61 SGPIO_MUX_CFG3 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
62 SGPIO_MUX_CFG3 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
64 SGPIO_MUX_CFG3 12 2 CONCAT_ORDER Select concatenation order 0 rw
65 SGPIO_MUX_CFG4 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
66 SGPIO_MUX_CFG4 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
67 SGPIO_MUX_CFG4 4 3 3 2 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
68 SGPIO_MUX_CFG4 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
69 SGPIO_MUX_CFG4 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
70 SGPIO_MUX_CFG4 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
72 SGPIO_MUX_CFG4 12 2 CONCAT_ORDER Select concatenation order 0 rw
73 SGPIO_MUX_CFG5 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
74 SGPIO_MUX_CFG5 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
75 SGPIO_MUX_CFG5 4 3 3 2 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
76 SGPIO_MUX_CFG5 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
77 SGPIO_MUX_CFG5 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
78 SGPIO_MUX_CFG5 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
80 SGPIO_MUX_CFG5 12 2 CONCAT_ORDER Select concatenation order 0 rw
81 SGPIO_MUX_CFG6 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
82 SGPIO_MUX_CFG6 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
83 SGPIO_MUX_CFG6 4 3 3 2 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
84 SGPIO_MUX_CFG6 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
85 SGPIO_MUX_CFG6 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
86 SGPIO_MUX_CFG6 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
88 SGPIO_MUX_CFG6 12 2 CONCAT_ORDER Select concatenation order 0 rw
89 SGPIO_MUX_CFG7 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
90 SGPIO_MUX_CFG7 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
91 SGPIO_MUX_CFG7 4 3 3 2 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
92 SGPIO_MUX_CFG7 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
93 SGPIO_MUX_CFG7 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
94 SGPIO_MUX_CFG7 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
96 SGPIO_MUX_CFG7 12 2 CONCAT_ORDER Select concatenation order 0 rw
97 SGPIO_MUX_CFG8 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
98 SGPIO_MUX_CFG8 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
99 SGPIO_MUX_CFG8 4 3 3 2 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
100 SGPIO_MUX_CFG8 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
101 SGPIO_MUX_CFG8 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
102 SGPIO_MUX_CFG8 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
104 SGPIO_MUX_CFG8 12 2 CONCAT_ORDER Select concatenation order 0 rw
105 SGPIO_MUX_CFG9 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
106 SGPIO_MUX_CFG9 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
107 SGPIO_MUX_CFG9 4 3 3 2 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
108 SGPIO_MUX_CFG9 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
109 SGPIO_MUX_CFG9 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
110 SGPIO_MUX_CFG9 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
112 SGPIO_MUX_CFG9 12 2 CONCAT_ORDER Select concatenation order 0 rw
113 SGPIO_MUX_CFG10 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
114 SGPIO_MUX_CFG10 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
115 SGPIO_MUX_CFG10 4 3 3 2 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
116 SGPIO_MUX_CFG10 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
117 SGPIO_MUX_CFG10 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
118 SGPIO_MUX_CFG10 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
120 SGPIO_MUX_CFG10 12 2 CONCAT_ORDER Select concatenation order 0 rw
121 SGPIO_MUX_CFG11 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
122 SGPIO_MUX_CFG11 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
123 SGPIO_MUX_CFG11 4 3 3 2 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
124 SGPIO_MUX_CFG11 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
125 SGPIO_MUX_CFG11 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
126 SGPIO_MUX_CFG11 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
128 SGPIO_MUX_CFG11 12 2 CONCAT_ORDER Select concatenation order 0 rw
129 SGPIO_MUX_CFG12 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
130 SGPIO_MUX_CFG12 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
131 SGPIO_MUX_CFG12 4 3 3 2 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
132 SGPIO_MUX_CFG12 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
133 SGPIO_MUX_CFG12 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
134 SGPIO_MUX_CFG12 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
136 SGPIO_MUX_CFG12 12 2 CONCAT_ORDER Select concatenation order 0 rw
137 SGPIO_MUX_CFG13 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
138 SGPIO_MUX_CFG13 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
139 SGPIO_MUX_CFG13 4 3 3 2 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
140 SGPIO_MUX_CFG13 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
141 SGPIO_MUX_CFG13 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
142 SGPIO_MUX_CFG13 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
144 SGPIO_MUX_CFG13 12 2 CONCAT_ORDER Select concatenation order 0 rw
145 SGPIO_MUX_CFG14 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
146 SGPIO_MUX_CFG14 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
147 SGPIO_MUX_CFG14 4 3 3 2 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
148 SGPIO_MUX_CFG14 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
149 SGPIO_MUX_CFG14 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
150 SGPIO_MUX_CFG14 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw
152 SGPIO_MUX_CFG14 12 2 CONCAT_ORDER Select concatenation order 0 rw
153 SGPIO_MUX_CFG15 0 1 EXT_CLK_ENABLE Select clock signal 0 rw
154 SGPIO_MUX_CFG15 1 2 CLK_SOURCE_PIN_MODE Select source clock pin 0 rw
155 SGPIO_MUX_CFG15 4 3 3 2 CLK_SOURCE_SLICE_MODE Select clock source slice 0 rw
156 SGPIO_MUX_CFG15 5 2 QUALIFIER_MODE Select qualifier mode 0 rw
157 SGPIO_MUX_CFG15 7 2 QUALIFIER_PIN_MODE Select qualifier pin 0 rw
158 SGPIO_MUX_CFG15 9 2 QUALIFIER_SLICE_MODE Select qualifier slice 0 rw