From b9249ca8a65b063d4f175c096eeafa483f31b241 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Thu, 27 Jun 2019 12:00:24 +0200 Subject: [PATCH 1/2] stlinkv2: Recognize V21_MSD, e.g. on STM32MP157C-DK2. --- src/platforms/pc-stlinkv2/stlinkv2.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/platforms/pc-stlinkv2/stlinkv2.c b/src/platforms/pc-stlinkv2/stlinkv2.c index 1d76c9f7..eadc42df 100644 --- a/src/platforms/pc-stlinkv2/stlinkv2.c +++ b/src/platforms/pc-stlinkv2/stlinkv2.c @@ -49,7 +49,7 @@ #endif #define VENDOR_ID_STLINK 0x483 -#define PRODUCT_ID_STLINK_MASK 0xfff0 +#define PRODUCT_ID_STLINK_MASK 0xffe0 #define PRODUCT_ID_STLINK_GROUP 0x3740 #define PRODUCT_ID_STLINKV1 0x3744 #define PRODUCT_ID_STLINKV2 0x3748 @@ -733,6 +733,10 @@ void stlink_init(int argc, char **argv) DEBUG("STLINKV21 serial %s\n", Stlink.serial); Stlink.ver_hw = 21; Stlink.ep_tx = 1; + } else if (desc.idProduct == PRODUCT_ID_STLINKV21_MSD) { + DEBUG("STLINKV21_MSD serial %s\n", Stlink.serial); + Stlink.ver_hw = 21; + Stlink.ep_tx = 1; } else if (desc.idProduct == PRODUCT_ID_STLINKV3E) { DEBUG("STLINKV3E serial %s\n", Stlink.serial); Stlink.ver_hw = 30; From 9e898cc4b8f3e1a5844a3693412a9977a65a0a63 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Thu, 18 Jul 2019 17:10:48 +0200 Subject: [PATCH 2/2] adiv5: Add more coresight part numbers found on STM32MP157c-DK2 (#492). Only print corename if not NULL. --- src/command.c | 3 ++- src/target/adiv5.c | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/command.c b/src/command.c index 85b77a0b..ff7bce91 100644 --- a/src/command.c +++ b/src/command.c @@ -226,7 +226,8 @@ static void display_target(int i, target *t, void *context) { (void)context; gdb_outf("%2d %c %s %s\n", i, target_attached(t)?'*':' ', - target_driver_name(t), target_core_name(t)); + target_driver_name(t), + (target_core_name(t)) ? target_core_name(t): ""); } bool cmd_targets(void) diff --git a/src/target/adiv5.c b/src/target/adiv5.c index a959f197..acf81119 100644 --- a/src/target/adiv5.c +++ b/src/target/adiv5.c @@ -195,9 +195,11 @@ static const struct { {0x941, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight TPIU-Lite", "(Trace Port Interface Unit)")}, {0x950, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight Component", "(unidentified Cortex-A9 component)")}, {0x955, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight Component", "(unidentified Cortex-A5 component)")}, + {0x956, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A7 ETM", "(Embedded Trace)")}, {0x95f, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-A15 PTM", "(Program Trace Macrocell)")}, {0x961, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight TMC", "(Trace Memory Controller)")}, {0x962, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight STM", "(System Trace Macrocell)")}, + {0x963, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight STM", "(System Trace Macrocell)")}, {0x975, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M7 ETM", "(Embedded Trace)")}, {0x9a0, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("CoreSight PMU", "(Performance Monitoring Unit)")}, {0x9a1, aa_nosupport, cidc_unknown, PIDR_PN_BIT_STRINGS("Cortex-M4 TPIU", "(Trace Port Interface Unit)")},