First implementation of CAN peripheral register definitions.
This commit is contained in:
Piotr Esden-Tempski
parent
c031b6691e
commit
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#include <libopenstm32/flash.h>
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#include <libopenstm32/flash.h>
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#include <libopenstm32/usb.h>
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#include <libopenstm32/usb.h>
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#include <libopenstm32/usb_desc.h>
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#include <libopenstm32/usb_desc.h>
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#include <libopenstm32/can.h>
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#include <libopenstm32/nvic.h>
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#include <libopenstm32/nvic.h>
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#include <libopenstm32/rtc.h>
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#include <libopenstm32/rtc.h>
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#include <libopenstm32/i2c.h>
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#include <libopenstm32/i2c.h>
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142
include/libopenstm32/can.h
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142
include/libopenstm32/can.h
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/*
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* This file is part of the libopenstm32 project.
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*
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* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENSTM32_CAN_H
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#define LIBOPENSTM32_CAN_H
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#include <libopenstm32/memorymap.h>
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#include <libopenstm32/common.h>
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/* --- Convenience macros -------------------------------------------------- */
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/* CAN register base adresses (for convenience) */
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#define CAN1 BX_CAN1_BASE
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#define CAN2 BX_CAN2_BASE
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/* --- CAN registers ------------------------------------------------------- */
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/* CAN master control register (CAN_MCR) */
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#define CAN_MCR(can_base) MMIO32(can_base + 0x000)
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/* CAN master status register (CAN_MSR) */
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#define CAN_MSR(can_base) MMIO32(can_base + 0x004)
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/* CAN transmit status register (CAN_TSR) */
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#define CAN_TSR(can_base) MMIO32(can_base + 0x008)
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/* CAN receive FIFO 0 register (CAN_RF0R) */
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#define CAN_RF0R(can_base) MMIO32(can_base + 0x00C)
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/* CAN receive FIFO 1 register (CAN_RF1R) */
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#define CAN_RF1R(can_base) MMIO32(can_base + 0x010)
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/* CAN interrupt enable register (CAN_IER) */
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#define CAN_IER(can_base) MMIO32(can_base + 0x014)
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/* CAN error status register (CAN_ESR) */
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#define CAN_ESR(can_base) MMIO32(can_base + 0x018)
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/* CAN bit timing register (CAN_BTR) */
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#define CAN_BTR(can_base) MMIO32(can_base + 0x01C)
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/* Registers in the offset range 0x020 to 0x17F are reserved */
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/* --- CAN mailbox registers ----------------------------------------------- */
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/* CAN mailbox / fifo register offsets */
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#define CAN_MBOX0 0x180
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#define CAN_MBOX1 0x190
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#define CAN_MBOX2 0x1A0
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#define CAN_FIFO0 0x1B0
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#define CAN_FIFO1 0x1C0
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/* CAN TX mailbox identifier register (CAN_TIxR) */
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#define CAN_TIxR(can_base, mbox) MMIO32(can_base + mbox + 0x0)
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#define CAN_TI0R(can_base) CAN_TIxR(can_base, CAN_MBOX0)
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#define CAN_TI1R(can_base) CAN_TIxR(can_base, CAN_MBOX1)
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#define CAN_TI2R(can_base) CAN_TIxR(can_base, CAN_MBOX2)
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/* CAN mailbox data length control and time stamp register (CAN_TDTxR) */
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#define CAN_TDTxR(can_base, mbox) MMIO32(can_base + mbox + 0x4)
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#define CAN_TDT0R(can_base) CAN_TDTxR(can_base, CAN_MBOX0)
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#define CAN_TDT1R(can_base) CAN_TDTxR(can_base, CAN_MBOX1)
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#define CAN_TDT2R(can_base) CAN_TDTxR(can_base, CAN_MBOX2)
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/* CAN mailbox data low register (CAN_TDLxR) */
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#define CAN_TDLxR(can_base, mbox) MMIO32(can_base + mbox + 0x8)
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#define CAN_TDL0R(can_base) CAN_TDLxR(can_base, CAN_MBOX0)
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#define CAN_TDL1R(can_base) CAN_TDLxR(can_base, CAN_MBOX1)
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#define CAN_TDL2R(can_base) CAN_TDLxR(can_base, CAN_MBOX2)
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/* CAN mailbox data high register (CAN_TDHxR) */
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#define CAN_TDHxR(can_base, mbox) MMIO32(can_base + mbox + 0xC)
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#define CAN_TDH0R(can_base) CAN_TDHxR(can_base, CAN_MBOX0)
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#define CAN_TDH1R(can_base) CAN_TDHxR(can_base, CAN_MBOX1)
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#define CAN_TDH2R(can_base) CAN_TDHxR(can_base, CAN_MBOX2)
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/* CAN RX FIFO identifier register (CAN_RIxR) */
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#define CAN_RIxR(can_base, fifo) MMIO32(can_base + fifo + 0x0)
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#define CAN_RI0R(can_base) CAN_RIxR(can_base, CAN_FIFO0)
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#define CAN_RI1R(can_base) CAN_RIxR(can_base, CAN_FIFO1)
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/* CAN RX FIFO mailbox data length control and time stamp register (CAN_RDTxR) */
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#define CAN_RDTxR(can_base, fifo) MMIO32(can_base + fifo + 0x4)
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#define CAN_RDT0R(can_base) CAN_RDTxR(can_base, CAN_FIFO0)
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#define CAN_RDT1R(can_base) CAN_RDTxR(can_base, CAN_FIFO1)
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/* CAN RX FIFO mailbox data low register (CAN_RDLxR) */
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#define CAN_RDLxR(can_base, fifo) MMIO32(can_base + fifo + 0x8)
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#define CAN_RDL0R(can_base) CAN_RDLxR(can_base, CAN_FIFO0)
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#define CAN_RDL1R(can_base) CAN_RDLxR(can_base, CAN_FIFO1)
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/* CAN RX FIFO mailbox data high register (CAN_RDHxR) */
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#define CAN_RDHxR(can_base, fifo) MMIO32(can_base + fifo + 0xC)
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#define CAN_RDH0R(can_base) CAN_RDHxR(can_base, CAN_FIFO0)
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#define CAN_RDH1R(can_base) CAN_RDHxR(can_base, CAN_FIFO1)
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/* --- CAN filter registers ------------------------------------------------ */
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/* CAN filter master register (CAN_FMR) */
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#define CAN_FMR(can_base) MMIO32(can_base + 0x200)
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/* CAN filter mode register (CAN_FM1R) */
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#define CAN_FM1R(can_base) MMIO32(can_base + 0x204)
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/* Register offset 0x208 reserved */
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/* CAN filter scale register (CAN_FS1R) */
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#define CAN_FS1R(can_base) MMIO32(can_base + 0x20C)
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/* Register offset 0x210 reserved */
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/* CAN filter FIFO assignement register (CAN_FFA1R) */
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#define CAN_FFA1R(can_base) MMIO32(can_base + 0x214)
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/* Register offset 0x218 reserved */
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/* CAN filter activation register (CAN_FA1R) */
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#define CAN_FA1R(can_base) MMIO32(can_base + 0x21C)
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/* Register offset 0x220 reserved */
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/* Registers with offset 0x224 to 0x23F reserved */
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/* CAN filter bank registers (CAN_FiRx) */
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/* Connectivity line devices have 28 banks so the bank id spans 0..27
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* all other devices have 14 banks so the bank id spans 0..13
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*/
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#define CAN_FiR1(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x0)
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#define CAN_FiR2(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x4)
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#endif /* LIBOPENSTM32_CAN_H */
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