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Added break and dead time convenience functions. Adapted 6step example to reflect that.

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This commit is contained in:
Piotr Esden-Tempski 2011-01-28 16:04:36 -08:00
parent a1bd228c87
commit 59293a9640
3 changed files with 136 additions and 1 deletions
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11
examples/stm32/stm32-h103/pwm_6step/pwm_6step.c
View File

@ -94,6 +94,15 @@ void tim_setup(void)
/* Period (32kHz) */
timer_set_period(TIM1, 72000000 / 32000);
/* Configure break and deadtime */
timer_set_deadtime(TIM1, 0);
timer_set_enabled_off_state_in_idle_mode(TIM1);
timer_set_enabled_off_state_in_run_mode(TIM1);
timer_disable_break(TIM1);
timer_set_break_polarity_high(TIM1);
timer_disable_break_automatic_output(TIM1);
timer_set_break_lock(TIM1, TIM_BDTR_LOCK_OFF);
/* -- OC1 and OC1N configuration -- */
/* Disable outputs. */
@ -180,7 +189,7 @@ void tim_setup(void)
timer_enable_preload(TIM1);
/* Enable outputs in the break subsystem */
TIM1_BDTR |= TIM_BDTR_MOE;
timer_enable_break_main_output(TIM1);
/* Counter enable */
timer_enable_counter(TIM1);

14
include/libopencm3/stm32/timer.h
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@ -894,5 +894,19 @@ void timer_disable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_idle_state_set(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_idle_state_unset(u32 timer_peripheral, enum tim_oc_id oc_id);
void timer_set_oc_value(u32 timer_peripheral, enum tim_oc_id oc_id, u32 value);
void timer_enable_break_main_output(u32 timer_peripheral);
void timer_disable_break_main_output(u32 timer_peripheral);
void timer_enable_break_automatic_output(u32 timer_peripheral);
void timer_disable_break_automatic_output(u32 timer_peripheral);
void timer_set_break_polarity_high(u32 timer_peripheral);
void timer_set_break_polarity_low(u32 timer_peripheral);
void timer_enable_break(u32 timer_peripheral);
void timer_disable_break(u32 timer_peripheral);
void timer_set_enabled_off_state_in_run_mode(u32 timer_peripheral);
void timer_set_disabled_off_state_in_run_mode(u32 timer_peripheral);
void timer_set_enabled_off_state_in_idle_mode(u32 timer_peripheral);
void timer_set_disabled_off_state_in_idle_mode(u32 timer_peripheral);
void timer_set_break_lock(u32 timer_peripheral, u32 lock);
void timer_set_deadtime(u32 timer_peripheral, u32 deadtime);
#endif

112
lib/stm32/timer.c
View File

@ -717,3 +717,115 @@ void timer_set_oc_value(u32 timer_peripheral, enum tim_oc_id oc_id, u32 value)
break;
}
}
void timer_enable_break_main_output(u32 timer_peripheral)
{
if ((timer_peripheral == TIM1) ||
(timer_peripheral == TIM8)) {
TIM_BDTR(timer_peripheral) |= TIM_BDTR_MOE;
}
}
void timer_disable_break_main_output(u32 timer_peripheral)
{
if ((timer_peripheral == TIM1) ||
(timer_peripheral == TIM8)) {
TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_MOE;
}
}
void timer_enable_break_automatic_output(u32 timer_peripheral)
{
if ((timer_peripheral == TIM1) ||
(timer_peripheral == TIM8)) {
TIM_BDTR(timer_peripheral) |= TIM_BDTR_AOE;
}
}
void timer_disable_break_automatic_output(u32 timer_peripheral)
{
if ((timer_peripheral == TIM1) ||
(timer_peripheral == TIM8)) {
TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_AOE;
}
}
void timer_set_break_polarity_high(u32 timer_peripheral)
{
if ((timer_peripheral == TIM1) ||
(timer_peripheral == TIM8)) {
TIM_BDTR(timer_peripheral) |= TIM_BDTR_BKP;
}
}
void timer_set_break_polarity_low(u32 timer_peripheral)
{
if ((timer_peripheral == TIM1) ||
(timer_peripheral == TIM8)) {
TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_BKP;
}
}
void timer_enable_break(u32 timer_peripheral)
{
if ((timer_peripheral == TIM1) ||
(timer_peripheral == TIM8)) {
TIM_BDTR(timer_peripheral) |= TIM_BDTR_BKE;
}
}
void timer_disable_break(u32 timer_peripheral)
{
if ((timer_peripheral == TIM1) ||
(timer_peripheral == TIM8)) {
TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_BKE;
}
}
void timer_set_enabled_off_state_in_run_mode(u32 timer_peripheral)
{
if ((timer_peripheral == TIM1) ||
(timer_peripheral == TIM8)) {
TIM_BDTR(timer_peripheral) |= TIM_BDTR_OSSR;
}
}
void timer_set_disabled_off_state_in_run_mode(u32 timer_peripheral)
{
if ((timer_peripheral == TIM1) ||
(timer_peripheral == TIM8)) {
TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_OSSR;
}
}
void timer_set_enabled_off_state_in_idle_mode(u32 timer_peripheral)
{
if ((timer_peripheral == TIM1) ||
(timer_peripheral == TIM8)) {
TIM_BDTR(timer_peripheral) |= TIM_BDTR_OSSI;
}
}
void timer_set_disabled_off_state_in_idle_mode(u32 timer_peripheral)
{
if ((timer_peripheral == TIM1) ||
(timer_peripheral == TIM8)) {
TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_OSSI;
}
}
void timer_set_break_lock(u32 timer_peripheral, u32 lock)
{
if ((timer_peripheral == TIM1) ||
(timer_peripheral == TIM8)) {
TIM_BDTR(timer_peripheral) |= lock;
}
}
void timer_set_deadtime(u32 timer_peripheral, u32 deadtime)
{
if ((timer_peripheral == TIM1) ||
(timer_peripheral == TIM8)) {
TIM_BDTR(timer_peripheral) |= deadtime;
}
}