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stm32: l0: timer/lptimer: doc+

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better doc for l0 lptimer registers, add mask.
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Guillaume Revaillot 2018-11-13 18:27:27 +01:00 committed by Guillaume Revaillot
parent 6c1f54dcb7
commit 594c354068
1 changed files with 58 additions and 0 deletions
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58
include/libopencm3/stm32/l0/timer.h
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@ -114,6 +114,9 @@ LGPL License Terms @ref lgpl_license
#define LPTIM1_ARR LPTIM_ARR(LPTIM1_BASE)
#define LPTIM1_CNT LPTIM_CNT(LPTIM1_BASE)
/** @defgroup lptim_isr LPTIM_ISR Interrupt and Status Register
* @ingroup timer_defines
@{*/
#define LPTIM_ISR_CMPM (1 << 0)
#define LPTIM_ISR_ARRM (1 << 1)
#define LPTIM_ISR_EXTTRIG (1 << 2)
@ -121,7 +124,11 @@ LGPL License Terms @ref lgpl_license
#define LPTIM_ISR_ARROK (1 << 4)
#define LPTIM_ISR_UP (1 << 5)
#define LPTIM_ISR_DOWN (1 << 6)
/**@}*/
/** @defgroup lptim_icr LPTIM_ICR Interrupt Clear Register
* @ingroup timer_defines
@{*/
#define LPTIM_ICR_CMPMCF (1 << 0)
#define LPTIM_ICR_ARRMCF (1 << 1)
#define LPTIM_ICR_EXTTRIGCF (1 << 2)
@ -129,7 +136,11 @@ LGPL License Terms @ref lgpl_license
#define LPTIM_ICR_ARROKCF (1 << 4)
#define LPTIM_ICR_UPCF (1 << 5)
#define LPTIM_ICR_DOWNCF (1 << 6)
/**@}*/
/** @defgroup lptim_ier LPTIM_IER Interrupt Enable Register
* @ingroup timer_defines
@{*/
#define LPTIM_IER_CMPMIE (1 << 0)
#define LPTIM_IER_ARRMIE (1 << 1)
#define LPTIM_IER_EXTTRIGIE (1 << 2)
@ -137,32 +148,53 @@ LGPL License Terms @ref lgpl_license
#define LPTIM_IER_ARROKIE (1 << 4)
#define LPTIM_IER_UPIE (1 << 5)
#define LPTIM_IER_DOWNIE (1 << 6)
/**@}*/
/** @defgroup lptim_cfgr LPTIM_CFGR Configuration Register
* @ingroup timer_defines
@{*/
/** CKSEL: Select internal (0) or external clock source (1) **/
#define LPTIM_CFGR_CKSEL (1 << 0)
#define LPTIM_CFGR_CKPOL_SHIFT 1
#define LPTIM_CFGR_CKPOL_MASK 0x03
#define LPTIM_CFGR_CKPOL (3 << LPTIM_CFGR_CKPOL_SHIFT)
/** @defgroup lptim_cfgr_ckpol LPTIM_CFGR CKPOL Clock Polarity
@{*/
#define LPTIM_CFGR_CKPOL_RISING (0 << LPTIM_CFGR_CKPOL_SHIFT)
#define LPTIM_CFGR_CKPOL_FALLING (1 << LPTIM_CFGR_CKPOL_SHIFT)
#define LPTIM_CFGR_CKPOL_BOTH (2 << LPTIM_CFGR_CKPOL_SHIFT)
#define LPTIM_CFGR_CKPOL_ENC_1 (0 << LPTIM_CFGR_CKPOL_SHIFT)
#define LPTIM_CFGR_CKPOL_ENC_2 (1 << LPTIM_CFGR_CKPOL_SHIFT)
#define LPTIM_CFGR_CKPOL_ENC_3 (2 << LPTIM_CFGR_CKPOL_SHIFT)
/**@}*/
#define LPTIM_CFGR_CKFLT_SHIFT 3
#define LPTIM_CFGR_CKFLT_MASK 0x03
#define LPTIM_CFGR_CKFLT (3 << LPTIM_CFGR_CKFLT_SHIFT)
/** @defgroup lptim_cfgr_ckflt LPTIM_CFGR CKFLT Configurable digital filter for external clock
@{*/
#define LPTIM_CFGR_CKFLT_2 (1 << LPTIM_CFGR_CKFLT_SHIFT)
#define LPTIM_CFGR_CKFLT_4 (2 << LPTIM_CFGR_CKFLT_SHIFT)
#define LPTIM_CFGR_CKFLT_8 (3 << LPTIM_CFGR_CKFLT_SHIFT)
/**@}*/
#define LPTIM_CFGR_TRGFLT_SHIFT 6
#define LPTIM_CFGR_TRGFLT_MASK 0x03
#define LPTIM_CFGR_TRGFLT (3 << LPTIM_CFGR_TRGFLT_SHIFT)
/** @defgroup lptim_cfgr_trgflt LPTIM_CFGR TRGFLT Configurable digital filter for trigger
@{*/
#define LPTIM_CFGR_TRGFLT_2 (1 << LPTIM_CFGR_TRGFLT_SHIFT)
#define LPTIM_CFGR_TRGFLT_4 (2 << LPTIM_CFGR_TRGFLT_SHIFT)
#define LPTIM_CFGR_TRGFLT_8 (3 << LPTIM_CFGR_TRGFLT_SHIFT)
/**@}*/
#define LPTIM_CFGR_PRESC_SHIFT 9
#define LPTIM_CFGR_PRESC_MASK 0x07
#define LPTIM_CFGR_PRESC (7 << LPTIM_CFGR_PRESC_SHIFT)
/** @defgroup lptim_cfgr_presc LPTIM_CFGR PRESC Clock prescaler
@{*/
#define LPTIM_CFGR_PRESC_1 (0 << LPTIM_CFGR_PRESC_SHIFT)
#define LPTIM_CFGR_PRESC_2 (1 << LPTIM_CFGR_PRESC_SHIFT)
#define LPTIM_CFGR_PRESC_4 (2 << LPTIM_CFGR_PRESC_SHIFT)
@ -171,9 +203,13 @@ LGPL License Terms @ref lgpl_license
#define LPTIM_CFGR_PRESC_32 (5 << LPTIM_CFGR_PRESC_SHIFT)
#define LPTIM_CFGR_PRESC_64 (6 << LPTIM_CFGR_PRESC_SHIFT)
#define LPTIM_CFGR_PRESC_128 (7 << LPTIM_CFGR_PRESC_SHIFT)
/**@}*/
#define LPTIM_CFGR_TRIGSEL_SHIFT 13
#define LPTIM_CFGR_TRIGSEL_MASK 0x07
#define LPTIM_CFGR_TRIGSEL (7 << LPTIM_CFGR_TRIGSEL_SHIFT)
/** @defgroup lptim_cfgr_trigsel LPTIM_CFGR TRIGSEL Trigger selector
@{*/
#define LPTIM_CFGR_TRIGSEL_EXT_TRIG0 (0 << LPTIM_CFGR_TRIGSEL_SHIFT)
#define LPTIM_CFGR_TRIGSEL_EXT_TRIG1 (1 << LPTIM_CFGR_TRIGSEL_SHIFT)
#define LPTIM_CFGR_TRIGSEL_EXT_TRIG2 (2 << LPTIM_CFGR_TRIGSEL_SHIFT)
@ -182,30 +218,52 @@ LGPL License Terms @ref lgpl_license
/* 5 is reserved */
#define LPTIM_CFGR_TRIGSEL_EXT_TRIG6 (6 << LPTIM_CFGR_TRIGSEL_SHIFT)
#define LPTIM_CFGR_TRIGSEL_EXT_TRIG7 (7 << LPTIM_CFGR_TRIGSEL_SHIFT)
/**@}*/
#define LPTIM_CFGR_TRIGEN_SHIFT 17
#define LPTIM_CFGR_TRIGSEL_MASK 0x07
#define LPTIM_CFGR_TRIGEN (3 << LPTIM_CFGR_TRIGEN_SHIFT)
/* @defgroup LPTIM_CFGR_TRIGEN LPTIM_CFGR TRIGEN Trigger enable and polarity
@{*/
#define LPTIM_CFGR_TRIGEN_SW (0 << LPTIM_CFGR_TRIGEN_SHIFT)
#define LPTIM_CFGR_TRIGEN_RISING (1 << LPTIM_CFGR_TRIGEN_SHIFT)
#define LPTIM_CFGR_TRIGEN_FALLING (2 << LPTIM_CFGR_TRIGEN_SHIFT)
#define LPTIM_CFGR_TRIGEN_BOTH (3 << LPTIM_CFGR_TRIGEN_SHIFT)
/**@}*/
/** TIMOUT: Timeout enable **/
#define LPTIM_CFGR_TIMOUT (1 << 19)
/** WAVE: Waveform shape **/
#define LPTIM_CFGR_WAVE (1 << 20)
/** WAVPOL: Waveform shape polarity **/
#define LPTIM_CFGR_WAVPOL (1 << 21)
/** PRELOAD: Register update mode **/
#define LPTIM_CFGR_PRELOAD (1 << 22)
/** COUNTMODE: Counter mode enable **/
#define LPTIM_CFGR_COUNTMODE (1 << 23)
/** ENC: Encoder mode enable **/
#define LPTIM_CFGR_ENC (1 << 24)
/**@}*/
/** @defgroup lptim_cr LPTIM_CR Control Register
* @ingroup timer_defines
@{*/
/** ENABLE: Counter enable **/
#define LPTIM_CR_ENABLE (1 << 0)
/** SNGSTRT: Start in Single Mode **/
#define LPTIM_CR_SNGSTRT (1 << 1)
/** CNGSTRT: Start in Continuous Mode **/
#define LPTIM_CR_CNTSTRT (1 << 2)
/**@}*/
#endif