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stm32/spi: Replace all SPIx_I2S_BASE with SPIx_BASE

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Latest versions of all reference manuals refer to the address as SPIx_BASE, and
simply name some of the individual registers as SPI_I2SXXXX.  Likewise, the
interrupts are simply SPIx, not SPIx/I2Sx.  Rather than hacking more duplicates
into the F0 and L0 parts where this was turning up, remove the pointless _I2S_
from SPI2/SPI3 and make it all consistent

Compile tested only, with the examples collection.

Signed-off-by: Karl Palsson <karlp@tweak.net.au>

Fixes #331
Fixes #347
This commit is contained in:
Karl Palsson 2014-09-30 22:09:11 +00:00 committed by Karl Palsson
parent 2211944233
commit 5d4437fe43
9 changed files with 34 additions and 39 deletions
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40
include/libopencm3/stm32/common/spi_common_all.h
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@ -44,8 +44,8 @@ specific memorymap.h header before including this header file.*/
@{*/ @{*/
#define SPI1 SPI1_BASE #define SPI1 SPI1_BASE
#define SPI2 SPI2_I2S_BASE #define SPI2 SPI2_BASE
#define SPI3 SPI3_I2S_BASE #define SPI3 SPI3_BASE
#define SPI4 SPI4_BASE #define SPI4 SPI4_BASE
#define SPI5 SPI5_BASE #define SPI5 SPI5_BASE
#define SPI6 SPI6_BASE #define SPI6 SPI6_BASE
@ -57,59 +57,59 @@ specific memorymap.h header before including this header file.*/
/* Note: Not used in I2S mode. */ /* Note: Not used in I2S mode. */
#define SPI_CR1(spi_base) MMIO32(spi_base + 0x00) #define SPI_CR1(spi_base) MMIO32(spi_base + 0x00)
#define SPI1_CR1 SPI_CR1(SPI1_BASE) #define SPI1_CR1 SPI_CR1(SPI1_BASE)
#define SPI2_CR1 SPI_CR1(SPI2_I2S_BASE) #define SPI2_CR1 SPI_CR1(SPI2_BASE)
#define SPI3_CR1 SPI_CR1(SPI3_I2S_BASE) #define SPI3_CR1 SPI_CR1(SPI3_BASE)
/* Control register 2 (SPIx_CR2) */ /* Control register 2 (SPIx_CR2) */
#define SPI_CR2(spi_base) MMIO32(spi_base + 0x04) #define SPI_CR2(spi_base) MMIO32(spi_base + 0x04)
#define SPI1_CR2 SPI_CR2(SPI1_BASE) #define SPI1_CR2 SPI_CR2(SPI1_BASE)
#define SPI2_CR2 SPI_CR2(SPI2_I2S_BASE) #define SPI2_CR2 SPI_CR2(SPI2_BASE)
#define SPI3_CR2 SPI_CR2(SPI3_I2S_BASE) #define SPI3_CR2 SPI_CR2(SPI3_BASE)
/* Status register (SPIx_SR) */ /* Status register (SPIx_SR) */
#define SPI_SR(spi_base) MMIO32(spi_base + 0x08) #define SPI_SR(spi_base) MMIO32(spi_base + 0x08)
#define SPI1_SR SPI_SR(SPI1_BASE) #define SPI1_SR SPI_SR(SPI1_BASE)
#define SPI2_SR SPI_SR(SPI2_I2S_BASE) #define SPI2_SR SPI_SR(SPI2_BASE)
#define SPI3_SR SPI_SR(SPI3_I2S_BASE) #define SPI3_SR SPI_SR(SPI3_BASE)
/* Data register (SPIx_DR) */ /* Data register (SPIx_DR) */
#define SPI_DR(spi_base) MMIO32(spi_base + 0x0c) #define SPI_DR(spi_base) MMIO32(spi_base + 0x0c)
#define SPI1_DR SPI_DR(SPI1_BASE) #define SPI1_DR SPI_DR(SPI1_BASE)
#define SPI2_DR SPI_DR(SPI2_I2S_BASE) #define SPI2_DR SPI_DR(SPI2_BASE)
#define SPI3_DR SPI_DR(SPI3_I2S_BASE) #define SPI3_DR SPI_DR(SPI3_BASE)
/* CRC polynomial register (SPIx_CRCPR) */ /* CRC polynomial register (SPIx_CRCPR) */
/* Note: Not used in I2S mode. */ /* Note: Not used in I2S mode. */
#define SPI_CRCPR(spi_base) MMIO32(spi_base + 0x10) #define SPI_CRCPR(spi_base) MMIO32(spi_base + 0x10)
#define SPI1_CRCPR SPI_CRCPR(SPI1_BASE) #define SPI1_CRCPR SPI_CRCPR(SPI1_BASE)
#define SPI2_CRCPR SPI_CRCPR(SPI2_I2S_BASE) #define SPI2_CRCPR SPI_CRCPR(SPI2_BASE)
#define SPI3_CRCPR SPI_CRCPR(SPI3_I2S_BASE) #define SPI3_CRCPR SPI_CRCPR(SPI3_BASE)
/* RX CRC register (SPIx_RXCRCR) */ /* RX CRC register (SPIx_RXCRCR) */
/* Note: Not used in I2S mode. */ /* Note: Not used in I2S mode. */
#define SPI_RXCRCR(spi_base) MMIO32(spi_base + 0x14) #define SPI_RXCRCR(spi_base) MMIO32(spi_base + 0x14)
#define SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE) #define SPI1_RXCRCR SPI_RXCRCR(SPI1_BASE)
#define SPI2_RXCRCR SPI_RXCRCR(SPI2_I2S_BASE) #define SPI2_RXCRCR SPI_RXCRCR(SPI2_BASE)
#define SPI3_RXCRCR SPI_RXCRCR(SPI3_I2S_BASE) #define SPI3_RXCRCR SPI_RXCRCR(SPI3_BASE)
/* TX CRC register (SPIx_RXCRCR) */ /* TX CRC register (SPIx_RXCRCR) */
/* Note: Not used in I2S mode. */ /* Note: Not used in I2S mode. */
#define SPI_TXCRCR(spi_base) MMIO32(spi_base + 0x18) #define SPI_TXCRCR(spi_base) MMIO32(spi_base + 0x18)
#define SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE) #define SPI1_TXCRCR SPI_TXCRCR(SPI1_BASE)
#define SPI2_TXCRCR SPI_TXCRCR(SPI2_I2S_BASE) #define SPI2_TXCRCR SPI_TXCRCR(SPI2_BASE)
#define SPI3_TXCRCR SPI_TXCRCR(SPI3_I2S_BASE) #define SPI3_TXCRCR SPI_TXCRCR(SPI3_BASE)
/* I2S configuration register (SPIx_I2SCFGR) */ /* I2S configuration register (SPIx_I2SCFGR) */
#define SPI_I2SCFGR(spi_base) MMIO32(spi_base + 0x1c) #define SPI_I2SCFGR(spi_base) MMIO32(spi_base + 0x1c)
#define SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE) #define SPI1_I2SCFGR SPI_I2SCFGR(SPI1_BASE)
#define SPI2_I2SCFGR SPI_I2SCFGR(SPI2_I2S_BASE) #define SPI2_I2SCFGR SPI_I2SCFGR(SPI2_BASE)
#define SPI3_I2SCFGR SPI_I2SCFGR(SPI3_I2S_BASE) #define SPI3_I2SCFGR SPI_I2SCFGR(SPI3_BASE)
/* I2S prescaler register (SPIx_I2SPR) */ /* I2S prescaler register (SPIx_I2SPR) */
#define SPI_I2SPR(spi_base) MMIO32(spi_base + 0x20) #define SPI_I2SPR(spi_base) MMIO32(spi_base + 0x20)
#define SPI1_I2SPR SPI_I2SPR(SPI1_BASE) #define SPI1_I2SPR SPI_I2SPR(SPI1_BASE)
#define SPI2_I2SPR SPI_I2SPR(SPI2_I2S_BASE) #define SPI2_I2SPR SPI_I2SPR(SPI2_BASE)
#define SPI3_I2SPR SPI_I2SPR(SPI3_I2S_BASE) #define SPI3_I2SPR SPI_I2SPR(SPI3_BASE)
/* --- SPI_CR1 values ------------------------------------------------------ */ /* --- SPI_CR1 values ------------------------------------------------------ */

4
include/libopencm3/stm32/common/spi_common_f03.h
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@ -39,8 +39,8 @@
#define SPI_DR8(spi_base) MMIO8(spi_base + 0x0c) #define SPI_DR8(spi_base) MMIO8(spi_base + 0x0c)
#define SPI1_DR8 SPI_DR8(SPI1_BASE) #define SPI1_DR8 SPI_DR8(SPI1_BASE)
#define SPI2_DR8 SPI_DR8(SPI2_I2S_BASE) #define SPI2_DR8 SPI_DR8(SPI2_BASE)
#define SPI3_DR8 SPI_DR8(SPI3_I2S_BASE) #define SPI3_DR8 SPI_DR8(SPI3_BASE)
/* DFF: Data frame format */ /* DFF: Data frame format */
/****************************************************************************/ /****************************************************************************/

2
include/libopencm3/stm32/f0/memorymap.h
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@ -71,7 +71,7 @@
#define ADC_BASE (PERIPH_BASE_APB + 0x12400) #define ADC_BASE (PERIPH_BASE_APB + 0x12400)
#define TIM1_BASE (PERIPH_BASE_APB + 0x12C00) #define TIM1_BASE (PERIPH_BASE_APB + 0x12C00)
#define SPI1_I2S1_BASE (PERIPH_BASE_APB + 0x13000) #define SPI1_BASE (PERIPH_BASE_APB + 0x13000)
#define USART1_BASE (PERIPH_BASE_APB + 0x13800) #define USART1_BASE (PERIPH_BASE_APB + 0x13800)
#define TIM15_BASE (PERIPH_BASE_APB + 0x14000) #define TIM15_BASE (PERIPH_BASE_APB + 0x14000)

4
include/libopencm3/stm32/f1/memorymap.h
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@ -49,8 +49,8 @@
#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) #define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) #define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ /* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
#define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800) #define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)
#define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00) #define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)
/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */ /* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) #define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) #define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)

4
include/libopencm3/stm32/f2/memorymap.h
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@ -49,8 +49,8 @@
#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) #define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) #define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */ /* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
#define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800) #define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)
#define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00) #define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)
/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */ /* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) #define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) #define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)

4
include/libopencm3/stm32/f3/memorymap.h
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@ -48,8 +48,8 @@
#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) #define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) #define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
#define I2S2_EXT_BASE (PERIPH_BASE_APB1 + 0x3400) #define I2S2_EXT_BASE (PERIPH_BASE_APB1 + 0x3400)
#define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800) #define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)
#define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00) #define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)
#define I2S3_EXT_BASE (PERIPH_BASE_APB1 + 0x4000) #define I2S3_EXT_BASE (PERIPH_BASE_APB1 + 0x4000)
#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) #define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) #define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)

4
include/libopencm3/stm32/f4/memorymap.h
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@ -49,8 +49,8 @@
#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) #define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) #define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
#define I2S3_EXT_BASE (PERIPH_BASE_APB1 + 0x3400) #define I2S3_EXT_BASE (PERIPH_BASE_APB1 + 0x3400)
#define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800) #define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)
#define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00) #define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)
#define I2S2_EXT_BASE (PERIPH_BASE_APB1 + 0x4000) #define I2S2_EXT_BASE (PERIPH_BASE_APB1 + 0x4000)
#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) #define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) #define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)

5
include/libopencm3/stm32/l1/memorymap.h
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@ -118,9 +118,4 @@
#define ST_TSENSE_CAL1_30C MMIO16(0x1FF8007A) #define ST_TSENSE_CAL1_30C MMIO16(0x1FF8007A)
#define ST_TSENSE_CAL2_110C MMIO16(0x1FF8007E) #define ST_TSENSE_CAL2_110C MMIO16(0x1FF8007E)
/* Make the map names match those for other families to allow commonality */
#define SPI1_I2S_BASE SPI1_BASE
#define SPI2_I2S_BASE SPI2_BASE
#define SPI3_I2S_BASE SPI3_BASE
#endif #endif

6
lib/stm32/common/spi_common_all.c
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@ -86,12 +86,12 @@ void spi_reset(uint32_t spi_peripheral)
rcc_periph_reset_pulse(RST_SPI1); rcc_periph_reset_pulse(RST_SPI1);
break; break;
#endif #endif
#if defined(SPI2_I2S_BASE) #if defined(SPI2_BASE)
case SPI2_I2S_BASE: case SPI2_BASE:
rcc_periph_reset_pulse(RST_SPI2); rcc_periph_reset_pulse(RST_SPI2);
break; break;
#endif #endif
#if defined(SPI3_I2S_BASE) #if defined(SPI3_BASE)
case SPI3_I2S_BASE: case SPI3_I2S_BASE:
rcc_periph_reset_pulse(RST_SPI3); rcc_periph_reset_pulse(RST_SPI3);
break; break;