From 5ea4763845cefdb5f9d2878801cef1f32e094535 Mon Sep 17 00:00:00 2001 From: Alexandru Gagniuc Date: Sun, 7 Jul 2013 13:56:11 -0500 Subject: [PATCH] lm4f: Appease checkpath.pl and de-typedef enums Signed-off-by: Alexandru Gagniuc --- include/libopencm3/lm4f/rcc.h | 20 ++++++++++---------- include/libopencm3/lm4f/systemcontrol.h | 8 ++++---- lib/lm4f/rcc.c | 18 +++++++++--------- lib/lm4f/systemcontrol.c | 8 ++++---- 4 files changed, 27 insertions(+), 27 deletions(-) diff --git a/include/libopencm3/lm4f/rcc.h b/include/libopencm3/lm4f/rcc.h index cf35ee89..98a92cfd 100644 --- a/include/libopencm3/lm4f/rcc.h +++ b/include/libopencm3/lm4f/rcc.h @@ -45,13 +45,13 @@ LGPL License Terms @ref lgpl_license * * Possible values of the oscillator source. */ -typedef enum { +enum osc_src { OSCSRC_MOSC = SYSCTL_RCC2_OSCSRC2_MOSC, OSCSRC_PIOSC = SYSCTL_RCC2_OSCSRC2_PIOSC, OSCSRC_PIOSC_D4 = SYSCTL_RCC2_OSCSRC2_PIOSC_D4, OSCSRC_30K_INT = SYSCTL_RCC2_OSCSRC2_30K, OSCSRC_32K_EXT = SYSCTL_RCC2_OSCSRC2_32K768, -} osc_src_t; +}; /** * \brief PWM clock divisor values @@ -59,14 +59,14 @@ typedef enum { * Possible values of the binary divisor used to predivide the system clock down * for use as the timing reference for the PWM module. */ -typedef enum { +enum pwm_clkdiv { PWMDIV_2 = SYSCTL_RCC_PWMDIV_2, PWMDIV_4 = SYSCTL_RCC_PWMDIV_4, PWMDIV_8 = SYSCTL_RCC_PWMDIV_8, PWMDIV_16 = SYSCTL_RCC_PWMDIV_16, PWMDIV_32 = SYSCTL_RCC_PWMDIV_32, PWMDIV_64 = SYSCTL_RCC_PWMDIV_64, -} pwm_clkdiv_t; +}; /** * \brief Predefined crystal values @@ -76,7 +76,7 @@ typedef enum { * SYSCTL_PLLFREQ1 are automatically adjusted in hardware to provide a PLL clock * of 400MHz. */ -typedef enum { +enum xtal_t { XTAL_4M = SYSCTL_RCC_XTAL_4M, XTAL_4M_096 = SYSCTL_RCC_XTAL_4M_096, XTAL_4M_9152 = SYSCTL_RCC_XTAL_4M_9152, @@ -98,14 +98,14 @@ typedef enum { XTAL_20M = SYSCTL_RCC_XTAL_20M, XTAL_24M = SYSCTL_RCC_XTAL_24M, XTAL_25M = SYSCTL_RCC_XTAL_25M, -} xtal_t; +}; /* ============================================================================= * Function prototypes * ---------------------------------------------------------------------------*/ BEGIN_DECLS /* Low-level clock API */ -void rcc_configure_xtal(xtal_t xtal); +void rcc_configure_xtal(enum xtal_t xtal); void rcc_disable_main_osc(void); void rcc_disable_interal_osc(void); void rcc_enable_main_osc(void); @@ -113,18 +113,18 @@ void rcc_enable_interal_osc(void); void rcc_enable_rcc2(void); void rcc_pll_off(void); void rcc_pll_on(void); -void rcc_set_osc_source(osc_src_t src); +void rcc_set_osc_source(enum osc_src src); void rcc_pll_bypass_disable(void); void rcc_pll_bypass_enable(void); void rcc_set_pll_divisor(uint8_t div400); -void rcc_set_pwm_divisor(pwm_clkdiv_t div); +void rcc_set_pwm_divisor(enum pwm_clkdiv div); void rcc_usb_pll_off(void); void rcc_usb_pll_on(void); void rcc_wait_for_pll_ready(void); /* High-level clock API */ void rcc_change_pll_divisor(uint8_t plldiv400); uint32_t rcc_get_system_clock_frequency(void); -void rcc_sysclk_config(osc_src_t src, xtal_t xtal, uint8_t pll_div400); +void rcc_sysclk_config(enum osc_src src, enum xtal_t xtal, uint8_t pll_div400); END_DECLS diff --git a/include/libopencm3/lm4f/systemcontrol.h b/include/libopencm3/lm4f/systemcontrol.h index 1af3ac38..62e22313 100644 --- a/include/libopencm3/lm4f/systemcontrol.h +++ b/include/libopencm3/lm4f/systemcontrol.h @@ -486,7 +486,7 @@ LGPL License Terms @ref lgpl_license * SCC for sleep clock * DCC for deep-sleep clock */ -typedef enum { +enum lm4f_clken { /* * Run clock control */ @@ -725,15 +725,15 @@ typedef enum { DCC_WTIMER4, DCC_WTIMER5, -} clken_t; +}; /* ============================================================================ * Function prototypes * --------------------------------------------------------------------------*/ BEGIN_DECLS -void periph_clock_enable(clken_t periph); -void periph_clock_disable(clken_t periph); +void periph_clock_enable(enum lm4f_clken periph); +void periph_clock_disable(enum lm4f_clken periph); END_DECLS diff --git a/lib/lm4f/rcc.c b/lib/lm4f/rcc.c index a8404ad8..9b051b34 100644 --- a/lib/lm4f/rcc.c +++ b/lib/lm4f/rcc.c @@ -116,7 +116,7 @@ uint32_t lm4f_rcc_sysclk_freq = 16000000; * * @param[in] xtal predefined crystal type @see xtal_t */ -void rcc_configure_xtal(xtal_t xtal) +void rcc_configure_xtal(enum xtal_t xtal) { uint32_t reg32; @@ -213,7 +213,7 @@ void rcc_pll_on(void) * USERCC2 must have been set by a call to rcc_enable_rcc2() before calling this * function. */ -void rcc_set_osc_source(osc_src_t src) +void rcc_set_osc_source(enum osc_src src) { uint32_t reg32; @@ -291,7 +291,7 @@ void rcc_set_pll_divisor(uint8_t div400) * * @param[in] div clock divisor to use @see pwm_clkdiv_t */ -void rcc_set_pwm_divisor(pwm_clkdiv_t div) +void rcc_set_pwm_divisor(enum pwm_clkdiv div) { uint32_t reg32; @@ -385,8 +385,8 @@ uint32_t rcc_get_system_clock_frequency(void) return lm4f_rcc_sysclk_freq; } -/* Get the clock frequency corresponging to a given XTAL value */ -static uint32_t xtal_to_freq(xtal_t xtal) +/* Get the clock frequency corresponding to a given XTAL value */ +static uint32_t xtal_to_freq(enum xtal_t xtal) { const uint32_t freqs[] = { 4000000, /* XTAL_4M */ @@ -440,7 +440,7 @@ static uint32_t xtal_to_freq(xtal_t xtal) * * @return System clock frequency in Hz */ -void rcc_sysclk_config(osc_src_t osc_src, xtal_t xtal, uint8_t pll_div400) +void rcc_sysclk_config(enum osc_src src, enum xtal_t xtal, uint8_t pll_div400) { /* * We could be using the PLL at this point, or we could be running of a @@ -449,7 +449,7 @@ void rcc_sysclk_config(osc_src_t osc_src, xtal_t xtal, uint8_t pll_div400) rcc_pll_bypass_enable(); /* Enable the main oscillator, if needed */ - if (osc_src == OSCSRC_MOSC) { + if (src == OSCSRC_MOSC) { rcc_enable_main_osc(); } @@ -459,7 +459,7 @@ void rcc_sysclk_config(osc_src_t osc_src, xtal_t xtal, uint8_t pll_div400) /* Set XTAL value to 16MHz */ rcc_configure_xtal(xtal); /* Set the oscillator source */ - rcc_set_osc_source(osc_src); + rcc_set_osc_source(src); if (pll_div400) { /* Enable the PLL */ rcc_pll_on(); @@ -467,7 +467,7 @@ void rcc_sysclk_config(osc_src_t osc_src, xtal_t xtal, uint8_t pll_div400) rcc_change_pll_divisor(pll_div400); } else { /* We are running off a raw clock */ - switch (osc_src) { + switch (src) { case OSCSRC_PIOSC: lm4f_rcc_sysclk_freq = 16000000; break; diff --git a/lib/lm4f/systemcontrol.c b/lib/lm4f/systemcontrol.c index 691b6617..c2993b91 100644 --- a/lib/lm4f/systemcontrol.c +++ b/lib/lm4f/systemcontrol.c @@ -22,9 +22,9 @@ /** * \brief Enable the clock source for the peripheral * - * @param[in] periph peripheral and clock type to enable @see clken_t + * @param[in] periph peripheral and clock type to enable @see lm4f_clken */ -void periph_clock_enable(clken_t periph) +void periph_clock_enable(enum lm4f_clken periph) { MMIO32(SYSCTL_BASE + (periph >> 5)) |= 1 << (periph & 0x1f); } @@ -32,9 +32,9 @@ void periph_clock_enable(clken_t periph) /** * \brief Disable the clock source for the peripheral * - * @param[in] periph peripheral and clock type to enable @see clken_t + * @param[in] periph peripheral and clock type to enable @see lm4f_clken */ -void periph_clock_disable(clken_t periph) +void periph_clock_disable(enum lm4f_clken periph) { MMIO32(SYSCTL_BASE + (periph >> 5)) &= ~(1 << (periph & 0x1f)); }