f2/dma.h: Whitespace and coding-style fixes.
This commit is contained in:
Uwe Hermann
parent
9949b5dcf4
commit
5f82f28d01
@ -30,7 +30,7 @@
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#define DMA2 DMA2_BASE
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/* DMA stream base addresses (for convenience) */
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#define DMA_STREAM(port, n) (port + 0x10 + 24*n)
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#define DMA_STREAM(port, n) ((port) + 0x10 + (24 * (n)))
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#define DMA1_STREAM(n) DMA_STREAM(DMA1, n)
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#define DMA2_STREAM(n) DMA_STREAM(DMA2, n)
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@ -146,7 +146,7 @@
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#define DMA2_S7PAR DMA2_SPAR(7)
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/* DMA Stream x memory address 0 register (DMA_SxM0AR) */
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#define DMA_SM0AR(port, n) *(volatile void **)(DMA_STREAM(port, n) + 0x0C)
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#define DMA_SM0AR(port, n) *(volatile void **)(DMA_STREAM(port, n) + 0x0c)
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#define DMA1_SM0AR(n) DMA_SM0AR(DMA1, n)
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#define DMA2_SM0AR(n) DMA_SM0AR(DMA2, n)
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@ -216,161 +216,161 @@
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/* --- DMA_LISR values ----------------------------------------------------- */
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#define DMA_LISR_FEIF0 (1<<0)
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#define DMA_LISR_DMEIF0 (1<<2)
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#define DMA_LISR_TEIF0 (1<<3)
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#define DMA_LISR_HTIF0 (1<<4)
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#define DMA_LISR_TCIF0 (1<<5)
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#define DMA_LISR_FEIF0 (1 << 0)
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#define DMA_LISR_DMEIF0 (1 << 2)
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#define DMA_LISR_TEIF0 (1 << 3)
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#define DMA_LISR_HTIF0 (1 << 4)
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#define DMA_LISR_TCIF0 (1 << 5)
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#define DMA_LISR_FEIF1 (1<<6)
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#define DMA_LISR_DMEIF1 (1<<8)
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#define DMA_LISR_TEIF1 (1<<9)
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#define DMA_LISR_HTIF1 (1<<10)
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#define DMA_LISR_TCIF1 (1<<11)
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#define DMA_LISR_FEIF1 (1 << 6)
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#define DMA_LISR_DMEIF1 (1 << 8)
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#define DMA_LISR_TEIF1 (1 << 9)
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#define DMA_LISR_HTIF1 (1 << 10)
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#define DMA_LISR_TCIF1 (1 << 11)
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#define DMA_LISR_FEIF2 (1<<16)
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#define DMA_LISR_DMEIF2 (1<<18)
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#define DMA_LISR_TEIF2 (1<<19)
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#define DMA_LISR_HTIF2 (1<<20)
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#define DMA_LISR_TCIF2 (1<<21)
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#define DMA_LISR_FEIF2 (1 << 16)
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#define DMA_LISR_DMEIF2 (1 << 18)
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#define DMA_LISR_TEIF2 (1 << 19)
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#define DMA_LISR_HTIF2 (1 << 20)
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#define DMA_LISR_TCIF2 (1 << 21)
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#define DMA_LISR_FEIF3 (1<<22)
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#define DMA_LISR_DMEIF3 (1<<24)
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#define DMA_LISR_TEIF3 (1<<25)
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#define DMA_LISR_HTIF3 (1<<26)
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#define DMA_LISR_TCIF3 (1<<27)
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#define DMA_LISR_FEIF3 (1 << 22)
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#define DMA_LISR_DMEIF3 (1 << 24)
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#define DMA_LISR_TEIF3 (1 << 25)
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#define DMA_LISR_HTIF3 (1 << 26)
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#define DMA_LISR_TCIF3 (1 << 27)
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/* --- DMA_HISR values ----------------------------------------------------- */
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#define DMA_HISR_FEIF4 (1<<0)
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#define DMA_HISR_DMEIF4 (1<<2)
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#define DMA_HISR_TEIF4 (1<<3)
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#define DMA_HISR_HTIF4 (1<<4)
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#define DMA_HISR_TCIF4 (1<<5)
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#define DMA_HISR_FEIF4 (1 << 0)
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#define DMA_HISR_DMEIF4 (1 << 2)
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#define DMA_HISR_TEIF4 (1 << 3)
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#define DMA_HISR_HTIF4 (1 << 4)
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#define DMA_HISR_TCIF4 (1 << 5)
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#define DMA_HISR_FEIF5 (1<<6)
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#define DMA_HISR_DMEIF5 (1<<8)
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#define DMA_HISR_TEIF5 (1<<9)
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#define DMA_HISR_HTIF5 (1<<10)
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#define DMA_HISR_TCIF5 (1<<11)
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#define DMA_HISR_FEIF5 (1 << 6)
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#define DMA_HISR_DMEIF5 (1 << 8)
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#define DMA_HISR_TEIF5 (1 << 9)
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#define DMA_HISR_HTIF5 (1 << 10)
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#define DMA_HISR_TCIF5 (1 << 11)
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#define DMA_HISR_FEIF6 (1<<16)
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#define DMA_HISR_DMEIF6 (1<<18)
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#define DMA_HISR_TEIF6 (1<<19)
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#define DMA_HISR_HTIF6 (1<<20)
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#define DMA_HISR_TCIF6 (1<<21)
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#define DMA_HISR_FEIF6 (1 << 16)
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#define DMA_HISR_DMEIF6 (1 << 18)
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#define DMA_HISR_TEIF6 (1 << 19)
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#define DMA_HISR_HTIF6 (1 << 20)
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#define DMA_HISR_TCIF6 (1 << 21)
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#define DMA_HISR_FEIF7 (1<<22)
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#define DMA_HISR_DMEIF7 (1<<24)
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#define DMA_HISR_TEIF7 (1<<25)
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#define DMA_HISR_HTIF7 (1<<26)
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#define DMA_HISR_TCIF7 (1<<27)
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#define DMA_HISR_FEIF7 (1 << 22)
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#define DMA_HISR_DMEIF7 (1 << 24)
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#define DMA_HISR_TEIF7 (1 << 25)
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#define DMA_HISR_HTIF7 (1 << 26)
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#define DMA_HISR_TCIF7 (1 << 27)
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/* --- DMA_LIFCR values ----------------------------------------------------- */
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#define DMA_LIFCR_CFEIF0 (1<<0)
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#define DMA_LIFCR_CDMEIF0 (1<<2)
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#define DMA_LIFCR_CTEIF0 (1<<3)
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#define DMA_LIFCR_CHTIF0 (1<<4)
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#define DMA_LIFCR_CTCIF0 (1<<5)
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#define DMA_LIFCR_CFEIF0 (1 << 0)
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#define DMA_LIFCR_CDMEIF0 (1 << 2)
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#define DMA_LIFCR_CTEIF0 (1 << 3)
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#define DMA_LIFCR_CHTIF0 (1 << 4)
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#define DMA_LIFCR_CTCIF0 (1 << 5)
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#define DMA_LIFCR_CFEIF1 (1<<6)
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#define DMA_LIFCR_CDMEIF1 (1<<8)
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#define DMA_LIFCR_CTEIF1 (1<<9)
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#define DMA_LIFCR_CHTIF1 (1<<10)
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#define DMA_LIFCR_CTCIF1 (1<<11)
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#define DMA_LIFCR_CFEIF1 (1 << 6)
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#define DMA_LIFCR_CDMEIF1 (1 << 8)
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#define DMA_LIFCR_CTEIF1 (1 << 9)
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#define DMA_LIFCR_CHTIF1 (1 << 10)
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#define DMA_LIFCR_CTCIF1 (1 << 11)
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#define DMA_LIFCR_CFEIF2 (1<<16)
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#define DMA_LIFCR_CDMEIF2 (1<<18)
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#define DMA_LIFCR_CTEIF2 (1<<19)
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#define DMA_LIFCR_CHTIF2 (1<<20)
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#define DMA_LIFCR_CTCIF2 (1<<21)
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#define DMA_LIFCR_CFEIF2 (1 << 16)
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#define DMA_LIFCR_CDMEIF2 (1 << 18)
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#define DMA_LIFCR_CTEIF2 (1 << 19)
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#define DMA_LIFCR_CHTIF2 (1 << 20)
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#define DMA_LIFCR_CTCIF2 (1 << 21)
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#define DMA_LIFCR_CFEIF3 (1<<22)
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#define DMA_LIFCR_CDMEIF3 (1<<24)
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#define DMA_LIFCR_CTEIF3 (1<<25)
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#define DMA_LIFCR_CHTIF3 (1<<26)
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#define DMA_LIFCR_CTCIF3 (1<<27)
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#define DMA_LIFCR_CFEIF3 (1 << 22)
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#define DMA_LIFCR_CDMEIF3 (1 << 24)
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#define DMA_LIFCR_CTEIF3 (1 << 25)
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#define DMA_LIFCR_CHTIF3 (1 << 26)
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#define DMA_LIFCR_CTCIF3 (1 << 27)
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/* --- DMA_HIFCR values ----------------------------------------------------- */
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#define DMA_HIFCR_CFEIF4 (1<<0)
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#define DMA_HIFCR_CDMEIF4 (1<<2)
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#define DMA_HIFCR_CTEIF4 (1<<3)
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#define DMA_HIFCR_CHTIF4 (1<<4)
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#define DMA_HIFCR_CTCIF4 (1<<5)
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#define DMA_HIFCR_CFEIF4 (1 << 0)
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#define DMA_HIFCR_CDMEIF4 (1 << 2)
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#define DMA_HIFCR_CTEIF4 (1 << 3)
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#define DMA_HIFCR_CHTIF4 (1 << 4)
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#define DMA_HIFCR_CTCIF4 (1 << 5)
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#define DMA_HIFCR_CFEIF5 (1<<6)
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#define DMA_HIFCR_CDMEIF5 (1<<8)
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#define DMA_HIFCR_CTEIF5 (1<<9)
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#define DMA_HIFCR_CHTIF5 (1<<10)
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#define DMA_HIFCR_CTCIF5 (1<<11)
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#define DMA_HIFCR_CFEIF5 (1 << 6)
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#define DMA_HIFCR_CDMEIF5 (1 << 8)
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#define DMA_HIFCR_CTEIF5 (1 << 9)
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#define DMA_HIFCR_CHTIF5 (1 << 10)
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#define DMA_HIFCR_CTCIF5 (1 << 11)
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#define DMA_HIFCR_CFEIF6 (1<<16)
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#define DMA_HIFCR_CDMEIF6 (1<<18)
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#define DMA_HIFCR_CTEIF6 (1<<19)
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#define DMA_HIFCR_CHTIF6 (1<<20)
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#define DMA_HIFCR_CTCIF6 (1<<21)
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#define DMA_HIFCR_CFEIF6 (1 << 16)
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#define DMA_HIFCR_CDMEIF6 (1 << 18)
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#define DMA_HIFCR_CTEIF6 (1 << 19)
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#define DMA_HIFCR_CHTIF6 (1 << 20)
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#define DMA_HIFCR_CTCIF6 (1 << 21)
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#define DMA_HIFCR_CFEIF7 (1<<22)
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#define DMA_HIFCR_CDMEIF7 (1<<24)
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#define DMA_HIFCR_CTEIF7 (1<<25)
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#define DMA_HIFCR_CHTIF7 (1<<26)
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#define DMA_HIFCR_CTCIF7 (1<<27)
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#define DMA_HIFCR_CFEIF7 (1 << 22)
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#define DMA_HIFCR_CDMEIF7 (1 << 24)
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#define DMA_HIFCR_CTEIF7 (1 << 25)
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#define DMA_HIFCR_CHTIF7 (1 << 26)
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#define DMA_HIFCR_CTCIF7 (1 << 27)
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/* --- DMA_SxCR values ----------------------------------------------------- */
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#define DMA_SxCR_EN (1<<0)
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#define DMA_SxCR_DMEIE (1<<1)
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#define DMA_SxCR_TEIE (1<<2)
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#define DMA_SxCR_HTIE (1<<3)
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#define DMA_SxCR_TCIE (1<<4)
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#define DMA_SxCR_PFCTRL (1<<5)
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#define DMA_SxCR_EN (1 << 0)
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#define DMA_SxCR_DMEIE (1 << 1)
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#define DMA_SxCR_TEIE (1 << 2)
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#define DMA_SxCR_HTIE (1 << 3)
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#define DMA_SxCR_TCIE (1 << 4)
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#define DMA_SxCR_PFCTRL (1 << 5)
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#define DMA_SxCR_DIR_SHIFT 6
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#define DMA_SxCR_DIR_PERIPHERAL_TO_MEM (0<<6)
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#define DMA_SxCR_DIR_MEM_TO_PERIPHERAL (1<<6)
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#define DMA_SxCR_DIR_MEM_TO_MEM (2<<6)
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#define DMA_SxCR_DIR_PERIPHERAL_TO_MEM (0 << 6)
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#define DMA_SxCR_DIR_MEM_TO_PERIPHERAL (1 << 6)
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#define DMA_SxCR_DIR_MEM_TO_MEM (2 << 6)
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#define DMA_SxCR_CIRC (1<<8)
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#define DMA_SxCR_PINC (1<<9)
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#define DMA_SxCR_MINC (1<<10)
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#define DMA_SxCR_CIRC (1 << 8)
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#define DMA_SxCR_PINC (1 << 9)
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#define DMA_SxCR_MINC (1 << 10)
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#define DMA_SxCR_PSIZE_SHIFT 11
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#define DMA_SxCR_PSIZE_8BIT (0<<11)
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#define DMA_SxCR_PSIZE_16BIT (1<<11)
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#define DMA_SxCR_PSIZE_32BIT (2<<11)
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#define DMA_SxCR_PSIZE_8BIT (0 << 11)
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#define DMA_SxCR_PSIZE_16BIT (1 << 11)
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#define DMA_SxCR_PSIZE_32BIT (2 << 11)
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#define DMA_SxCR_MSIZE_SHIFT 13
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#define DMA_SxCR_MSIZE_8BIT (0<<13)
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#define DMA_SxCR_MSIZE_16BIT (1<<13)
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#define DMA_SxCR_MSIZE_32BIT (2<<13)
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#define DMA_SxCR_MSIZE_8BIT (0 << 13)
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#define DMA_SxCR_MSIZE_16BIT (1 << 13)
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#define DMA_SxCR_MSIZE_32BIT (2 << 13)
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#define DMA_SxCR_PINCOS (1<<15)
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#define DMA_SxCR_PINCOS (1 << 15)
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#define DMA_SxCR_PL_SHIFT 16
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#define DMA_SxCR_PL_LOW (0<<16)
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#define DMA_SxCR_PL_MEDIUM (1<<16)
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#define DMA_SxCR_PL_HIGH (2<<16)
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#define DMA_SxCR_PL_VERY_HIGH (3<<16)
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#define DMA_SxCR_PL_LOW (0 << 16)
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#define DMA_SxCR_PL_MEDIUM (1 << 16)
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#define DMA_SxCR_PL_HIGH (2 << 16)
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#define DMA_SxCR_PL_VERY_HIGH (3 << 16)
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#define DMA_SxCR_DBM (1<<18)
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#define DMA_SxCR_CT (1<<18)
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#define DMA_SxCR_DBM (1 << 18)
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#define DMA_SxCR_CT (1 << 18)
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#define DMA_SxCR_PBURST_SHIFT 21
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#define DMA_SxCR_PBURST_SINGLE (0<<21)
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#define DMA_SxCR_PBURST_INCR4 (1<<21)
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#define DMA_SxCR_PBURST_INCR8 (2<<21)
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#define DMA_SxCR_PBURST_INCR16 (3<<21)
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#define DMA_SxCR_PBURST_SINGLE (0 << 21)
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#define DMA_SxCR_PBURST_INCR4 (1 << 21)
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#define DMA_SxCR_PBURST_INCR8 (2 << 21)
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#define DMA_SxCR_PBURST_INCR16 (3 << 21)
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#define DMA_SxCR_MBURST_SHIFT 23
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#define DMA_SxCR_MBURST_SINGLE (0<<23)
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#define DMA_SxCR_MBURST_INCR4 (1<<23)
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#define DMA_SxCR_MBURST_INCR8 (2<<23)
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#define DMA_SxCR_MBURST_INCR16 (3<<23)
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#define DMA_SxCR_MBURST_SINGLE (0 << 23)
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#define DMA_SxCR_MBURST_INCR4 (1 << 23)
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#define DMA_SxCR_MBURST_INCR8 (2 << 23)
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#define DMA_SxCR_MBURST_INCR16 (3 << 23)
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#define DMA_SxCR_CHSEL_SHIFT 25
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#define DMA_SxCR_CHSEL(n) (n<<25)
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#define DMA_SxCR_CHSEL(n) (n << 25)
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/* --- DMA_SxNDTR values --------------------------------------------------- */
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@ -391,21 +391,21 @@
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/* --- DMA_SxFCR values ---------------------------------------------------- */
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#define DMA_SxFCR_FTH_SHIFT 0
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#define DMA_SxFCR_FTH_1_4_FULL (0<<0)
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#define DMA_SxFCR_FTH_2_4_FULL (1<<0)
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#define DMA_SxFCR_FTH_3_4_FULL (2<<0)
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#define DMA_SxFCR_FTH_4_4_FULL (3<<0)
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#define DMA_SxFCR_FTH_1_4_FULL (0 << 0)
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#define DMA_SxFCR_FTH_2_4_FULL (1 << 0)
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#define DMA_SxFCR_FTH_3_4_FULL (2 << 0)
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#define DMA_SxFCR_FTH_4_4_FULL (3 << 0)
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#define DMA_SxFCR_DMDIS (1<<2)
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#define DMA_SxFCR_DMDIS (1 << 2)
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#define DMA_SxFCR_FS_SHIFT 3
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#define DMA_SxFCR_FS_LT_1_4_FULL (0<<0)
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#define DMA_SxFCR_FS_LT_2_4_FULL (1<<0)
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#define DMA_SxFCR_FS_LT_3_4_FULL (2<<0)
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#define DMA_SxFCR_FS_LT_4_4_FULL (3<<0)
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#define DMA_SxFCR_FS_FULL (4<<3)
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#define DMA_SxFCR_FS_EMPTY (5<<3)
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#define DMA_SxFCR_FS_LT_1_4_FULL (0 << 0)
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#define DMA_SxFCR_FS_LT_2_4_FULL (1 << 0)
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#define DMA_SxFCR_FS_LT_3_4_FULL (2 << 0)
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#define DMA_SxFCR_FS_LT_4_4_FULL (3 << 0)
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#define DMA_SxFCR_FS_FULL (4 << 3)
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#define DMA_SxFCR_FS_EMPTY (5 << 3)
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#define DMA_SxFCR_FEIE (1<<7)
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#define DMA_SxFCR_FEIE (1 << 7)
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#endif
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