diff --git a/src/platforms/stlink/Readme b/src/platforms/stlink/Readme
index b20a6db1..ec9e05f5 100644
--- a/src/platforms/stlink/Readme
+++ b/src/platforms/stlink/Readme
@@ -9,3 +9,9 @@ ID Pins PC13/14 unconnected       PC 13 pulled low
 LED STLINK      PA8, active High  PA9, Dual Led
 MCO Out         NA                PA8
 RESET(Target)   T_JRST(PB1)       NRST (PB0)
+
+On the NucleoXXXP boards, e.g. NUCLEO-L4R5ZI (144 pin) or
+NUCLEO-L452RE-P (64 pins), by default nRst is not connected. To reach the
+target nRST pin with the "mon connect_srst enable" option, the right NRST
+jumper must be placed. On Nucleo144-P boards it is JP3, on NUCLEO64-P
+boards it is JP4.
diff --git a/src/platforms/stlink/platform.c b/src/platforms/stlink/platform.c
index 5e2ca3bf..591c2cba 100644
--- a/src/platforms/stlink/platform.c
+++ b/src/platforms/stlink/platform.c
@@ -90,10 +90,21 @@ void platform_init(void)
 
 void platform_srst_set_val(bool assert)
 {
-	if (assert)
-		gpio_clear(SRST_PORT, srst_pin);
-	else
-		gpio_set(SRST_PORT, srst_pin);
+	uint32_t crl = GPIOB_CRL;
+	uint32_t shift = (srst_pin == GPIO0) ? 0 : 4;
+	uint32_t mask = 0xf << shift;
+	crl &= ~mask;
+	if (assert) {
+		/* Set SRST as Open-Drain, 50 Mhz, low.*/
+		GPIOB_BRR = srst_pin;
+		GPIOB_CRL = crl | (7 << shift);
+	} else {
+		/* Set SRST as input, pull-up.
+		 * SRST might be unconnected, e.g on Nucleo-P!*/
+		GPIOB_CRL = crl | (8 << shift);
+		GPIOB_BSRR = srst_pin;
+	}
+	while (gpio_get(SRST_PORT, srst_pin) == assert) {};
 }
 
 bool platform_srst_get_val()