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efm32: generate _MASK constants

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constants are generated for all fields that either have named values or
length > 1
This commit is contained in:
chrysn 2012-03-04 16:57:43 +01:00
parent bc1bff477b
commit 61b649370f
3 changed files with 38 additions and 1 deletions
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33
include/libopencm3/efm32/tinygecko/cmu.h
View File

@ -90,6 +90,7 @@
#define CMU_CTRL_DBGCLK_AUXHFRCO (0<<28)
#define CMU_CTRL_DBGCLK_HFCLK (1<<28)
#define CMU_CTRL_DBGCLK_MASK (0x1<<28)
#define CMU_CTRL_CLKOUTSEL1_LFRCO (0<<23)
#define CMU_CTRL_CLKOUTSEL1_LFXO (1<<23)
#define CMU_CTRL_CLKOUTSEL1_HFCLK (2<<23)
@ -98,6 +99,7 @@
#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (5<<23)
#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (6<<23)
#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (7<<23)
#define CMU_CTRL_CLKOUTSEL1_MASK (0x7<<23)
#define CMU_CTRL_CLKOUTSEL0_LFRCO (0<<20)
#define CMU_CTRL_CLKOUTSEL0_LFXO (1<<20)
#define CMU_CTRL_CLKOUTSEL0_HFCLK (2<<20)
@ -106,29 +108,37 @@
#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (5<<20)
#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (6<<20)
#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (7<<20)
#define CMU_CTRL_CLKOUTSEL0_MASK (0x7<<20)
#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (0<<18)
#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (1<<18)
#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (2<<18)
#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (3<<18)
#define CMU_CTRL_LFXOTIMEOUT_MASK (0x3<<18)
#define CMU_CTRL_LFXOBUFCUR (1<<17)
#define CMU_CTRL_LXFOBOOST_70PCENT (0<<13)
#define CMU_CTRL_LXFOBOOST_100PCENT (1<<13)
#define CMU_CTRL_LXFOBOOST_MASK (0x1<<13)
#define CMU_CTRL_LFXOMODE_XTAL (0<<11)
#define CMU_CTRL_LFXOMODE_BUFEXTCLK (1<<11)
#define CMU_CTRL_LFXOMODE_DIGEXTCLK (2<<11)
#define CMU_CTRL_LFXOMODE_MASK (0x3<<11)
#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (0<<9)
#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (1<<9)
#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (2<<9)
#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (3<<9)
#define CMU_CTRL_HFXOTIMEOUT_MASK (0x3<<9)
#define CMU_CTRL_HFXOGLITCHDETEN (1<<7)
/* No values defined for the field HFXOBUFCUR */
#define CMU_CTRL_HFXOBUFCUR_MASK (0x3<<5)
#define CMU_CTRL_HFXOBOOST_50PCENT (0<<2)
#define CMU_CTRL_HFXOBOOST_70PCENT (1<<2)
#define CMU_CTRL_HFXOBOOST_80PCENT (2<<2)
#define CMU_CTRL_HFXOBOOST_100PCENT (3<<2)
#define CMU_CTRL_HFXOBOOST_MASK (0x3<<2)
#define CMU_CTRL_HFXOMODE_XTAL (0<<0)
#define CMU_CTRL_HFXOMODE_BUFEXTCLK (1<<0)
#define CMU_CTRL_HFXOMODE_DIGEXTCLK (2<<0)
#define CMU_CTRL_HFXOMODE_MASK (0x3<<0)
/** @} */
@ -172,6 +182,7 @@
#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (7<<0)
#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (8<<0)
#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (9<<0)
#define CMU_HFPERCLKDIV_HFPERCLKDIV_MASK (0x7<<0)
/** @} */
@ -184,13 +195,16 @@
*/
/* No values defined for the field SUDELAY */
#define CMU_HFRCOCTRL_SUDELAY_MASK (0x1f<<12)
#define CMU_HFRCOCTRL_BAND_1MHZ (0<<8)
#define CMU_HFRCOCTRL_BAND_7MHZ (1<<8)
#define CMU_HFRCOCTRL_BAND_11MHZ (2<<8)
#define CMU_HFRCOCTRL_BAND_14MHZ (3<<8)
#define CMU_HFRCOCTRL_BAND_21MHZ (4<<8)
#define CMU_HFRCOCTRL_BAND_28MHZ (5<<8)
#define CMU_HFRCOCTRL_BAND_MASK (0x7<<8)
/* No values defined for the field TUNING */
#define CMU_HFRCOCTRL_TUNING_MASK (0xff<<0)
/** @} */
@ -208,7 +222,9 @@
#define CMU_AUXHFRCOCTRL_BAND_1MHZ (3<<8)
#define CMU_AUXHFRCOCTRL_BAND_28MHZ (6<<8)
#define CMU_AUXHFRCOCTRL_BAND_21MHZ (7<<8)
#define CMU_AUXHFRCOCTRL_BAND_MASK (0x7<<8)
/* No values defined for the field TUNING */
#define CMU_AUXHFRCOCTRL_TUNING_MASK (0xff<<0)
/** @} */
@ -227,11 +243,13 @@
#define CMU_CALCTRL_DOWNSEL_HFRCO (3<<3)
#define CMU_CALCTRL_DOWNSEL_LFRCO (4<<3)
#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (5<<3)
#define CMU_CALCTRL_DOWNSEL_MASK (0x7<<3)
#define CMU_CALCTRL_UPSEL_HFXO (0<<0)
#define CMU_CALCTRL_UPSEL_LFXO (1<<0)
#define CMU_CALCTRL_UPSEL_HFRCO (2<<0)
#define CMU_CALCTRL_UPSEL_LFRCO (3<<0)
#define CMU_CALCTRL_UPSEL_AUXHFRCO (4<<0)
#define CMU_CALCTRL_UPSEL_MASK (0x7<<0)
/** @} */
@ -270,6 +288,7 @@
#define CMU_CMD_HFCLKSEL_HFXO (2<<0)
#define CMU_CMD_HFCLKSEL_LFRCO (3<<0)
#define CMU_CMD_HFCLKSEL_LFXO (4<<0)
#define CMU_CMD_HFCLKSEL_MASK (0x7<<0)
/** @} */
@ -283,16 +302,20 @@
#define CMU_LFCLKSEL_LFBE_DISABLED (0<<20)
#define CMU_LFCLKSEL_LFBE_ULFRCO (1<<20)
#define CMU_LFCLKSEL_LFBE_MASK (0x1<<20)
#define CMU_LFCLKSEL_LFAE_DISABLED (0<<16)
#define CMU_LFCLKSEL_LFAE_ULFRCO (1<<16)
#define CMU_LFCLKSEL_LFAE_MASK (0x1<<16)
#define CMU_LFCLKSEL_LFB_DISABLED (0<<2)
#define CMU_LFCLKSEL_LFB_LFRCO (1<<2)
#define CMU_LFCLKSEL_LFB_LFXO (2<<2)
#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (3<<2)
#define CMU_LFCLKSEL_LFB_MASK (0x3<<2)
#define CMU_LFCLKSEL_LFA_DISABLED (0<<0)
#define CMU_LFCLKSEL_LFA_LFRCO (1<<0)
#define CMU_LFCLKSEL_LFA_LFXO (2<<0)
#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (3<<0)
#define CMU_LFCLKSEL_LFA_MASK (0x3<<0)
/** @} */
@ -384,6 +407,7 @@
#define CMU_FREEZE_REGFREEZE_UPDATE (0<<0)
#define CMU_FREEZE_REGFREEZE_FREEZE (1<<0)
#define CMU_FREEZE_REGFREEZE_MASK (0x1<<0)
/** @} */
@ -426,6 +450,7 @@
#define CMU_LFAPRESC0_LCD_DIV32 (1<<12)
#define CMU_LFAPRESC0_LCD_DIV64 (2<<12)
#define CMU_LFAPRESC0_LCD_DIV128 (3<<12)
#define CMU_LFAPRESC0_LCD_MASK (0x3<<12)
#define CMU_LFAPRESC0_LETIMER0_DIV1 (0<<8)
#define CMU_LFAPRESC0_LETIMER0_DIV2 (1<<8)
#define CMU_LFAPRESC0_LETIMER0_DIV4 (2<<8)
@ -442,6 +467,7 @@
#define CMU_LFAPRESC0_LETIMER0_DIV8192 (13<<8)
#define CMU_LFAPRESC0_LETIMER0_DIV16384 (14<<8)
#define CMU_LFAPRESC0_LETIMER0_DIV32768 (15<<8)
#define CMU_LFAPRESC0_LETIMER0_MASK (0xf<<8)
#define CMU_LFAPRESC0_RTC_DIV1 (0<<4)
#define CMU_LFAPRESC0_RTC_DIV2 (1<<4)
#define CMU_LFAPRESC0_RTC_DIV4 (2<<4)
@ -458,10 +484,12 @@
#define CMU_LFAPRESC0_RTC_DIV8192 (13<<4)
#define CMU_LFAPRESC0_RTC_DIV16384 (14<<4)
#define CMU_LFAPRESC0_RTC_DIV32768 (15<<4)
#define CMU_LFAPRESC0_RTC_MASK (0xf<<4)
#define CMU_LFAPRESC0_LESENSE_DIV1 (0<<0)
#define CMU_LFAPRESC0_LESENSE_DIV2 (1<<0)
#define CMU_LFAPRESC0_LESENSE_DIV4 (2<<0)
#define CMU_LFAPRESC0_LESENSE_DIV8 (3<<0)
#define CMU_LFAPRESC0_LESENSE_MASK (0x3<<0)
/** @} */
@ -477,6 +505,7 @@
#define CMU_LFBPRESC0_LEUART0_DIV2 (1<<0)
#define CMU_LFBPRESC0_LEUART0_DIV4 (2<<0)
#define CMU_LFBPRESC0_LEUART0_DIV8 (3<<0)
#define CMU_LFBPRESC0_LEUART0_MASK (0x3<<0)
/** @} */
@ -490,6 +519,7 @@
#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (0<<1)
#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (1<<1)
#define CMU_PCNTCTRL_PCNT0CLKSEL_MASK (0x1<<1)
#define CMU_PCNTCTRL_PCNT0CLKEN (1<<0)
/** @} */
@ -510,8 +540,10 @@
#define CMU_LCDCTRL_VBFDIV_DIV32 (5<<4)
#define CMU_LCDCTRL_VBFDIV_DIV64 (6<<4)
#define CMU_LCDCTRL_VBFDIV_DIV128 (7<<4)
#define CMU_LCDCTRL_VBFDIV_MASK (0x7<<4)
#define CMU_LCDCTRL_VBOOSTEN (1<<3)
/* No values defined for the field FDIV */
#define CMU_LCDCTRL_FDIV_MASK (0x7<<0)
/** @} */
@ -525,6 +557,7 @@
#define CMU_ROUTE_LOCATION_LOC0 (0<<4)
#define CMU_ROUTE_LOCATION_LOC1 (1<<4)
#define CMU_ROUTE_LOCATION_MASK (0x7<<4)
#define CMU_ROUTE_CLKOUT1PEN (1<<1)
#define CMU_ROUTE_CLKOUT0PEN (1<<0)

1
include/libopencm3/efm32/tinygecko/emu.h
View File

@ -66,6 +66,7 @@
#define EMU_CTRL_EM4CTRL_TWO (2<<2)
#define EMU_CTRL_EM4CTRL_THREE (3<<2)
#define EMU_CTRL_EM4CTRL_MASK (0x3<<2)
#define EMU_CTRL_EM2BLOCK (1<<1) /**< When this bit is set, no mode lower than EM1 will be entered */
#define EMU_CTRL_EMVREG (1<<0) /**< When this bit is set, the voltage regulator will stay on in modes lower than EM1 */

5
include/libopencm3/efm32/tinygecko/generate.py
View File

@ -93,7 +93,10 @@ def yaml2h(filenamebase):
else:
# FIXME: this should require the 'type' parameter to be set on this field
outfile.write("/* No values defined for the field %s */\n"%field['name'])
# FIXME: define mask
if "values" in field or field.get("length", 1) != 1:
mask = "(%#x<<%s)"%(~(~0<<field.get('length', 1)), field['shift'])
define("%s_%s_%s_MASK"%(data['shortname'], regdata['name'], field['name']), mask)
else:
for value in regdata['values']:
define("%s_%s_%s"%(data['shortname'], regdata['name'], value['name']), value['value'], value.get('doc', None))