diff --git a/include/libopencm3/stm32/f3/rcc.h b/include/libopencm3/stm32/f3/rcc.h
index c813fea1..7961b851 100644
--- a/include/libopencm3/stm32/f3/rcc.h
+++ b/include/libopencm3/stm32/f3/rcc.h
@@ -106,21 +106,21 @@
 /* PLLMUL: PLL multiplication factor */
 #define RCC_CFGR_PLLMUL_SHIFT			18
 #define RCC_CFGR_PLLMUL_MASK			0xF
-#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X2		0x0
-#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X3		0x1
-#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X4		0x2
-#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X5		0x3
-#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X6		0x4
-#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X7		0x5
-#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X8		0x6
-#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X9		0x7
-#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X10		0x8
-#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X11		0x9
-#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X12		0xA
-#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X13		0xB
-#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X14		0xC
-#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X15		0xD
-#define RCC_CFGR_PLLMUL_PLL_IN_CLK_X16		0xE
+#define RCC_CFGR_PLLMUL_MUL2		0x0
+#define RCC_CFGR_PLLMUL_MUL3		0x1
+#define RCC_CFGR_PLLMUL_MUL4		0x2
+#define RCC_CFGR_PLLMUL_MUL5		0x3
+#define RCC_CFGR_PLLMUL_MUL6		0x4
+#define RCC_CFGR_PLLMUL_MUL7		0x5
+#define RCC_CFGR_PLLMUL_MUL8		0x6
+#define RCC_CFGR_PLLMUL_MUL9		0x7
+#define RCC_CFGR_PLLMUL_MUL10		0x8
+#define RCC_CFGR_PLLMUL_MUL11		0x9
+#define RCC_CFGR_PLLMUL_MUL12		0xA
+#define RCC_CFGR_PLLMUL_MUL13		0xB
+#define RCC_CFGR_PLLMUL_MUL14		0xC
+#define RCC_CFGR_PLLMUL_MUL15		0xD
+#define RCC_CFGR_PLLMUL_MUL16		0xE
 
 /* PPRE2: APB high-speed prescaler (APB2) */
 #define RCC_CFGR_PPRE2_SHIFT			11
diff --git a/lib/stm32/f3/rcc.c b/lib/stm32/f3/rcc.c
index 0a69efee..1c86cf44 100644
--- a/lib/stm32/f3/rcc.c
+++ b/lib/stm32/f3/rcc.c
@@ -46,7 +46,7 @@ uint32_t rcc_apb2_frequency = 8000000;
 
 const struct rcc_clock_scale rcc_hsi_8mhz[RCC_CLOCK_END] = {
 	{ /* 44MHz */
-		.pll = RCC_CFGR_PLLMUL_PLL_IN_CLK_X11,
+		.pll = RCC_CFGR_PLLMUL_MUL11,
 		.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,
 		.hpre = RCC_CFGR_HPRE_DIV_NONE,
 		.ppre1 = RCC_CFGR_PPRE1_DIV_2,
@@ -57,7 +57,7 @@ const struct rcc_clock_scale rcc_hsi_8mhz[RCC_CLOCK_END] = {
 		.apb2_frequency = 44000000,
 	},
 	{ /* 48MHz */
-		.pll = RCC_CFGR_PLLMUL_PLL_IN_CLK_X12,
+		.pll = RCC_CFGR_PLLMUL_MUL12,
 		.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,
 		.hpre = RCC_CFGR_HPRE_DIV_NONE,
 		.ppre1 = RCC_CFGR_PPRE1_DIV_2,
@@ -68,7 +68,7 @@ const struct rcc_clock_scale rcc_hsi_8mhz[RCC_CLOCK_END] = {
 		.apb2_frequency = 48000000,
 	},
 	{ /* 64MHz */
-		.pll = RCC_CFGR_PLLMUL_PLL_IN_CLK_X16,
+		.pll = RCC_CFGR_PLLMUL_MUL16,
 		.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,
 		.hpre = RCC_CFGR_HPRE_DIV_NONE,
 		.ppre1 = RCC_CFGR_PPRE1_DIV_2,