stm32l0: rcc: add new peripheral enable bits
I2C3, USART4/5, GPIOE
This commit is contained in:
Karl Palsson
parent
b556a72fdb
commit
623fabca5f
@ -253,6 +253,7 @@
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/* --- RCC_IOPRSTR - GPIO Reset Register */
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#define RCC_IOPPRSTR_IOPHRST (1<<7)
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#define RCC_IOPPRSTR_IOPERST (1<<4)
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#define RCC_IOPPRSTR_IOPDRST (1<<3)
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#define RCC_IOPPRSTR_IOPCRST (1<<2)
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#define RCC_IOPPRSTR_IOPBRST (1<<1)
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@ -280,12 +281,15 @@
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/* --- RCC_APB1RSTR values ------------------------------------------------- */
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#define RCC_APB1RSTR_LPTIM1RST (1 << 31)
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#define RCC_APB1RSTR_I2C3RST (1 << 30)
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#define RCC_APB1RSTR_DACRST (1 << 29)
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#define RCC_APB1RSTR_PWRRST (1 << 28)
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#define RCC_APB1RSTR_CRSRST (1 << 27)
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#define RCC_APB1RSTR_USBRST (1 << 23)
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#define RCC_APB1RSTR_I2C2RST (1 << 22)
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#define RCC_APB1RSTR_I2C1RST (1 << 21)
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#define RCC_APB1RSTR_USART5RST (1 << 20)
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#define RCC_APB1RSTR_USART4RST (1 << 19)
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#define RCC_APB1RSTR_LPUART1RST (1 << 18)
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#define RCC_APB1RSTR_USART2RST (1 << 17)
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#define RCC_APB1RSTR_SPI2RST (1 << 14)
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@ -299,6 +303,7 @@
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/* --- RCC_IOPENR - GPIO clock enable register */
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#define RCC_IOPENR_IOPHEN (1<<7)
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#define RCC_IOPENR_IOPEEN (1<<4)
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#define RCC_IOPENR_IOPDEN (1<<3)
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#define RCC_IOPENR_IOPCEN (1<<2)
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#define RCC_IOPENR_IOPBEN (1<<1)
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@ -347,6 +352,8 @@
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#define RCC_APB1ENR_USBEN (1 << 23)
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#define RCC_APB1ENR_I2C2EN (1 << 22)
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#define RCC_APB1ENR_I2C1EN (1 << 21)
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#define RCC_APB1ENR_USART5EN (1 << 20)
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#define RCC_APB1ENR_USART4EN (1 << 19)
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#define RCC_APB1ENR_LPUART1EN (1 << 18)
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#define RCC_APB1ENR_USART2EN (1 << 17)
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#define RCC_APB1ENR_SPI2EN (1 << 14)
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@ -361,6 +368,7 @@
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/* --- RCC_IOPSMENR - GPIO Clock enable in sleep mode */
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#define RCC_IOPSMENR_IOPHSMEN (1<<7)
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#define RCC_IOPSMENR_IOPESMEN (1<<4)
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#define RCC_IOPSMENR_IOPDSMEN (1<<3)
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#define RCC_IOPSMENR_IOPCSMEN (1<<2)
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#define RCC_IOPSMENR_IOPBSMEN (1<<1)
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@ -389,12 +397,15 @@
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/* --- RCC_APB1SMENR - APB1 periph clock in sleep mode */
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#define RCC_APB1SMENR_LPTIM1SMEN (1 << 31)
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#define RCC_APB1SMENR_I2C3SMEN (1 << 30)
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#define RCC_APB1SMENR_DACSMEN (1 << 29)
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#define RCC_APB1SMENR_PWRSMEN (1 << 28)
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#define RCC_APB1SMENR_CRSSMEN (1 << 27)
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#define RCC_APB1SMENR_USBSMEN (1 << 23)
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#define RCC_APB1SMENR_I2C2SMEN (1 << 22)
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#define RCC_APB1SMENR_I2C1SMEN (1 << 21)
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#define RCC_APB1SMENR_USART5SMEN (1 << 20)
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#define RCC_APB1SMENR_USART4SMEN (1 << 19)
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#define RCC_APB1SMENR_LPUART1SMEN (1 << 18)
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#define RCC_APB1SMENR_USART2SMEN (1 << 17)
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#define RCC_APB1SMENR_SPI2SMEN (1 << 14)
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@ -416,6 +427,12 @@
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#define RCC_CCIPR_LPTIM1SEL_SHIFT 18
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#define RCC_CCIPR_LPTIM1SEL_MASK 0x3
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#define RCC_CCIPR_I2C3SEL_APB 0
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#define RCC_CCIPR_I2C3SEL_SYS 1
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#define RCC_CCIPR_I2C3SEL_HSI16 2
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#define RCC_CCIPR_I2C3SEL_SHIFT 16
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#define RCC_CCIPR_I2C3SEL_MASK 0x3
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#define RCC_CCIPR_I2C1SEL_APB 0
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#define RCC_CCIPR_I2C1SEL_SYS 1
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#define RCC_CCIPR_I2C1SEL_HSI16 2
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@ -496,6 +513,7 @@ enum rcc_periph_clken {
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RCC_GPIOB = _REG_BIT(0x2c, 1),
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RCC_GPIOC = _REG_BIT(0x2c, 2),
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RCC_GPIOD = _REG_BIT(0x2c, 3),
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RCC_GPIOE = _REG_BIT(0x2c, 4),
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RCC_GPIOH = _REG_BIT(0x2c, 7),
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/* AHB peripherals */
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@ -526,12 +544,15 @@ enum rcc_periph_clken {
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RCC_SPI2 = _REG_BIT(0x38, 14),
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RCC_USART2 = _REG_BIT(0x38, 17),
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RCC_LPUART1 = _REG_BIT(0x38, 18),
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RCC_USART4 = _REG_BIT(0x38, 19),
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RCC_USART5 = _REG_BIT(0x38, 20),
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RCC_I2C1 = _REG_BIT(0x38, 21),
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RCC_I2C2 = _REG_BIT(0x38, 22),
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RCC_USB = _REG_BIT(0x38, 23),
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RCC_CRS = _REG_BIT(0x38, 27),
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RCC_PWR = _REG_BIT(0x38, 28),
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RCC_DAC = _REG_BIT(0x38, 29),
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RCC_I2C3 = _REG_BIT(0x38, 30),
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RCC_LPTIM1 = _REG_BIT(0x38, 31),
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/* GPIO peripherals in sleep mode */
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@ -539,6 +560,7 @@ enum rcc_periph_clken {
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SCC_GPIOB = _REG_BIT(0x3c, 1),
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SCC_GPIOC = _REG_BIT(0x3c, 2),
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SCC_GPIOD = _REG_BIT(0x3c, 3),
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SCC_GPIOE = _REG_BIT(0x3c, 4),
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SCC_GPIOH = _REG_BIT(0x3c, 7),
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/* AHB peripherals in sleep mode */
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@ -569,12 +591,15 @@ enum rcc_periph_clken {
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SCC_SPI2 = _REG_BIT(0x48, 14),
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SCC_USART2 = _REG_BIT(0x48, 17),
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SCC_LPUART1 = _REG_BIT(0x48, 18),
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SCC_USART4 = _REG_BIT(0x48, 19),
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SCC_USART5 = _REG_BIT(0x48, 20),
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SCC_I2C1 = _REG_BIT(0x48, 21),
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SCC_I2C2 = _REG_BIT(0x48, 22),
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SCC_USB = _REG_BIT(0x48, 23),
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SCC_CRS = _REG_BIT(0x48, 27),
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SCC_PWR = _REG_BIT(0x48, 28),
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SCC_DAC = _REG_BIT(0x48, 29),
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SCC_I2C3 = _REG_BIT(0x48, 30),
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SCC_LPTIM1 = _REG_BIT(0x48, 31),
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};
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@ -584,6 +609,7 @@ enum rcc_periph_rst {
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RST_GPIOB = _REG_BIT(0x1c, 1),
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RST_GPIOC = _REG_BIT(0x1c, 2),
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RST_GPIOD = _REG_BIT(0x1c, 3),
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RST_GPIOE = _REG_BIT(0x1c, 4),
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RST_GPIOH = _REG_BIT(0x1c, 7),
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/* AHB peripherals */
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@ -613,12 +639,15 @@ enum rcc_periph_rst {
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RST_SPI2 = _REG_BIT(0x28, 14),
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RST_USART2 = _REG_BIT(0x28, 17),
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RST_LPUART1 = _REG_BIT(0x28, 18),
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RST_USART4 = _REG_BIT(0x28, 19),
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RST_USART5 = _REG_BIT(0x28, 20),
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RST_I2C1 = _REG_BIT(0x28, 21),
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RST_I2C2 = _REG_BIT(0x28, 22),
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RST_USB = _REG_BIT(0x28, 23),
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RST_CRS = _REG_BIT(0x28, 27),
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RST_PWR = _REG_BIT(0x28, 28),
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RST_DAC = _REG_BIT(0x28, 29),
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RST_I2C3 = _REG_BIT(0x28, 30),
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RST_LPTIM1 = _REG_BIT(0x28, 31),
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};
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#include <libopencm3/stm32/common/rcc_common_all.h>
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