jackcartersmith/blackmagic
1
0
Fork 0
Code Issues Pull Requests Releases Activity

[Style] Fixed style in the newly added F3 code.

Browse Source
This commit is contained in:
Piotr Esden-Tempski 2013-07-04 21:10:56 -07:00
parent b6231dbb49
commit 62e6635992
16 changed files with 693 additions and 584 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
include/libopencm3/stm32/common/gpio_common_f234.h
View File

@ -54,7 +54,7 @@ specific memorymap.h header before including this header file.*/
/**@}*/ /**@}*/
/* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------------- */ /* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------- */
/* Port mode register (GPIOx_MODER) */ /* Port mode register (GPIOx_MODER) */
#define GPIO_MODER(port) MMIO32(port + 0x00) #define GPIO_MODER(port) MMIO32(port + 0x00)

4
include/libopencm3/stm32/common/gpio_common_f24.h
View File

@ -51,7 +51,7 @@ specific memorymap.h header before including this header file.*/
#define GPIOI GPIO_PORT_I_BASE #define GPIOI GPIO_PORT_I_BASE
/**@}*/ /**@}*/
/* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------------- */ /* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------- */
/* Port mode register (GPIOx_MODER) */ /* Port mode register (GPIOx_MODER) */
#define GPIOG_MODER GPIO_MODER(GPIOG) #define GPIOG_MODER GPIO_MODER(GPIOG)
@ -108,4 +108,4 @@ specific memorymap.h header before including this header file.*/
#else #else
#warning "gpio_common_f24.h should not be included explicitly, only via gpio.h" #warning "gpio_common_f24.h should not be included explicitly, only via gpio.h"
#endif #endif
/** @endcond */ /** @endcond */

60
include/libopencm3/stm32/f3/adc.h
View File

@ -416,7 +416,10 @@
/* OVRMOD: Overrun Mode */ /* OVRMOD: Overrun Mode */
#define ADC_CFGR_OVRMOD (1 << 12) #define ADC_CFGR_OVRMOD (1 << 12)
/* EXTEN[1:0]: External trigger enable and polarity selection for regular channels */ /*
* EXTEN[1:0]: External trigger enable and polarity selection for regular
* channels
*/
#define ADC_CFGR_EXTEN_DISABLED (0x0 << 10) #define ADC_CFGR_EXTEN_DISABLED (0x0 << 10)
#define ADC_CFGR_EXTEN_RISING_EDGE (0x1 << 10) #define ADC_CFGR_EXTEN_RISING_EDGE (0x1 << 10)
#define ADC_CFGR_EXTEN_FALLING_EDGE (0x2 << 10) #define ADC_CFGR_EXTEN_FALLING_EDGE (0x2 << 10)
@ -619,7 +622,10 @@
/* Bits 12:8 JSQ1[4:0]: 1st conversion in the injected sequence */ /* Bits 12:8 JSQ1[4:0]: 1st conversion in the injected sequence */
/* JEXTEN[1:0]: External Trigger Enable and Polarity Selection for injected channels */ /*
* JEXTEN[1:0]: External Trigger Enable and Polarity Selection for injected
* channels
*/
#define ADC_JSQR_JEXTEN_DISABLED (0x0 << 6) #define ADC_JSQR_JEXTEN_DISABLED (0x0 << 6)
#define ADC_JSQR_JEXTEN_RISING_EDGE (0x1 << 6) #define ADC_JSQR_JEXTEN_RISING_EDGE (0x1 << 6)
#define ADC_JSQR_JEXTEN_FALLING_EDGE (0x2 << 6) #define ADC_JSQR_JEXTEN_FALLING_EDGE (0x2 << 6)
@ -661,7 +667,10 @@
/* Bits 30:26 OFFSET1_CH[4:0]: Channel selection for the Data offset 1 */ /* Bits 30:26 OFFSET1_CH[4:0]: Channel selection for the Data offset 1 */
/* Bits 11:0 OFFSET1[11:0]: Data offset y for the channel programmed into bits OFFSET1_CH[4:0] */ /*
* Bits 11:0 OFFSET1[11:0]: Data offset y for the channel programmed into bits
* OFFSET1_CH[4:0]
*/
/*------- ADC_OFR2 values ---------*/ /*------- ADC_OFR2 values ---------*/
@ -671,7 +680,10 @@
/* Bits 30:26 OFFSET2_CH[4:0]: Channel selection for the Data offset 2 */ /* Bits 30:26 OFFSET2_CH[4:0]: Channel selection for the Data offset 2 */
/* Bits 11:0 OFFSET2[11:0]: Data offset y for the channel programmed into bits OFFSET2_CH[4:0] */ /*
* Bits 11:0 OFFSET2[11:0]: Data offset y for the channel programmed into bits
* OFFSET2_CH[4:0]
*/
/*------- ADC_OFR3 values ---------*/ /*------- ADC_OFR3 values ---------*/
@ -681,7 +693,10 @@
/* Bits 30:26 OFFSET3_CH[4:0]: Channel selection for the Data offset 3 */ /* Bits 30:26 OFFSET3_CH[4:0]: Channel selection for the Data offset 3 */
/* Bits 11:0 OFFSET3[11:0]: Data offset y for the channel programmed into bits OFFSET3_CH[4:0] */ /*
* Bits 11:0 OFFSET3[11:0]: Data offset y for the channel programmed into bits
* OFFSET3_CH[4:0]
*/
/*------- ADC_OFR4 values ---------*/ /*------- ADC_OFR4 values ---------*/
@ -691,7 +706,10 @@
/* Bits 30:26 OFFSET4_CH[4:0]: Channel selection for the Data offset 4 */ /* Bits 30:26 OFFSET4_CH[4:0]: Channel selection for the Data offset 4 */
/* Bits 11:0 OFFSET4[11:0]: Data offset y for the channel programmed into bits OFFSET4_CH[4:0] */ /*
* Bits 11:0 OFFSET4[11:0]: Data offset y for the channel programmed into bits
* OFFSET4_CH[4:0]
*/
/*------- ADC_JDRy, y= 1..4 values -------*/ /*------- ADC_JDRy, y= 1..4 values -------*/
@ -795,13 +813,13 @@
/*-------- ADC_CCR values ------------*/ /*-------- ADC_CCR values ------------*/
/* VBATEN: VBAT enable */ /* VBATEN: VBAT enable */
#define ADC_CCR_VBATEN (1 << 24) #define ADC_CCR_VBATEN (1 << 24)
/* TSEN: Temperature sensor enable */ /* TSEN: Temperature sensor enable */
#define ADC_CCR_TSEN (1 << 23) #define ADC_CCR_TSEN (1 << 23)
/* VREFEN: VREFINT enable */ /* VREFEN: VREFINT enable */
#define ADC_CCR_VREFEN (1 << 22) #define ADC_CCR_VREFEN (1 << 22)
/* CKMODE[1:0]: ADC clock mode */ /* CKMODE[1:0]: ADC clock mode */
#define ADC_CCR_CKMODE_CKX (0x0 << 16) #define ADC_CCR_CKMODE_CKX (0x0 << 16)
@ -813,7 +831,7 @@
/* MDMA[1:0]: Direct memory access mode for dual ADC mode */ /* MDMA[1:0]: Direct memory access mode for dual ADC mode */
#define ADC_CCR_MDMA_DISABLE (0x0 << 14) #define ADC_CCR_MDMA_DISABLE (0x0 << 14)
//#define ADC_CCR_MDMA_RESERVED (0x1 << 14) /*#define ADC_CCR_MDMA_RESERVED (0x1 << 14)*/
#define ADC_CCR_MDMA_12_10_BIT (0x2 << 14) #define ADC_CCR_MDMA_12_10_BIT (0x2 << 14)
#define ADC_CCR_MDMA_8_6_BIT (0x3 << 14) #define ADC_CCR_MDMA_8_6_BIT (0x3 << 14)
@ -850,9 +868,10 @@ void adc_disable_discontinuous_mode_injected(uint32_t adc);
void adc_enable_automatic_injected_group_conversion(uint32_t adc); void adc_enable_automatic_injected_group_conversion(uint32_t adc);
void adc_disable_automatic_injected_group_conversion(uint32_t adc); void adc_disable_automatic_injected_group_conversion(uint32_t adc);
void adc_enable_analog_watchdog_on_all_channels(uint32_t adc); void adc_enable_analog_watchdog_on_all_channels(uint32_t adc);
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t channel); void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc,
//void adc_enable_scan_mode(uint32_t adc); uint8_t channel);
//void adc_disable_scan_mode(uint32_t adc); /*void adc_enable_scan_mode(uint32_t adc);*/
/*void adc_disable_scan_mode(uint32_t adc);*/
void adc_enable_eoc_interrupt_injected(uint32_t adc); void adc_enable_eoc_interrupt_injected(uint32_t adc);
void adc_disable_eoc_interrupt_injected(uint32_t adc); void adc_disable_eoc_interrupt_injected(uint32_t adc);
void adc_enable_all_awd_interrupt(uint32_t adc); void adc_enable_all_awd_interrupt(uint32_t adc);
@ -883,8 +902,10 @@ void adc_set_injected_offset(uint32_t adc, uint8_t reg, uint32_t offset);
void adc_set_clk_prescale(uint32_t prescaler); void adc_set_clk_prescale(uint32_t prescaler);
void adc_set_multi_mode(uint32_t mode); void adc_set_multi_mode(uint32_t mode);
void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger, uint32_t polarity); void adc_enable_external_trigger_regular(uint32_t adc, uint32_t trigger,
void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger, uint32_t polarity); uint32_t polarity);
void adc_enable_external_trigger_injected(uint32_t adc, uint32_t trigger,
uint32_t polarity);
void adc_set_resolution(uint32_t adc, uint16_t resolution); void adc_set_resolution(uint32_t adc, uint16_t resolution);
void adc_enable_overrun_interrupt(uint32_t adc); void adc_enable_overrun_interrupt(uint32_t adc);
void adc_disable_overrun_interrupt(uint32_t adc); void adc_disable_overrun_interrupt(uint32_t adc);
@ -893,15 +914,12 @@ void adc_clear_overrun_flag(uint32_t adc);
bool adc_awd(uint32_t adc); bool adc_awd(uint32_t adc);
void adc_eoc_after_each(uint32_t adc); void adc_eoc_after_each(uint32_t adc);
void adc_eoc_after_group(uint32_t adc); void adc_eoc_after_group(uint32_t adc);
//void adc_set_dma_continue(uint32_t adc); /*void adc_set_dma_continue(uint32_t adc);*/
//void adc_set_dma_terminate(uint32_t adc); /*void adc_set_dma_terminate(uint32_t adc);*/
void adc_enable_temperature_sensor(void); void adc_enable_temperature_sensor(void);
void adc_disable_temperature_sensor(void); void adc_disable_temperature_sensor(void);
END_DECLS END_DECLS
#endif #endif

6
include/libopencm3/stm32/f3/crc.h
View File

@ -36,7 +36,7 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/stm32/memorymap.h> #include <libopencm3/stm32/memorymap.h>
#include <libopencm3/stm32/common/crc_common_all.h> #include <libopencm3/stm32/common/crc_common_all.h>
/* --- CRC registers ------------------------------------------------------- */ /* --- CRC registers ------------------------------------------------------- */
/* Initial CRC value (CRC_INIT) */ /* Initial CRC value (CRC_INIT) */
#define CRC_INIT MMIO32(CRC_BASE + 0x10) #define CRC_INIT MMIO32(CRC_BASE + 0x10)
@ -61,11 +61,11 @@ LGPL License Terms @ref lgpl_license
#define CRC_CR_POLYSIZE_8 (0x2 << 3) #define CRC_CR_POLYSIZE_8 (0x2 << 3)
#define CRC_CR_POLYSIZE_7 (0x3 << 3) #define CRC_CR_POLYSIZE_7 (0x3 << 3)
/* --- CRC_INIT values ------------------------------------------------------- */ /* --- CRC_INIT values ----------------------------------------------------- */
/* Bits 31:0 CRC_INIT: Programmable initial CRC value */ /* Bits 31:0 CRC_INIT: Programmable initial CRC value */
/* --- CRC_POL values ------------------------------------------------------- */ /* --- CRC_POL values ------------------------------------------------------ */
/* Bits 31:0 POL[31:0]: Programmable polynomial */ /* Bits 31:0 POL[31:0]: Programmable polynomial */

25
include/libopencm3/stm32/f3/i2c.h
View File

@ -39,7 +39,7 @@ LGPL License Terms @ref lgpl_license
/* --- Convenience macros -------------------------------------------------- */ /* --- Convenience macros -------------------------------------------------- */
/* I2C register base addresses (for convenience) */ /* I2C register base addresses (for convenience) */
/****************************************************************************/ /*****************************************************************************/
/** @defgroup i2c_reg_base I2C register base address /** @defgroup i2c_reg_base I2C register base address
@ingroup i2c_defines @ingroup i2c_defines
@ -225,7 +225,7 @@ LGPL License Terms @ref lgpl_license
/* OA1EN: Own Address 1 enable */ /* OA1EN: Own Address 1 enable */
#define I2C_OAR1_OA1EN_DISABLE (0x0 << 15) #define I2C_OAR1_OA1EN_DISABLE (0x0 << 15)
#define I2C_OAR1_OA1EN_ENABLE (0x1 <<15) #define I2C_OAR1_OA1EN_ENABLE (0x1 << 15)
/* OA1MODE Own Address 1 10-bit mode */ /* OA1MODE Own Address 1 10-bit mode */
#define I2C_OAR1_OA1MODE (1 << 10) #define I2C_OAR1_OA1MODE (1 << 10)
@ -258,7 +258,7 @@ LGPL License Terms @ref lgpl_license
/* OA2[7:1]: Interface address */ /* OA2[7:1]: Interface address */
/* --- I2Cx_TIMINGR values ---------------------------------------------------- */ /* --- I2Cx_TIMINGR values ------------------------------------------------- */
/* PRESC[3:0]: Timing prescaler (31,28) */ /* PRESC[3:0]: Timing prescaler (31,28) */
#define I2C_TIMINGR_PRESC_SHIFT 28 #define I2C_TIMINGR_PRESC_SHIFT 28
@ -280,12 +280,12 @@ LGPL License Terms @ref lgpl_license
#define I2C_TIMINGR_SCLL_SHIFT 0 #define I2C_TIMINGR_SCLL_SHIFT 0
#define I2C_TIMINGR_SCLL_MASK (0xFF << I2C_TIMINGR_SCLL_SHIFT) #define I2C_TIMINGR_SCLL_MASK (0xFF << I2C_TIMINGR_SCLL_SHIFT)
/* --- I2Cx_TIEMOUTR values ---------------------------------------------------- */ /* --- I2Cx_TIEMOUTR values ------------------------------------------------ */
/* TEXTEN: Extended clock timeout enable */ /* TEXTEN: Extended clock timeout enable */
#define I2C_TIEMOUTR_TEXTEN (1 << 31) #define I2C_TIEMOUTR_TEXTEN (1 << 31)
//Not clear yet. /* XXX: Not clear yet. */
/* TIMEOUTB[11:0]: Bus timeout B */ /* TIMEOUTB[11:0]: Bus timeout B */
/* TIMOUTEN: Clock timeout enable */ /* TIMOUTEN: Clock timeout enable */
@ -295,14 +295,14 @@ LGPL License Terms @ref lgpl_license
#define I2C_TIEMOUTR_TIDLE_SCL_LOW (0x0 << 12) #define I2C_TIEMOUTR_TIDLE_SCL_LOW (0x0 << 12)
#define I2C_TIEMOUTR_TIDLE_SCL_SDA_HIGH (0x1 << 12) #define I2C_TIEMOUTR_TIDLE_SCL_SDA_HIGH (0x1 << 12)
//Not clear yet. /* XXX: Not clear yet. */
/* TIMEOUTA[11:0]: Bus Timeout A */ /* TIMEOUTA[11:0]: Bus Timeout A */
/* --- I2Cx_ISR values ---------------------------------------------------- */ /* --- I2Cx_ISR values ----------------------------------------------------- */
/* Bits 31:24 Reserved, must be kept at reset value */ /* Bits 31:24 Reserved, must be kept at reset value */
//Not clear yet. /* XXX: Not clear yet. */
/* ADDCODE[6:0]: Address match code (Slave mode) */ /* ADDCODE[6:0]: Address match code (Slave mode) */
/* DIR: Transfer direction (Slave mode) */ /* DIR: Transfer direction (Slave mode) */
@ -354,7 +354,7 @@ LGPL License Terms @ref lgpl_license
/* TXE: Transmit data register empty (transmitters) */ /* TXE: Transmit data register empty (transmitters) */
#define I2C_ISR_TXE (1 << 0) #define I2C_ISR_TXE (1 << 0)
/* --- I2Cx_ICR values ---------------------------------------------------- */ /* --- I2Cx_ICR values ----------------------------------------------------- */
/* ALERTCF: Alert flag clear */ /* ALERTCF: Alert flag clear */
#define I2C_ICR_ALERTCF (1 << 13) #define I2C_ICR_ALERTCF (1 << 13)
@ -435,12 +435,13 @@ void i2c_enable_rxdma(uint32_t i2c);
void i2c_disable_rxdma(uint32_t i2c); void i2c_disable_rxdma(uint32_t i2c);
void i2c_enable_txdma(uint32_t i2c); void i2c_enable_txdma(uint32_t i2c);
void i2c_disable_txdma(uint32_t i2c); void i2c_disable_txdma(uint32_t i2c);
void write_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, uint8_t size, uint8_t *data); void write_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg,
void read_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, uint8_t size, uint8_t *data); uint8_t size, uint8_t *data);
void read_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg,
uint8_t size, uint8_t *data);
END_DECLS END_DECLS
/**@}*/ /**@}*/
#endif #endif

142
include/libopencm3/stm32/f3/rcc.h
View File

@ -67,7 +67,7 @@
/* MCO: Microcontroller clock output */ /* MCO: Microcontroller clock output */
#define RCC_CFGR_MCO_SHIFT 24 #define RCC_CFGR_MCO_SHIFT 24
#define RCC_CFGR_MCO_DISABLED 0x0 #define RCC_CFGR_MCO_DISABLED 0x0
//Reserve RCC_CFGR_MCO 0x1 /*Reserve RCC_CFGR_MCO 0x1*/
#define RCC_CFGR_MCO_LSI 0x2 #define RCC_CFGR_MCO_LSI 0x2
#define RCC_CFGR_MCO_LSE 0x3 #define RCC_CFGR_MCO_LSE 0x3
#define RCC_CFGR_MCO_SYSCLK 0x4 #define RCC_CFGR_MCO_SYSCLK 0x4
@ -100,47 +100,47 @@
/* PPRE2: APB high-speed prescaler (APB2) */ /* PPRE2: APB high-speed prescaler (APB2) */
#define RCC_CFGR_PPRE2_SHIFT 11 #define RCC_CFGR_PPRE2_SHIFT 11
// 0XX: HCLK not divided /* 0XX: HCLK not divided */
#define RCC_CFGR_PPRE2_DIV_NONE 0x0 #define RCC_CFGR_PPRE2_DIV_NONE 0x0
#define RCC_CFGR_PPRE2_DIV_2 0x4 #define RCC_CFGR_PPRE2_DIV_2 0x4
#define RCC_CFGR_PPRE2_DIV_4 0x5 #define RCC_CFGR_PPRE2_DIV_4 0x5
#define RCC_CFGR_PPRE2_DIV_8 0x6 #define RCC_CFGR_PPRE2_DIV_8 0x6
#define RCC_CFGR_PPRE2_DIV_16 0x7 #define RCC_CFGR_PPRE2_DIV_16 0x7
/* PPRE1:APB Low-speed prescaler (APB1) */ /* PPRE1:APB Low-speed prescaler (APB1) */
#define RCC_CFGR_PPRE1_SHIFT 8 #define RCC_CFGR_PPRE1_SHIFT 8
// 0XX: HCLK not divided /* 0XX: HCLK not divided */
#define RCC_CFGR_PPRE1_DIV_NONE 0x0 #define RCC_CFGR_PPRE1_DIV_NONE 0x0
#define RCC_CFGR_PPRE1_DIV_2 0x4 #define RCC_CFGR_PPRE1_DIV_2 0x4
#define RCC_CFGR_PPRE1_DIV_4 0x5 #define RCC_CFGR_PPRE1_DIV_4 0x5
#define RCC_CFGR_PPRE1_DIV_8 0x6 #define RCC_CFGR_PPRE1_DIV_8 0x6
#define RCC_CFGR_PPRE1_DIV_16 0x7 #define RCC_CFGR_PPRE1_DIV_16 0x7
/* HPRE: HLCK prescaler */ /* HPRE: HLCK prescaler */
#define RCC_CFGR_HPRE_SHIFT 4 #define RCC_CFGR_HPRE_SHIFT 4
// 0XXX: SYSCLK not divided /* 0XXX: SYSCLK not divided */
#define RCC_CFGR_HPRE_DIV_NONE 0x0 #define RCC_CFGR_HPRE_DIV_NONE 0x0
#define RCC_CFGR_HPRE_DIV_2 0x8 #define RCC_CFGR_HPRE_DIV_2 0x8
#define RCC_CFGR_HPRE_DIV_4 0x9 #define RCC_CFGR_HPRE_DIV_4 0x9
#define RCC_CFGR_HPRE_DIV_8 0xA #define RCC_CFGR_HPRE_DIV_8 0xA
#define RCC_CFGR_HPRE_DIV_16 0xB #define RCC_CFGR_HPRE_DIV_16 0xB
#define RCC_CFGR_HPRE_DIV_64 0xC #define RCC_CFGR_HPRE_DIV_64 0xC
#define RCC_CFGR_HPRE_DIV_128 0xD #define RCC_CFGR_HPRE_DIV_128 0xD
#define RCC_CFGR_HPRE_DIV_256 0xE #define RCC_CFGR_HPRE_DIV_256 0xE
#define RCC_CFGR_HPRE_DIV_512 0xF #define RCC_CFGR_HPRE_DIV_512 0xF
/* SWS: System clock switch status */ /* SWS: System clock switch status */
#define RCC_CFGR_SWS_SHIFT 2 #define RCC_CFGR_SWS_SHIFT 2
#define RCC_CFGR_SWS_HSI 0x0 #define RCC_CFGR_SWS_HSI 0x0
#define RCC_CFGR_SWS_HSE 0x1 #define RCC_CFGR_SWS_HSE 0x1
#define RCC_CFGR_SWS_PLL 0x2 #define RCC_CFGR_SWS_PLL 0x2
/* SW: System clock switch */ /* SW: System clock switch */
#define RCC_CFGR_SW_SHIFT 0 #define RCC_CFGR_SW_SHIFT 0
#define RCC_CFGR_SW_HSI 0x0 #define RCC_CFGR_SW_HSI 0x0
#define RCC_CFGR_SW_HSE 0x1 #define RCC_CFGR_SW_HSE 0x1
#define RCC_CFGR_SW_PLL 0x2 #define RCC_CFGR_SW_PLL 0x2
/* --- RCC_CIR values ------------------------------------------------------ */ /* --- RCC_CIR values ------------------------------------------------------ */
@ -203,7 +203,7 @@
#define RCC_APB1RSTR_TIM3RST (1 << 1) #define RCC_APB1RSTR_TIM3RST (1 << 1)
#define RCC_APB1RSTR_TIM2RST (1 << 0) #define RCC_APB1RSTR_TIM2RST (1 << 0)
/* --- RCC_AHBENR values ------------------------------------------------- */ /* --- RCC_AHBENR values --------------------------------------------------- */
#define RCC_AHBENR_ADC34EN (1 << 29) #define RCC_AHBENR_ADC34EN (1 << 29)
#define RCC_AHBENR_ADC12EN (1 << 28) #define RCC_AHBENR_ADC12EN (1 << 28)
#define RCC_AHBENR_TSCEN (1 << 24) #define RCC_AHBENR_TSCEN (1 << 24)
@ -215,7 +215,7 @@
#define RCC_AHBENR_IOPAEN (1 << 17) #define RCC_AHBENR_IOPAEN (1 << 17)
#define RCC_AHBENR_CRCEN (1 << 1) #define RCC_AHBENR_CRCEN (1 << 1)
/* --- RCC_APB2ENR values ------------------------------------------------- */ /* --- RCC_APB2ENR values -------------------------------------------------- */
#define RCC_APB2ENR_TIM17EN (1 << 18) #define RCC_APB2ENR_TIM17EN (1 << 18)
#define RCC_APB2ENR_TIM16EN (1 << 17) #define RCC_APB2ENR_TIM16EN (1 << 17)
@ -226,7 +226,7 @@
#define RCC_APB2ENR_TIM1EN (1 << 11) #define RCC_APB2ENR_TIM1EN (1 << 11)
#define RCC_APB2ENR_SYSCFGEN (1 << 0) #define RCC_APB2ENR_SYSCFGEN (1 << 0)
/* --- RCC_APB1ENR values ------------------------------------------------- */ /* --- RCC_APB1ENR values -------------------------------------------------- */
#define RCC_APB1ENR_DACEN (1 << 29) #define RCC_APB1ENR_DACEN (1 << 29)
#define RCC_APB1ENR_PWREN (1 << 28) #define RCC_APB1ENR_PWREN (1 << 28)
@ -267,7 +267,7 @@
#define RCC_CSR_LSIRDY (1 << 1) #define RCC_CSR_LSIRDY (1 << 1)
#define RCC_CSR_LSION (1 << 0) #define RCC_CSR_LSION (1 << 0)
/* --- RCC_AHBRSTR values ------------------------------------------------------ */ /* --- RCC_AHBRSTR values -------------------------------------------------- */
#define RCC_AHBRSTR_ADC34RST (1 << 29) #define RCC_AHBRSTR_ADC34RST (1 << 29)
#define RCC_AHBRSTR_ADC12RST (1 << 28) #define RCC_AHBRSTR_ADC12RST (1 << 28)
#define RCC_AHBRSTR_TSCRST (1 << 24) #define RCC_AHBRSTR_TSCRST (1 << 24)
@ -278,7 +278,7 @@
#define RCC_AHBRSTR_IOPBRST (1 << 18) #define RCC_AHBRSTR_IOPBRST (1 << 18)
#define RCC_AHBRSTR_IOPARST (1 << 17) #define RCC_AHBRSTR_IOPARST (1 << 17)
/* --- RCC_CFGR2 values ------------------------------------------------------ */ /* --- RCC_CFGR2 values ---------------------------------------------------- */
/* ADC34PRES: ADC34 prescaler */ /* ADC34PRES: ADC34 prescaler */
#define RCC_CFGR2_ADC34PRES_SHIFT 9 #define RCC_CFGR2_ADC34PRES_SHIFT 9
#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_1 0x10 #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_1 0x10
@ -293,11 +293,11 @@
#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_64 0x19 #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_64 0x19
#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_128 0x1A #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_128 0x1A
#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_256 0x1B #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV_256 0x1B
//OTHERS /* OTHERS */
//#define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV256 0x /* #define RCC_CFGR2_ADC34PRES_PLL_CLK_DIV256 0x */
/* ADC12PRES ADC prescaler */ /* ADC12PRES ADC prescaler */
//REVISAR DIRECCIONES /* REVISAR DIRECCIONES */
#define RCC_CFGR2_ADC12PRES_SHIFT 4 #define RCC_CFGR2_ADC12PRES_SHIFT 4
#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_1 0x10 #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_1 0x10
#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_2 0x11 #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_2 0x11
@ -311,11 +311,11 @@
#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_64 0x19 #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_64 0x19
#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_128 0x1A #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_128 0x1A
#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_256 0x1B #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV_256 0x1B
//OTHERS /* OTHERS */
//#define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV256 0x /* #define RCC_CFGR2_ADC12PRES_PLL_CLK_DIV256 0x */
/* PREDIV[3:0] PREDIV division factor */ /* PREDIV[3:0] PREDIV division factor */
//REVISAR DIRECCIONES /* REVISAR DIRECCIONES */
#define RCC_CFGR2_PREDIV_SHIFT 0 #define RCC_CFGR2_PREDIV_SHIFT 0
#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_NONE 0x0 #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_NONE 0x0
#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_2 0x1 #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_2 0x1
@ -334,7 +334,7 @@
#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_15 0xE #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_15 0xE
#define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_16 0xF #define RCC_CFGR2_PREDIV_HSE_IN_PLL_DIV_16 0xF
/* --- RCC_CFGR3 values ------------------------------------------------------ */ /* --- RCC_CFGR3 values ---------------------------------------------------- */
#define RCC_CFGR3_TIM8SW (1 << 9) #define RCC_CFGR3_TIM8SW (1 << 9)
#define RCC_CFGR3_TIM1SW (1 << 8) #define RCC_CFGR3_TIM1SW (1 << 8)
#define RCC_CFGR3_I2C2SW (1 << 5) #define RCC_CFGR3_I2C2SW (1 << 5)
@ -377,48 +377,48 @@ extern uint32_t rcc_ppre2_frequency;
/* --- Function prototypes ------------------------------------------------- */ /* --- Function prototypes ------------------------------------------------- */
typedef enum { enum rcc_clock {
CLOCK_44MHZ, CLOCK_44MHZ,
CLOCK_48MHZ, CLOCK_48MHZ,
CLOCK_64MHZ, CLOCK_64MHZ,
CLOCK_END CLOCK_END
} rcc_clock_t; };
typedef struct { typedef struct {
uint8_t pll; uint8_t pll;
uint8_t pllsrc; uint8_t pllsrc;
uint32_t flash_config; uint32_t flash_config;
uint8_t hpre; uint8_t hpre;
uint8_t ppre1; uint8_t ppre1;
uint8_t ppre2; uint8_t ppre2;
uint8_t power_save; uint8_t power_save;
uint32_t apb1_frequency; uint32_t apb1_frequency;
uint32_t apb2_frequency; uint32_t apb2_frequency;
} clock_scale_t; } clock_scale_t;
extern const clock_scale_t hsi_8mhz[CLOCK_END]; extern const clock_scale_t hsi_8mhz[CLOCK_END];
typedef enum { enum osc {
PLL, HSE, HSI, LSE, LSI PLL, HSE, HSI, LSE, LSI
} osc_t; } osc_t;
BEGIN_DECLS BEGIN_DECLS
void rcc_osc_ready_int_clear(osc_t osc); void rcc_osc_ready_int_clear(enum osc osc);
void rcc_osc_ready_int_enable(osc_t osc); void rcc_osc_ready_int_enable(enum osc osc);
void rcc_osc_ready_int_disable(osc_t osc); void rcc_osc_ready_int_disable(enum osc osc);
int rcc_osc_ready_int_flag(osc_t osc); int rcc_osc_ready_int_flag(enum osc osc);
void rcc_css_int_clear(void); void rcc_css_int_clear(void);
int rcc_css_int_flag(void); int rcc_css_int_flag(void);
void rcc_wait_for_osc_ready(osc_t osc); void rcc_wait_for_osc_ready(enum osc osc);
void rcc_wait_for_osc_not_ready(osc_t osc); void rcc_wait_for_osc_not_ready(enum osc osc);
void rcc_wait_for_sysclk_status(osc_t osc); void rcc_wait_for_sysclk_status(enum osc osc);
void rcc_osc_on(osc_t osc); void rcc_osc_on(enum osc osc);
void rcc_osc_off(osc_t osc); void rcc_osc_off(enum osc osc);
void rcc_css_enable(void); void rcc_css_enable(void);
void rcc_css_disable(void); void rcc_css_disable(void);
void rcc_osc_bypass_enable(osc_t osc); void rcc_osc_bypass_enable(enum osc osc);
void rcc_osc_bypass_disable(osc_t osc); void rcc_osc_bypass_disable(enum osc osc);
void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en); void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en);
void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en); void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en);
void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset); void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset);

4
include/libopencm3/stm32/f3/spi.h
View File

@ -63,7 +63,7 @@ LGPL License Terms @ref lgpl_license
#define SPI_CR2_FRXTH (1 << 12) #define SPI_CR2_FRXTH (1 << 12)
/* DS [3:0]: Data size */ /* DS [3:0]: Data size */
// 0x0 - 0x2 NOT USED /* 0x0 - 0x2 NOT USED */
#define SPI_CR2_DS_4BIT (0x3 << 8) #define SPI_CR2_DS_4BIT (0x3 << 8)
#define SPI_CR2_DS_5BIT (0x4 << 8) #define SPI_CR2_DS_5BIT (0x4 << 8)
#define SPI_CR2_DS_6BIT (0x5 << 8) #define SPI_CR2_DS_6BIT (0x5 << 8)
@ -109,4 +109,4 @@ uint8_t spi_read8(uint32_t spi);
END_DECLS END_DECLS
#endif #endif

8
include/libopencm3/stm32/f3/usart.h
View File

@ -253,7 +253,7 @@ LGPL License Terms @ref lgpl_license
/* ADDM7:7-bit Address Detection/4-bit Address Detection */ /* ADDM7:7-bit Address Detection/4-bit Address Detection */
#define USART_CR2_ADDM7 (1 << 4) #define USART_CR2_ADDM7 (1 << 4)
/* ADD[3:0]: Addres of the usart node /* ADD[3:0]: Addres of the usart node
#define USART_CR2_ADD_MASK 0xF */ #define USART_CR2_ADD_MASK 0xF */
/* --- USART_CR3 values ---------------------------------------------------- */ /* --- USART_CR3 values ---------------------------------------------------- */
@ -263,13 +263,13 @@ LGPL License Terms @ref lgpl_license
/* WUS[1:0]: Wakeup from Stop mode interrupt flag selectio */ /* WUS[1:0]: Wakeup from Stop mode interrupt flag selectio */
#define USART_CR3_WUS_ON (0x0 << 20) #define USART_CR3_WUS_ON (0x0 << 20)
// RESERVE #define USART_CR3_WUS (0x1 << 20) /* RESERVE #define USART_CR3_WUS (0x1 << 20) */
#define USART_CR3_WUS_START_BIT (0x2 << 20) #define USART_CR3_WUS_START_BIT (0x2 << 20)
#define USART_CR3_WUS_RXNE (0x3 << 20) #define USART_CR3_WUS_RXNE (0x3 << 20)
/* SCARCNT[2:0]: Smartcard auto-retry count */ /* SCARCNT[2:0]: Smartcard auto-retry count */
#define USART_CR3_SCARCNT_OFF (0x0 << 17) #define USART_CR3_SCARCNT_OFF (0x0 << 17)
// 0x1 to 0x7: number of automatic retransmission attempts /* 0x1 to 0x7: number of automatic retransmission attempts */
/* DEP: Driver enable polarity selection */ /* DEP: Driver enable polarity selection */
#define USART_CR3_DEP (1 << 15) #define USART_CR3_DEP (1 << 15)
@ -345,7 +345,7 @@ LGPL License Terms @ref lgpl_license
/* --- USART_RTOR values --------------------------------------------------- */ /* --- USART_RTOR values --------------------------------------------------- */
//Preguntar /* XXX: Preguntar */
/* BLEN[7:0]: Block Length */ /* BLEN[7:0]: Block Length */
#define USART_RTOR_BLEN1_MASK (0xFF << 24) #define USART_RTOR_BLEN1_MASK (0xFF << 24)

1
lib/sam/common/usart.c
View File

@ -106,4 +106,3 @@ void usart_disable_rx_interrupt(uint32_t usart)
{ {
USART_IDR(usart) = USART_CSR_RXRDY; USART_IDR(usart) = USART_CSR_RXRDY;
} }

1
lib/stm32/f1/spi.c
View File

@ -30,4 +30,3 @@ LGPL License Terms @ref lgpl_license
#include <libopencm3/stm32/spi.h> #include <libopencm3/stm32/spi.h>
#include <libopencm3/stm32/common/spi_common_all.h> #include <libopencm3/stm32/common/spi_common_all.h>

545
lib/stm32/f3/adc.c
View File

File diff suppressed because it is too large Load Diff

30
lib/stm32/f3/gpio.c
View File

@ -21,7 +21,8 @@
#include <libopencm3/stm32/f3/gpio.h> #include <libopencm3/stm32/f3/gpio.h>
void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, uint16_t gpios) void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down,
uint16_t gpios)
{ {
uint16_t i; uint16_t i;
uint32_t moder, pupd; uint32_t moder, pupd;
@ -34,8 +35,9 @@ void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, uint
pupd = GPIO_PUPDR(gpioport); pupd = GPIO_PUPDR(gpioport);
for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) {
if (!((1 << i) & gpios)) if (!((1 << i) & gpios)) {
continue; continue;
}
moder &= ~GPIO_MODE_MASK(i); moder &= ~GPIO_MODE_MASK(i);
moder |= GPIO_MODE(i, mode); moder |= GPIO_MODE(i, mode);
@ -48,21 +50,24 @@ void gpio_mode_setup(uint32_t gpioport, uint8_t mode, uint8_t pull_up_down, uint
GPIO_PUPDR(gpioport) = pupd; GPIO_PUPDR(gpioport) = pupd;
} }
void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed, uint16_t gpios) void gpio_set_output_options(uint32_t gpioport, uint8_t otype, uint8_t speed,
uint16_t gpios)
{ {
uint16_t i; uint16_t i;
uint32_t ospeedr; uint32_t ospeedr;
if (otype == 0x1) if (otype == 0x1) {
GPIO_OTYPER(gpioport) |= gpios; GPIO_OTYPER(gpioport) |= gpios;
else } else {
GPIO_OTYPER(gpioport) &= ~gpios; GPIO_OTYPER(gpioport) &= ~gpios;
}
ospeedr = GPIO_OSPEEDR(gpioport); ospeedr = GPIO_OSPEEDR(gpioport);
for (i = 0; i < 16; i++) { for (i = 0; i < 16; i++) {
if (!((1 << i) & gpios)) if (!((1 << i) & gpios)) {
continue; continue;
}
ospeedr &= ~GPIO_OSPEED_MASK(i); ospeedr &= ~GPIO_OSPEED_MASK(i);
ospeedr |= GPIO_OSPEED(i, speed); ospeedr |= GPIO_OSPEED(i, speed);
} }
@ -79,15 +84,17 @@ void gpio_set_af(uint32_t gpioport, uint8_t alt_func_num, uint16_t gpios)
afrh = GPIO_AFRH(gpioport); afrh = GPIO_AFRH(gpioport);
for (i = 0; i < 8; i++) { for (i = 0; i < 8; i++) {
if (!((1 << i) & gpios)) if (!((1 << i) & gpios)) {
continue; continue;
}
afrl &= ~GPIO_AFR_MASK(i); afrl &= ~GPIO_AFR_MASK(i);
afrl |= GPIO_AFR(i, alt_func_num); afrl |= GPIO_AFR(i, alt_func_num);
} }
for (i = 8; i < 16; i++) { for (i = 8; i < 16; i++) {
if (!((1 << i) & gpios)) if (!((1 << i) & gpios)) {
continue; continue;
}
afrl &= ~GPIO_AFR_MASK(i - 8); afrl &= ~GPIO_AFR_MASK(i - 8);
afrh |= GPIO_AFR(i - 8, alt_func_num); afrh |= GPIO_AFR(i - 8, alt_func_num);
} }
@ -137,8 +144,11 @@ void gpio_port_config_lock(uint32_t gpioport, uint16_t gpios)
reg32 = GPIO_LCKR(gpioport); /* Read LCKK. */ reg32 = GPIO_LCKR(gpioport); /* Read LCKK. */
reg32 = GPIO_LCKR(gpioport); /* Read LCKK again. */ reg32 = GPIO_LCKR(gpioport); /* Read LCKK again. */
/* Tell the compiler the variable is actually used. It will get optimized out anyways. */ /*
reg32 = reg32; * Tell the compiler the variable is actually used.
* It will get optimized out anyways.
*/
reg32 = reg32;
/* If (reg32 & GPIO_LCKK) is true, the lock is now active. */ /* If (reg32 & GPIO_LCKK) is true, the lock is now active. */
} }

257
lib/stm32/f3/i2c.c
View File

@ -107,7 +107,7 @@ mode, or simply release the bus if in Slave mode.
void i2c_send_stop(uint32_t i2c) void i2c_send_stop(uint32_t i2c)
{ {
I2C_CR2(i2c) |= I2C_CR2_STOP; I2C_CR2(i2c) |= I2C_CR2_STOP;
} }
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
@ -173,166 +173,174 @@ void i2c_send_data(uint32_t i2c, uint8_t data)
*/ */
uint8_t i2c_get_data(uint32_t i2c) uint8_t i2c_get_data(uint32_t i2c)
{ {
return(I2C_RXDR(i2c) & 0xff); return I2C_RXDR(i2c) & 0xff;
} }
void i2c_enable_analog_filter(uint32_t i2c) void i2c_enable_analog_filter(uint32_t i2c)
{ {
I2C_CR1(i2c) &= ~I2C_CR1_ANFOFF; I2C_CR1(i2c) &= ~I2C_CR1_ANFOFF;
} }
void i2c_disable_analog_filter(uint32_t i2c) void i2c_disable_analog_filter(uint32_t i2c)
{ {
I2C_CR1(i2c) |= I2C_CR1_ANFOFF; I2C_CR1(i2c) |= I2C_CR1_ANFOFF;
} }
void i2c_set_digital_filter(uint32_t i2c, uint8_t dnf_setting) void i2c_set_digital_filter(uint32_t i2c, uint8_t dnf_setting)
{ {
I2C_CR1(i2c) = (I2C_CR1(i2c) & ~I2C_CR1_DNF_MASK) | dnf_setting; I2C_CR1(i2c) = (I2C_CR1(i2c) & ~I2C_CR1_DNF_MASK) | dnf_setting;
} }
/* t_presc= (presc+1)*t_i2cclk */ /* t_presc= (presc+1)*t_i2cclk */
void i2c_set_prescaler(uint32_t i2c, uint8_t presc) void i2c_set_prescaler(uint32_t i2c, uint8_t presc)
{ {
I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_PRESC_MASK) | (presc << I2C_TIMINGR_PRESC_SHIFT); I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_PRESC_MASK) |
(presc << I2C_TIMINGR_PRESC_SHIFT);
} }
void i2c_set_data_setup_time(uint32_t i2c, uint8_t s_time) void i2c_set_data_setup_time(uint32_t i2c, uint8_t s_time)
{ {
I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLDEL_MASK) | (s_time << I2C_TIMINGR_SCLDEL_SHIFT); I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLDEL_MASK) |
(s_time << I2C_TIMINGR_SCLDEL_SHIFT);
} }
void i2c_set_data_hold_time(uint32_t i2c, uint8_t h_time) void i2c_set_data_hold_time(uint32_t i2c, uint8_t h_time)
{ {
I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SDADEL_MASK) | (h_time << I2C_TIMINGR_SDADEL_SHIFT); I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SDADEL_MASK) |
(h_time << I2C_TIMINGR_SDADEL_SHIFT);
} }
void i2c_set_scl_high_period(uint32_t i2c, uint8_t period) void i2c_set_scl_high_period(uint32_t i2c, uint8_t period)
{ {
I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLH_MASK) | (period << I2C_TIMINGR_SCLH_SHIFT); I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLH_MASK) |
(period << I2C_TIMINGR_SCLH_SHIFT);
} }
void i2c_set_scl_low_period(uint32_t i2c, uint8_t period) void i2c_set_scl_low_period(uint32_t i2c, uint8_t period)
{ {
I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLL_MASK) | (period << I2C_TIMINGR_SCLL_SHIFT); I2C_TIMINGR(i2c) = (I2C_TIMINGR(i2c) & ~I2C_TIMINGR_SCLL_MASK) |
(period << I2C_TIMINGR_SCLL_SHIFT);
} }
void i2c_enable_stretching(uint32_t i2c) void i2c_enable_stretching(uint32_t i2c)
{ {
I2C_CR1(i2c) &= ~I2C_CR1_NOSTRETCH; I2C_CR1(i2c) &= ~I2C_CR1_NOSTRETCH;
} }
void i2c_disable_stretching(uint32_t i2c) void i2c_disable_stretching(uint32_t i2c)
{ {
I2C_CR1(i2c) |= I2C_CR1_NOSTRETCH; I2C_CR1(i2c) |= I2C_CR1_NOSTRETCH;
} }
void i2c_100khz_i2cclk8mhz(uint32_t i2c) void i2c_100khz_i2cclk8mhz(uint32_t i2c)
{ {
i2c_set_prescaler(i2c, 1); i2c_set_prescaler(i2c, 1);
i2c_set_scl_low_period(i2c, 0x13); i2c_set_scl_low_period(i2c, 0x13);
i2c_set_scl_high_period(i2c, 0xF); i2c_set_scl_high_period(i2c, 0xF);
i2c_set_data_hold_time(i2c, 0x2); i2c_set_data_hold_time(i2c, 0x2);
i2c_set_data_setup_time(i2c, 0x4); i2c_set_data_setup_time(i2c, 0x4);
} }
void i2c_set_7bit_addr_mode(uint32_t i2c) void i2c_set_7bit_addr_mode(uint32_t i2c)
{ {
I2C_CR2(i2c) &= ~I2C_CR2_ADD10; I2C_CR2(i2c) &= ~I2C_CR2_ADD10;
} }
void i2c_set_10bit_addr_mode(uint32_t i2c) void i2c_set_10bit_addr_mode(uint32_t i2c)
{ {
I2C_CR2(i2c) |= I2C_CR2_ADD10; I2C_CR2(i2c) |= I2C_CR2_ADD10;
} }
void i2c_set_7bit_address(uint32_t i2c, uint8_t addr) void i2c_set_7bit_address(uint32_t i2c, uint8_t addr)
{ {
I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_SADD_7BIT_MASK) | ((addr & 0x7F) << I2C_CR2_SADD_7BIT_SHIFT); I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_SADD_7BIT_MASK) |
((addr & 0x7F) << I2C_CR2_SADD_7BIT_SHIFT);
} }
void i2c_set_10bit_address(uint32_t i2c, uint16_t addr) void i2c_set_10bit_address(uint32_t i2c, uint16_t addr)
{ {
I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_SADD_10BIT_MASK) | ((addr & 0x3FF) << I2C_CR2_SADD_10BIT_SHIFT); I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_SADD_10BIT_MASK) |
((addr & 0x3FF) << I2C_CR2_SADD_10BIT_SHIFT);
} }
void i2c_set_write_transfer_dir(uint32_t i2c) void i2c_set_write_transfer_dir(uint32_t i2c)
{ {
I2C_CR2(i2c) &= ~I2C_CR2_RD_WRN; I2C_CR2(i2c) &= ~I2C_CR2_RD_WRN;
} }
void i2c_set_read_transfer_dir(uint32_t i2c) void i2c_set_read_transfer_dir(uint32_t i2c)
{ {
I2C_CR2(i2c) |= I2C_CR2_RD_WRN; I2C_CR2(i2c) |= I2C_CR2_RD_WRN;
} }
void i2c_set_bytes_to_transfer(uint32_t i2c, uint32_t n_bytes) void i2c_set_bytes_to_transfer(uint32_t i2c, uint32_t n_bytes)
{ {
I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_NBYTES_MASK) | (n_bytes << I2C_CR2_NBYTES_SHIFT); I2C_CR2(i2c) = (I2C_CR2(i2c) & ~I2C_CR2_NBYTES_MASK) |
(n_bytes << I2C_CR2_NBYTES_SHIFT);
} }
uint8_t i2c_is_start(uint32_t i2c) uint8_t i2c_is_start(uint32_t i2c)
{ {
if ((I2C_CR2(i2c) & I2C_CR2_START) != 0) { if ((I2C_CR2(i2c) & I2C_CR2_START) != 0) {
return(1); return 1;
} else { }
return(0);
} return 0;
} }
void i2c_enable_autoend(uint32_t i2c) void i2c_enable_autoend(uint32_t i2c)
{ {
I2C_CR2(i2c) |= I2C_CR2_AUTOEND; I2C_CR2(i2c) |= I2C_CR2_AUTOEND;
} }
void i2c_disable_autoend(uint32_t i2c) void i2c_disable_autoend(uint32_t i2c)
{ {
I2C_CR2(i2c) &= ~I2C_CR2_AUTOEND; I2C_CR2(i2c) &= ~I2C_CR2_AUTOEND;
} }
uint8_t i2c_nack(uint32_t i2c) uint8_t i2c_nack(uint32_t i2c)
{ {
if ((I2C_ISR(i2c) & I2C_ISR_NACKF) != 0) { if ((I2C_ISR(i2c) & I2C_ISR_NACKF) != 0) {
return(1); return 1;
} else { }
return(0);
} return 0;
} }
uint8_t i2c_busy(uint32_t i2c) uint8_t i2c_busy(uint32_t i2c)
{ {
if ((I2C_ISR(i2c) & I2C_ISR_BUSY) != 0) { if ((I2C_ISR(i2c) & I2C_ISR_BUSY) != 0) {
return(1); return 1;
} else { }
return(0);
} return 0;
} }
uint8_t i2c_transmit_int_status(uint32_t i2c) uint8_t i2c_transmit_int_status(uint32_t i2c)
{ {
if ((I2C_ISR(i2c) & I2C_ISR_TXIS) != 0) { if ((I2C_ISR(i2c) & I2C_ISR_TXIS) != 0) {
return(1); return 1;
} else { }
return(0);
} return 0;
} }
uint8_t i2c_transfer_complete(uint32_t i2c) uint8_t i2c_transfer_complete(uint32_t i2c)
{ {
if ((I2C_ISR(i2c) & I2C_ISR_TC) != 0) { if ((I2C_ISR(i2c) & I2C_ISR_TC) != 0) {
return(1); return 1;
} else { }
return(0);
} return 0;
} }
uint8_t i2c_received_data(uint32_t i2c) uint8_t i2c_received_data(uint32_t i2c)
{ {
if ((I2C_ISR(i2c) & I2C_ISR_RXNE) != 0) { if ((I2C_ISR(i2c) & I2C_ISR_RXNE) != 0) {
return(1); return 1;
} else { }
return(0);
} return 0;
} }
@ -398,78 +406,79 @@ void i2c_disable_txdma(uint32_t i2c)
I2C_CR1(i2c) &= ~I2C_CR1_TXDMAEN; I2C_CR1(i2c) &= ~I2C_CR1_TXDMAEN;
} }
void write_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, uint8_t size, uint8_t *data) { void write_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, uint8_t size,
int wait; uint8_t *data)
int i;
while (i2c_busy(i2c) == 1) {}
while (i2c_is_start(i2c) == 1) {}
/*Setting transfer properties*/
i2c_set_bytes_to_transfer(i2c, size+1);
i2c_set_7bit_address(i2c, (i2c_addr & 0x7F));
i2c_set_write_transfer_dir(i2c);
i2c_enable_autoend(i2c);
/*start transfer*/
i2c_send_start(i2c);
wait=true;
while (wait) {
if (i2c_transmit_int_status(i2c)) {
wait=false;
}
while (i2c_nack(i2c)){}
}
i2c_send_data(i2c, reg);
for (i=0; i<size; i++) {
wait=true;
while (wait) {
if (i2c_transmit_int_status(i2c)) {
wait=false;
}
while (i2c_nack(i2c)){}
}
i2c_send_data(i2c, data[i]);
}
}
void read_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, uint8_t size, uint8_t *data)
{ {
int wait; int wait;
int i; int i;
while (i2c_busy(i2c) == 1) {} while (i2c_busy(i2c) == 1);
while (i2c_is_start(i2c) == 1) {} while (i2c_is_start(i2c) == 1);
/*Setting transfer properties*/ /*Setting transfer properties*/
i2c_set_bytes_to_transfer(i2c, 1); i2c_set_bytes_to_transfer(i2c, size + 1);
i2c_set_7bit_address(i2c, i2c_addr); i2c_set_7bit_address(i2c, (i2c_addr & 0x7F));
i2c_set_write_transfer_dir(i2c); i2c_set_write_transfer_dir(i2c);
i2c_disable_autoend(i2c); i2c_enable_autoend(i2c);
/*start transfer*/ /*start transfer*/
i2c_send_start(i2c); i2c_send_start(i2c);
wait=true; wait = true;
while (wait) while (wait) {
{ if (i2c_transmit_int_status(i2c)) {
if (i2c_transmit_int_status(i2c)) { wait = false;
wait=false; }
} while (i2c_nack(i2c));
while (i2c_nack(i2c)){} /* Some error */ }
}
i2c_send_data(i2c, reg);
while (i2c_is_start(i2c) == 1) {} i2c_send_data(i2c, reg);
/*Setting transfer properties*/ for (i = 0; i < size; i++) {
i2c_set_bytes_to_transfer(i2c, size); wait = true;
i2c_set_7bit_address(i2c, i2c_addr); while (wait) {
i2c_set_read_transfer_dir(i2c); if (i2c_transmit_int_status(i2c)) {
i2c_enable_autoend(i2c); wait = false;
/*start transfer*/ }
i2c_send_start(i2c); while (i2c_nack(i2c));
}
for (i=0; i<size; i++) { i2c_send_data(i2c, data[i]);
while (i2c_received_data(i2c) == 0) {} }
data[i]=i2c_get_data(i2c);
}
} }
void read_i2c(uint32_t i2c, uint8_t i2c_addr, uint8_t reg, uint8_t size,
uint8_t *data)
{
int wait;
int i;
while (i2c_busy(i2c) == 1);
while (i2c_is_start(i2c) == 1);
/*Setting transfer properties*/
i2c_set_bytes_to_transfer(i2c, 1);
i2c_set_7bit_address(i2c, i2c_addr);
i2c_set_write_transfer_dir(i2c);
i2c_disable_autoend(i2c);
/*start transfer*/
i2c_send_start(i2c);
wait = true;
while (wait) {
if (i2c_transmit_int_status(i2c)) {
wait = false;
}
while (i2c_nack(i2c)); /* Some error */
}
i2c_send_data(i2c, reg);
while (i2c_is_start(i2c) == 1);
/*Setting transfer properties*/
i2c_set_bytes_to_transfer(i2c, size);
i2c_set_7bit_address(i2c, i2c_addr);
i2c_set_read_transfer_dir(i2c);
i2c_enable_autoend(i2c);
/*start transfer*/
i2c_send_start(i2c);
for (i = 0; i < size; i++) {
while (i2c_received_data(i2c) == 0);
data[i] = i2c_get_data(i2c);
}
}
/**@}*/ /**@}*/

186
lib/stm32/f3/rcc.c
View File

@ -30,44 +30,43 @@
uint32_t rcc_ppre1_frequency = 8000000; uint32_t rcc_ppre1_frequency = 8000000;
uint32_t rcc_ppre2_frequency = 8000000; uint32_t rcc_ppre2_frequency = 8000000;
const clock_scale_t hsi_8mhz[CLOCK_END] = const clock_scale_t hsi_8mhz[CLOCK_END] = {
{
{ /* 44MHz */ { /* 44MHz */
.pll= RCC_CFGR_PLLMUL_PLL_IN_CLK_X11, .pll = RCC_CFGR_PLLMUL_PLL_IN_CLK_X11,
.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2, .pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,
.hpre = RCC_CFGR_HPRE_DIV_NONE, .hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE1_DIV_2, .ppre1 = RCC_CFGR_PPRE1_DIV_2,
.ppre2 = RCC_CFGR_PPRE2_DIV_NONE, .ppre2 = RCC_CFGR_PPRE2_DIV_NONE,
.power_save = 1, .power_save = 1,
.flash_config = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_1WS, .flash_config = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_1WS,
.apb1_frequency = 22000000, .apb1_frequency = 22000000,
.apb2_frequency = 44000000, .apb2_frequency = 44000000,
}, },
{ /* 48MHz */ { /* 48MHz */
.pll= RCC_CFGR_PLLMUL_PLL_IN_CLK_X12, .pll = RCC_CFGR_PLLMUL_PLL_IN_CLK_X12,
.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2, .pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,
.hpre = RCC_CFGR_HPRE_DIV_NONE, .hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE1_DIV_2, .ppre1 = RCC_CFGR_PPRE1_DIV_2,
.ppre2 = RCC_CFGR_PPRE2_DIV_NONE, .ppre2 = RCC_CFGR_PPRE2_DIV_NONE,
.power_save = 1, .power_save = 1,
.flash_config = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_1WS, .flash_config = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_1WS,
.apb1_frequency = 24000000, .apb1_frequency = 24000000,
.apb2_frequency = 48000000, .apb2_frequency = 48000000,
}, },
{ /* 64MHz */ { /* 64MHz */
.pll= RCC_CFGR_PLLMUL_PLL_IN_CLK_X16, .pll = RCC_CFGR_PLLMUL_PLL_IN_CLK_X16,
.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2, .pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,
.hpre = RCC_CFGR_HPRE_DIV_NONE, .hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE1_DIV_2, .ppre1 = RCC_CFGR_PPRE1_DIV_2,
.ppre2 = RCC_CFGR_PPRE2_DIV_NONE, .ppre2 = RCC_CFGR_PPRE2_DIV_NONE,
.power_save = 1, .power_save = 1,
.flash_config = FLASH_ACR_PRFTBE| FLASH_ACR_LATENCY_2WS, .flash_config = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_2WS,
.apb1_frequency = 32000000, .apb1_frequency = 32000000,
.apb2_frequency = 64000000, .apb2_frequency = 64000000,
} }
}; };
void rcc_osc_ready_int_clear(osc_t osc) void rcc_osc_ready_int_clear(enum osc osc)
{ {
switch (osc) { switch (osc) {
case PLL: case PLL:
@ -88,7 +87,7 @@ void rcc_osc_ready_int_clear(osc_t osc)
} }
} }
void rcc_osc_ready_int_enable(osc_t osc) void rcc_osc_ready_int_enable(enum osc osc)
{ {
switch (osc) { switch (osc) {
case PLL: case PLL:
@ -109,7 +108,7 @@ void rcc_osc_ready_int_enable(osc_t osc)
} }
} }
void rcc_osc_ready_int_disable(osc_t osc) void rcc_osc_ready_int_disable(enum osc osc)
{ {
switch (osc) { switch (osc) {
case PLL: case PLL:
@ -130,7 +129,7 @@ void rcc_osc_ready_int_disable(osc_t osc)
} }
} }
int rcc_osc_ready_int_flag(osc_t osc) int rcc_osc_ready_int_flag(enum osc osc)
{ {
switch (osc) { switch (osc) {
case PLL: case PLL:
@ -163,7 +162,7 @@ int rcc_css_int_flag(void)
return ((RCC_CIR & RCC_CIR_CSSF) != 0); return ((RCC_CIR & RCC_CIR_CSSF) != 0);
} }
void rcc_wait_for_osc_ready(osc_t osc) void rcc_wait_for_osc_ready(enum osc osc)
{ {
switch (osc) { switch (osc) {
case PLL: case PLL:
@ -185,7 +184,7 @@ void rcc_wait_for_osc_ready(osc_t osc)
} }
void rcc_wait_for_osc_not_ready(osc_t osc) void rcc_wait_for_osc_not_ready(enum osc osc)
{ {
switch (osc) { switch (osc) {
case PLL: case PLL:
@ -206,7 +205,7 @@ void rcc_wait_for_osc_not_ready(osc_t osc)
} }
} }
void rcc_wait_for_sysclk_status(osc_t osc) void rcc_wait_for_sysclk_status(enum osc osc)
{ {
switch (osc) { switch (osc) {
case PLL: case PLL:
@ -224,7 +223,7 @@ void rcc_wait_for_sysclk_status(osc_t osc)
} }
} }
void rcc_osc_on(osc_t osc) void rcc_osc_on(enum osc osc)
{ {
switch (osc) { switch (osc) {
case PLL: case PLL:
@ -245,7 +244,7 @@ void rcc_osc_on(osc_t osc)
} }
} }
void rcc_osc_off(osc_t osc) void rcc_osc_off(enum osc osc)
{ {
switch (osc) { switch (osc) {
case PLL: case PLL:
@ -276,7 +275,7 @@ void rcc_css_disable(void)
RCC_CR &= ~RCC_CR_CSSON; RCC_CR &= ~RCC_CR_CSSON;
} }
void rcc_osc_bypass_enable(osc_t osc) void rcc_osc_bypass_enable(enum osc osc)
{ {
switch (osc) { switch (osc) {
case HSE: case HSE:
@ -293,7 +292,7 @@ void rcc_osc_bypass_enable(osc_t osc)
} }
} }
void rcc_osc_bypass_disable(osc_t osc) void rcc_osc_bypass_disable(enum osc osc)
{ {
switch (osc) { switch (osc) {
case HSE: case HSE:
@ -341,11 +340,11 @@ void rcc_set_sysclk_source(uint32_t clk)
void rcc_set_pll_source(uint32_t pllsrc) void rcc_set_pll_source(uint32_t pllsrc)
{ {
uint32_t reg32; uint32_t reg32;
reg32 = RCC_CFGR; reg32 = RCC_CFGR;
reg32 &= ~RCC_CFGR_PLLSRC; reg32 &= ~RCC_CFGR_PLLSRC;
RCC_CFGR = (reg32 | (pllsrc << 16)); RCC_CFGR = (reg32 | (pllsrc << 16));
} }
void rcc_set_ppre2(uint32_t ppre2) void rcc_set_ppre2(uint32_t ppre2)
@ -378,50 +377,51 @@ void rcc_set_hpre(uint32_t hpre)
void rcc_set_main_pll_hsi(uint32_t pll) void rcc_set_main_pll_hsi(uint32_t pll)
{ {
RCC_CFGR = (~RCC_CFGR_PLLMUL_MASK & RCC_CFGR) | (pll << RCC_CFGR_PLLMUL_SHIFT); RCC_CFGR = (~RCC_CFGR_PLLMUL_MASK & RCC_CFGR) |
(pll << RCC_CFGR_PLLMUL_SHIFT);
} }
uint32_t rcc_get_system_clock_source(void) uint32_t rcc_get_system_clock_source(void)
{ {
/* Return the clock source which is used as system clock. */ /* Return the clock source which is used as system clock. */
return ((RCC_CFGR & 0x000c) >> 2); return (RCC_CFGR & 0x000c) >> 2;
} }
void rcc_clock_setup_hsi(const clock_scale_t *clock) void rcc_clock_setup_hsi(const clock_scale_t *clock)
{ {
/* Enable internal high-speed oscillator. */ /* Enable internal high-speed oscillator. */
rcc_osc_on(HSI); rcc_osc_on(HSI);
rcc_wait_for_osc_ready(HSI); rcc_wait_for_osc_ready(HSI);
/* Select HSI as SYSCLK source. */ /* Select HSI as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_HSI); //se cayo rcc_set_sysclk_source(RCC_CFGR_SW_HSI); /* XXX: se cayo */
rcc_wait_for_sysclk_status(HSI); rcc_wait_for_sysclk_status(HSI);
rcc_osc_off(PLL); rcc_osc_off(PLL);
rcc_wait_for_osc_not_ready(PLL); rcc_wait_for_osc_not_ready(PLL);
rcc_set_pll_source(clock->pllsrc); rcc_set_pll_source(clock->pllsrc);
rcc_set_main_pll_hsi(clock->pll); rcc_set_main_pll_hsi(clock->pll);
/* Enable PLL oscillator and wait for it to stabilize. */ /* Enable PLL oscillator and wait for it to stabilize. */
rcc_osc_on(PLL); rcc_osc_on(PLL);
rcc_wait_for_osc_ready(PLL); rcc_wait_for_osc_ready(PLL);
/* /*
* Set prescalers for AHB, ADC, ABP1, ABP2. * Set prescalers for AHB, ADC, ABP1, ABP2.
* Do this before touching the PLL (TODO: why?). * Do this before touching the PLL (TODO: why?).
*/ */
rcc_set_hpre(clock->hpre); rcc_set_hpre(clock->hpre);
rcc_set_ppre2(clock->ppre2); rcc_set_ppre2(clock->ppre2);
rcc_set_ppre1(clock->ppre1); rcc_set_ppre1(clock->ppre1);
/* Configure flash settings. */ /* Configure flash settings. */
flash_set_ws(clock->flash_config); flash_set_ws(clock->flash_config);
/* Select PLL as SYSCLK source. */ /* Select PLL as SYSCLK source. */
rcc_set_sysclk_source(RCC_CFGR_SW_PLL); //se cayo rcc_set_sysclk_source(RCC_CFGR_SW_PLL); /* XXX: se cayo */
/* Wait for PLL clock to be selected. */ /* Wait for PLL clock to be selected. */
rcc_wait_for_sysclk_status(PLL); rcc_wait_for_sysclk_status(PLL);
/* Set the peripheral clock frequencies used. */ /* Set the peripheral clock frequencies used. */
rcc_ppre1_frequency = clock->apb1_frequency; rcc_ppre1_frequency = clock->apb1_frequency;
rcc_ppre2_frequency = clock->apb2_frequency; rcc_ppre2_frequency = clock->apb2_frequency;
} }
@ -434,35 +434,37 @@ void rcc_backupdomain_reset(void)
RCC_BDCR &= ~RCC_BDCR_BDRST; RCC_BDCR &= ~RCC_BDCR_BDRST;
} }
void rcc_set_i2c_clock_hsi(uint32_t i2c) { void rcc_set_i2c_clock_hsi(uint32_t i2c)
if (i2c==I2C1) { {
RCC_CFGR3 &= ~RCC_CFGR3_I2C1SW; if (i2c == I2C1) {
} RCC_CFGR3 &= ~RCC_CFGR3_I2C1SW;
if (i2c==I2C2) { }
RCC_CFGR3 &= ~RCC_CFGR3_I2C2SW; if (i2c == I2C2) {
} RCC_CFGR3 &= ~RCC_CFGR3_I2C2SW;
}
} }
void rcc_set_i2c_clock_sysclk(uint32_t i2c) { void rcc_set_i2c_clock_sysclk(uint32_t i2c)
if (i2c==I2C1) { {
RCC_CFGR3 |= RCC_CFGR3_I2C1SW; if (i2c == I2C1) {
} RCC_CFGR3 |= RCC_CFGR3_I2C1SW;
if (i2c==I2C2) { }
RCC_CFGR3 |= RCC_CFGR3_I2C2SW; if (i2c == I2C2) {
} RCC_CFGR3 |= RCC_CFGR3_I2C2SW;
}
} }
uint32_t rcc_get_i2c_clocks(void) uint32_t rcc_get_i2c_clocks(void)
{ {
return(RCC_CFGR3 & (RCC_CFGR3_I2C1SW | RCC_CFGR3_I2C2SW)); return RCC_CFGR3 & (RCC_CFGR3_I2C1SW | RCC_CFGR3_I2C2SW);
} }
void rcc_usb_prescale_1_5(void) void rcc_usb_prescale_1_5(void)
{ {
RCC_CFGR &= ~RCC_CFGR_USBPRES; RCC_CFGR &= ~RCC_CFGR_USBPRES;
} }
void rcc_usb_prescale_1(void) void rcc_usb_prescale_1(void)
{ {
RCC_CFGR |= RCC_CFGR_USBPRES; RCC_CFGR |= RCC_CFGR_USBPRES;
} }

2
lib/stm32/f3/spi.c
View File

@ -57,4 +57,4 @@ void spi_fifo_reception_threshold_16bit(uint32_t spi)
void spi_i2s_mode_spi_mode(uint32_t spi) void spi_i2s_mode_spi_mode(uint32_t spi)
{ {
SPI_I2SCFGR(spi) &= ~SPI_I2SCFGR_I2SMOD; SPI_I2SCFGR(spi) &= ~SPI_I2SCFGR_I2SMOD;
} }

4
lib/stm32/f3/usart.c
View File

@ -126,7 +126,7 @@ usart_reg_base
bool usart_get_interrupt_source(uint32_t usart, uint32_t flag) bool usart_get_interrupt_source(uint32_t usart, uint32_t flag)
{ {
uint32_t flag_set = (USART_ISR(usart) & flag); uint32_t flag_set = (USART_ISR(usart) & flag);
/* IDLE, RXNE, TC, TXE interrupts */ /* IDLE, RXNE, TC, TXE interrupts */
if ((flag >= USART_ISR_IDLE) && (flag <= USART_ISR_TXE)) { if ((flag >= USART_ISR_IDLE) && (flag <= USART_ISR_TXE)) {
return ((flag_set & USART_CR1(usart)) != 0); return ((flag_set & USART_CR1(usart)) != 0);
@ -138,4 +138,4 @@ bool usart_get_interrupt_source(uint32_t usart, uint32_t flag)
return false; return false;
} }
/**@}*/ /**@}*/