diff --git a/include/libopencm3/lpc43xx/gpdma.h b/include/libopencm3/lpc43xx/gpdma.h index 371f1b9b..066587fe 100644 --- a/include/libopencm3/lpc43xx/gpdma.h +++ b/include/libopencm3/lpc43xx/gpdma.h @@ -489,7 +489,7 @@ cacheable */ #define GPDMA_CxCONTROL_PROT3_SHIFT (30) #define GPDMA_CxCONTROL_PROT3_MASK (0x1 << GPDMA_CxCONTROL_PROT3_SHIFT) -#define GPDMA_CxCONTROL_PROT3(x) ((x) << GPDMA_CxCONTROL_PROT3_SHIFT) +#define GPDMA_CxCONTROL_PROT3(x) ((x) << GPDMA_CxCONTROL_PROT3_SHIFT) /* I: Terminal count interrupt enable bit */ #define GPDMA_CxCONTROL_I_SHIFT (31) diff --git a/include/libopencm3/lpc43xx/uart.h b/include/libopencm3/lpc43xx/uart.h index d90b501d..28830e35 100644 --- a/include/libopencm3/lpc43xx/uart.h +++ b/include/libopencm3/lpc43xx/uart.h @@ -429,7 +429,7 @@ void uart_init(uart_num_t uart_num, uart_databit_t data_nb_bits, uart_rx_data_ready_t uart_rx_data_ready(uart_num_t uart_num); uint8_t uart_read(uart_num_t uart_num); -uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles, +uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles, uart_error_t *error); void uart_write(uart_num_t uart_num, uint8_t data); diff --git a/lib/lpc43xx/ipc.c b/lib/lpc43xx/ipc.c index 07897588..c26931f2 100644 --- a/lib/lpc43xx/ipc.c +++ b/lib/lpc43xx/ipc.c @@ -30,8 +30,7 @@ void ipc_halt_m0(void) rst_active_status1 = RESET_ACTIVE_STATUS1; /* If the M0 has reset not asserted, halt it... */ - while( (rst_active_status1 & RESET_CTRL1_M0APP_RST) ) - { + while (rst_active_status1 & RESET_CTRL1_M0APP_RST) { RESET_CTRL1 = ((~rst_active_status1) | RESET_CTRL1_M0APP_RST); rst_active_status1 = RESET_ACTIVE_STATUS1; } @@ -51,9 +50,8 @@ void ipc_start_m0(uint32_t cm0_baseaddr) /* If the M0 is being held in reset, release it */ /* 1 = no reset, 0 = reset */ - while( !(rst_active_status1 & RESET_CTRL1_M0APP_RST) ) - { - RESET_CTRL1 = ((~rst_active_status1) & (~RESET_CTRL1_M0APP_RST)); + while (!(rst_active_status1 & RESET_CTRL1_M0APP_RST)) { + RESET_CTRL1 = ((~rst_active_status1) & ~RESET_CTRL1_M0APP_RST); rst_active_status1 = RESET_ACTIVE_STATUS1; } } diff --git a/lib/lpc43xx/ssp.c b/lib/lpc43xx/ssp.c index 9e7a0ad9..b63ec9bd 100644 --- a/lib/lpc43xx/ssp.c +++ b/lib/lpc43xx/ssp.c @@ -128,9 +128,9 @@ uint16_t ssp_transfer(ssp_num_t ssp_num, uint16_t data) * example... */ ssp_wait_until_not_busy(ssp_num); - + /* Wait Until Data Received (Rx FIFO not Empty) */ - while( (SSP_SR(ssp_port) & SSP_SR_RNE) == 0); + while ((SSP_SR(ssp_port) & SSP_SR_RNE) == 0); return SSP_DR(ssp_port); } diff --git a/lib/lpc43xx/timer.c b/lib/lpc43xx/timer.c index 3fe7393f..f263c24a 100644 --- a/lib/lpc43xx/timer.c +++ b/lib/lpc43xx/timer.c @@ -24,47 +24,49 @@ void timer_reset(uint32_t timer_peripheral) { - TIMER_TCR(timer_peripheral) |= TIMER_TCR_CRST; - TIMER_TCR(timer_peripheral) &= ~TIMER_TCR_CRST; + TIMER_TCR(timer_peripheral) |= TIMER_TCR_CRST; + TIMER_TCR(timer_peripheral) &= ~TIMER_TCR_CRST; } void timer_enable_counter(uint32_t timer_peripheral) { - TIMER_TCR(timer_peripheral) |= TIMER_TCR_CEN; + TIMER_TCR(timer_peripheral) |= TIMER_TCR_CEN; } void timer_disable_counter(uint32_t timer_peripheral) { - TIMER_TCR(timer_peripheral) &= ~TIMER_TCR_CEN; + TIMER_TCR(timer_peripheral) &= ~TIMER_TCR_CEN; } void timer_set_counter(uint32_t timer_peripheral, uint32_t count) { - TIMER_TC(timer_peripheral) = count; + TIMER_TC(timer_peripheral) = count; } uint32_t timer_get_counter(uint32_t timer_peripheral) { - return TIMER_TC(timer_peripheral); + return TIMER_TC(timer_peripheral); } uint32_t timer_get_prescaler(uint32_t timer_peripheral) { - return TIMER_PR(timer_peripheral); + return TIMER_PR(timer_peripheral); } void timer_set_prescaler(uint32_t timer_peripheral, uint32_t prescaler) { - TIMER_PR(timer_peripheral) = prescaler; + TIMER_PR(timer_peripheral) = prescaler; } void timer_set_mode(uint32_t timer_peripheral, uint32_t mode) { - TIMER_CTCR(timer_peripheral) = (TIMER_CTCR(timer_peripheral) & TIMER_CTCR_MODE_MASK) | mode; + TIMER_CTCR(timer_peripheral) = mode | + (TIMER_CTCR(timer_peripheral) & TIMER_CTCR_MODE_MASK); } void timer_set_count_input(uint32_t timer_peripheral, uint32_t input) { - TIMER_CTCR(timer_peripheral) = (TIMER_CTCR(timer_peripheral) & TIMER_CTCR_CINSEL_MASK) | input; + TIMER_CTCR(timer_peripheral) = input | + (TIMER_CTCR(timer_peripheral) & TIMER_CTCR_CINSEL_MASK); } diff --git a/lib/lpc43xx/uart.c b/lib/lpc43xx/uart.c index 946b7296..3168ce20 100644 --- a/lib/lpc43xx/uart.c +++ b/lib/lpc43xx/uart.c @@ -36,70 +36,71 @@ #define UART_SRC_IDIVE 0x10 #define UART_CGU_AUTOBLOCK_CLOCK_BIT 11 -#define UART_CGU_BASE_CLK_SEL_SHIFT 24 /* clock source selection (5 bits) */ +/* clock source selection (5 bits) */ +#define UART_CGU_BASE_CLK_SEL_SHIFT 24 uint32_t dummy_read; /* * UART Init function */ -void uart_init(uart_num_t uart_num, - uart_databit_t data_nb_bits, - uart_stopbit_t data_nb_stop, - uart_parity_t data_parity, - uint16_t uart_divisor, - uint8_t uart_divaddval, - uint8_t uart_mulval) +void uart_init(uart_num_t uart_num, uart_databit_t data_nb_bits, + uart_stopbit_t data_nb_stop, uart_parity_t data_parity, + uint16_t uart_divisor, uint8_t uart_divaddval, uint8_t uart_mulval) { uint32_t lcr_config; uint32_t uart_port; uart_port = uart_num; - switch(uart_num) - { - case UART0_NUM: - /* use PLL1 as clock source for UART0 */ - CGU_BASE_UART0_CLK = (CGU_SRC_PLL1<0) { + while ((UART_LSR(uart_port) & UART_LSR_RDR) == 0) { + if (rx_timeout_nb_cycles > 0) { counter++; - if (counter>=rx_timeout_nb_cycles) { + if (counter >= rx_timeout_nb_cycles) { *error = UART_TIMEOUT_ERROR; return 0; } @@ -222,7 +226,7 @@ uint8_t uart_read_timeout(uart_num_t uart_num, uint32_t rx_timeout_nb_cycles, ua return uart_val; } -/* This Function Wait Data TX Ready, and Write Data to UART +/* This Function Wait Data TX Ready, and Write Data to UART if rx_timeout_nb_cycles = 0 Infinite wait */ void uart_write(uart_num_t uart_num, uint8_t data)