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cortexa: Disable interrupts while single stepping.

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This commit is contained in:
Gareth McMullin 2016-04-20 11:35:58 -07:00
parent 88bf92ac36
commit 68bf825042
1 changed files with 5 additions and 0 deletions
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5
src/cortexa.c
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@ -100,6 +100,7 @@ struct cortexa_priv {
#define DBGDSCR_EXTDCCMODE_MASK (3 << 20) #define DBGDSCR_EXTDCCMODE_MASK (3 << 20)
#define DBGDSCR_HDBGEN (1 << 14) #define DBGDSCR_HDBGEN (1 << 14)
#define DBGDSCR_ITREN (1 << 13) #define DBGDSCR_ITREN (1 << 13)
#define DBGDSCR_INTDIS (1 << 11)
#define DBGDSCR_UND_I (1 << 8) #define DBGDSCR_UND_I (1 << 8)
#define DBGDSCR_MOE_MASK (0xf << 2) #define DBGDSCR_MOE_MASK (0xf << 2)
#define DBGDSCR_MOE_HALT_REQ (0x0 << 2) #define DBGDSCR_MOE_HALT_REQ (0x0 << 2)
@ -523,6 +524,10 @@ void cortexa_halt_resume(target *t, bool step)
/* Disable DBGITR. Not sure why, but RRQ is ignored otherwise. */ /* Disable DBGITR. Not sure why, but RRQ is ignored otherwise. */
uint32_t dbgdscr = apb_read(t, DBGDSCR); uint32_t dbgdscr = apb_read(t, DBGDSCR);
if (step)
dbgdscr |= DBGDSCR_INTDIS;
else
dbgdscr &= ~DBGDSCR_INTDIS;
dbgdscr &= ~DBGDSCR_ITREN; dbgdscr &= ~DBGDSCR_ITREN;
apb_write(t, DBGDSCR, dbgdscr); apb_write(t, DBGDSCR, dbgdscr);