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BuFran 2013-07-05 12:46:07 +02:00 committed by Piotr Esden-Tempski
parent 62e6635992
commit 68ee13be4b
15 changed files with 768 additions and 729 deletions
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22
include/libopencm3/stm32/f3/crc.h
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@ -1,15 +1,15 @@
/** @defgroup crc_defines CRC Defines /** @defgroup crc_defines CRC Defines
*
@brief <b>libopencm3 Defined Constants and Types for the STM32F3xx CRC * @brief <b>libopencm3 Defined Constants and Types for the STM32F3xx CRC
Generator </b> * Generator </b>
*
@ingroup STM32F3xx_defines * @ingroup STM32F3xx_defines
*
@version 1.0.0 * @version 1.0.0
*
@date 18 August 2012 * @date 18 August 2012
*
LGPL License Terms @ref lgpl_license * LGPL License Terms @ref lgpl_license
*/ */
/* /*
* This file is part of the libopencm3 project. * This file is part of the libopencm3 project.

20
include/libopencm3/stm32/f3/dac.h
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@ -1,14 +1,14 @@
/** @defgroup dac_defines DAC Defines /** @defgroup dac_defines DAC Defines
*
@brief <b>Defined Constants and Types for the STM32F3xx DAC</b> * @brief <b>Defined Constants and Types for the STM32F3xx DAC</b>
*
@ingroup STM32F3xx_defines * @ingroup STM32F3xx_defines
*
@version 1.0.0 * @version 1.0.0
*
@date 5 December 2012 * @date 5 December 2012
*
LGPL License Terms @ref lgpl_license * LGPL License Terms @ref lgpl_license
*/ */
/* /*

20
include/libopencm3/stm32/f3/dma.h
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@ -1,14 +1,14 @@
/** @defgroup dma_defines DMA Defines /** @defgroup dma_defines DMA Defines
*
@ingroup STM32F3xx_defines * @ingroup STM32F3xx_defines
*
@brief Defined Constants and Types for the STM32F3xx DMA Controller * @brief Defined Constants and Types for the STM32F3xx DMA Controller
*
@version 1.0.0 * @version 1.0.0
*
@date 30 November 2012 * @date 30 November 2012
*
LGPL License Terms @ref lgpl_license * LGPL License Terms @ref lgpl_license
*/ */
/* /*

21
include/libopencm3/stm32/f3/gpio.h
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@ -1,14 +1,15 @@
/** @defgroup gpio_defines GPIO Defines /** @defgroup gpio_defines GPIO Defines
*
@brief <b>Defined Constants and Types for the STM32F3xx General Purpose I/O</b> * @brief <b>Defined Constants and Types for the STM32F3xx General Purpose
* I/O</b>
@ingroup STM32F3xx_defines *
* @ingroup STM32F3xx_defines
@version 1.0.0 *
* @version 1.0.0
@date 1 July 2012 *
* @date 1 July 2012
LGPL License Terms @ref lgpl_license *
* LGPL License Terms @ref lgpl_license
*/ */
/* /*

25
include/libopencm3/stm32/f3/i2c.h
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@ -1,14 +1,14 @@
/** @defgroup i2c_defines I2C Defines /** @defgroup i2c_defines I2C Defines
*
@brief <b>Defined Constants and Types for the STM32F4xx I2C </b> * @brief <b>Defined Constants and Types for the STM32F4xx I2C </b>
*
@ingroup STM32F4xx_defines * @ingroup STM32F4xx_defines
*
@version 1.0.0 * @version 1.0.0
*
@date 12 October 2012 * @date 12 October 2012
*
LGPL License Terms @ref lgpl_license * LGPL License Terms @ref lgpl_license
*/ */
/* /*
@ -41,9 +41,8 @@ LGPL License Terms @ref lgpl_license
/* I2C register base addresses (for convenience) */ /* I2C register base addresses (for convenience) */
/*****************************************************************************/ /*****************************************************************************/
/** @defgroup i2c_reg_base I2C register base address /** @defgroup i2c_reg_base I2C register base address
@ingroup i2c_defines * @ingroup i2c_defines
* @{*/
@{*/
#define I2C1 I2C1_BASE #define I2C1 I2C1_BASE
#define I2C2 I2C2_BASE #define I2C2 I2C2_BASE
/**@}*/ /**@}*/

22
include/libopencm3/stm32/f3/iwdg.h
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@ -1,15 +1,15 @@
/** @defgroup iwdg_defines IWDG Defines /** @defgroup iwdg_defines IWDG Defines
*
@brief <b>Defined Constants and Types for the STM32F3xx Independent Watchdog * @brief <b>Defined Constants and Types for the STM32F3xx Independent Watchdog
Timer</b> * Timer</b>
*
@ingroup STM32F3xx_defines * @ingroup STM32F3xx_defines
*
@version 1.0.0 * @version 1.0.0
*
@date 18 August 2012 * @date 18 August 2012
*
LGPL License Terms @ref lgpl_license * LGPL License Terms @ref lgpl_license
*/ */
/* /*
* This file is part of the libopencm3 project. * This file is part of the libopencm3 project.

26
include/libopencm3/stm32/f3/spi.h
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@ -1,14 +1,14 @@
/** @defgroup spi_defines SPI Defines /** @defgroup spi_defines SPI Defines
*
@brief <b>Defined Constants and Types for the STM32F3xx SPI</b> * @brief <b>Defined Constants and Types for the STM32F3xx SPI</b>
*
@ingroup STM32F3xx_defines * @ingroup STM32F3xx_defines
*
@version 1.0.0 * @version 1.0.0
*
@date 5 December 2012 * @date 5 December 2012
*
LGPL License Terms @ref lgpl_license * LGPL License Terms @ref lgpl_license
*/ */
/* /*
@ -37,9 +37,9 @@ LGPL License Terms @ref lgpl_license
/* DFF: Data frame format */ /* DFF: Data frame format */
/****************************************************************************/ /****************************************************************************/
/** @defgroup spi_dff SPI data frame format /** @defgroup spi_dff SPI data frame format
@ingroup spi_defines * @ingroup spi_defines
*
@{*/ * @{*/
#define SPI_DR8(spi_base) MMIO8(spi_base + 0x0c) #define SPI_DR8(spi_base) MMIO8(spi_base + 0x0c)
#define SPI1_DR8 SPI_DR8(SPI1_BASE) #define SPI1_DR8 SPI_DR8(SPI1_BASE)

24
include/libopencm3/stm32/f3/timer.h
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@ -1,16 +1,16 @@
/** @defgroup timer_defines Timer Defines /** @defgroup timer_defines Timer Defines
*
@brief <b>libopencm3 Defined Constants and Types for the STM32F3xx Timers</b> * @brief <b>libopencm3 Defined Constants and Types for the STM32F3xx Timers</b>
*
@ingroup STM32F3xx_defines * @ingroup STM32F3xx_defines
*
@version 1.0.0 * @version 1.0.0
*
@date 8 March 2013 * @date 8 March 2013
*
@author @htmlonly &copy; @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com> * @author @htmlonly &copy; @endhtmlonly 2011 Fergus Noble <fergusnoble@gmail.com>
*
LGPL License Terms @ref lgpl_license * LGPL License Terms @ref lgpl_license
*/ */
/* /*
* This file is part of the libopencm3 project. * This file is part of the libopencm3 project.

20
include/libopencm3/stm32/f3/usart.h
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@ -1,14 +1,14 @@
/** @defgroup usart_defines USART Defines /** @defgroup usart_defines USART Defines
*
@brief <b>Defined Constants and Types for the STM32F3xx USART</b> * @brief <b>Defined Constants and Types for the STM32F3xx USART</b>
*
@ingroup STM32F3xx_defines * @ingroup STM32F3xx_defines
*
@version 1.0.0 * @version 1.0.0
*
@date 5 December 2012 * @date 5 December 2012
*
LGPL License Terms @ref lgpl_license * LGPL License Terms @ref lgpl_license
*/ */
/* /*

945
lib/stm32/f3/adc.c
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22
lib/stm32/f3/crc.c
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@ -1,15 +1,15 @@
/** @defgroup crc_file CRC /** @defgroup crc_file CRC
*
@ingroup STM32F3xx * @ingroup STM32F3xx
*
@brief <b>libopencm3 STM32F3xx CRC</b> * @brief <b>libopencm3 STM32F3xx CRC</b>
*
@version 1.0.0 * @version 1.0.0
*
@date 15 October 2012 * @date 15 October 2012
*
LGPL License Terms @ref lgpl_license * LGPL License Terms @ref lgpl_license
*/ */
/* /*
* This file is part of the libopencm3 project. * This file is part of the libopencm3 project.

22
lib/stm32/f3/dac.c
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@ -1,15 +1,15 @@
/** @defgroup dac_file DAC /** @defgroup dac_file DAC
*
@ingroup STM32F3xx * @ingroup STM32F3xx
*
@brief <b>libopencm3 STM32F3xx DAC</b> * @brief <b>libopencm3 STM32F3xx DAC</b>
*
@version 1.0.0 * @version 1.0.0
*
@date 18 August 2012 * @date 18 August 2012
*
LGPL License Terms @ref lgpl_license * LGPL License Terms @ref lgpl_license
*/ */
/* /*
* This file is part of the libopencm3 project. * This file is part of the libopencm3 project.

172
lib/stm32/f3/i2c.c
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@ -1,15 +1,15 @@
/** @defgroup i2c_file I2C /** @defgroup i2c_file I2C
*
@ingroup STM32F3xx * @ingroup STM32F3xx
*
@brief <b>libopencm3 STM32F3xx I2C</b> * @brief <b>libopencm3 STM32F3xx I2C</b>
*
@version 1.0.0 * @version 1.0.0
*
@date 15 October 2012 * @date 15 October 2012
*
LGPL License Terms @ref lgpl_license * LGPL License Terms @ref lgpl_license
*/ */
/* /*
* This file is part of the libopencm3 project. * This file is part of the libopencm3 project.
@ -35,12 +35,13 @@ LGPL License Terms @ref lgpl_license
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief I2C Reset. /** @brief I2C Reset.
*
The I2C peripheral and all its associated configuration registers are placed in * The I2C peripheral and all its associated configuration registers are placed
the reset condition. The reset is effected via the RCC peripheral reset system. * in the reset condition. The reset is effected via the RCC peripheral reset
* system.
@param[in] i2c Unsigned int32. I2C peripheral identifier @ref i2c_reg_base. *
*/ * @param[in] i2c Unsigned int32. I2C peripheral identifier @ref i2c_reg_base.
*/
void i2c_reset(uint32_t i2c) void i2c_reset(uint32_t i2c)
{ {
@ -58,9 +59,9 @@ void i2c_reset(uint32_t i2c)
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief I2C Peripheral Enable. /** @brief I2C Peripheral Enable.
*
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/ */
void i2c_peripheral_enable(uint32_t i2c) void i2c_peripheral_enable(uint32_t i2c)
{ {
@ -69,12 +70,13 @@ void i2c_peripheral_enable(uint32_t i2c)
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief I2C Peripheral Disable. /** @brief I2C Peripheral Disable.
*
This must not be reset while in Master mode until a communication has finished. * This must not be reset while in Master mode until a communication has
In Slave mode, the peripheral is disabled only after communication has ended. * finished. In Slave mode, the peripheral is disabled only after communication
* has ended.
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. *
*/ * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/
void i2c_peripheral_disable(uint32_t i2c) void i2c_peripheral_disable(uint32_t i2c)
{ {
@ -83,13 +85,13 @@ void i2c_peripheral_disable(uint32_t i2c)
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief I2C Send Start Condition. /** @brief I2C Send Start Condition.
*
If in Master mode this will cause a restart condition to occur at the end of the * If in Master mode this will cause a restart condition to occur at the end of
current transmission. If in Slave mode, this will initiate a start condition * the current transmission. If in Slave mode, this will initiate a start
when the current bus activity is completed. * condition when the current bus activity is completed.
*
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/ */
void i2c_send_start(uint32_t i2c) void i2c_send_start(uint32_t i2c)
{ {
@ -98,12 +100,12 @@ void i2c_send_start(uint32_t i2c)
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief I2C Send Stop Condition. /** @brief I2C Send Stop Condition.
*
After the current byte transfer this will initiate a stop condition if in Master * After the current byte transfer this will initiate a stop condition if in
mode, or simply release the bus if in Slave mode. * Master mode, or simply release the bus if in Slave mode.
*
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/ */
void i2c_send_stop(uint32_t i2c) void i2c_send_stop(uint32_t i2c)
{ {
@ -112,11 +114,11 @@ void i2c_send_stop(uint32_t i2c)
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief I2C Clear Stop Flag. /** @brief I2C Clear Stop Flag.
*
Clear the "Send Stop" flag in the I2C config register * Clear the "Send Stop" flag in the I2C config register
*
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/ */
void i2c_clear_stop(uint32_t i2c) void i2c_clear_stop(uint32_t i2c)
{ {
I2C_ICR(i2c) |= I2C_ICR_STOPCF; I2C_ICR(i2c) |= I2C_ICR_STOPCF;
@ -124,12 +126,12 @@ void i2c_clear_stop(uint32_t i2c)
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief I2C Set the 7 bit Slave Address for the Peripheral. /** @brief I2C Set the 7 bit Slave Address for the Peripheral.
*
This sets an address for Slave mode operation, in 7 bit form. * This sets an address for Slave mode operation, in 7 bit form.
*
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
@param[in] slave Unsigned int8. Slave address 0...127. * @param[in] slave Unsigned int8. Slave address 0...127.
*/ */
void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave) void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave)
{ {
@ -140,14 +142,14 @@ void i2c_set_own_7bit_slave_address(uint32_t i2c, uint8_t slave)
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief I2C Set the 10 bit Slave Address for the Peripheral. /** @brief I2C Set the 10 bit Slave Address for the Peripheral.
*
This sets an address for Slave mode operation, in 10 bit form. * This sets an address for Slave mode operation, in 10 bit form.
*
@todo add "I2C_OAR1(i2c) |= (1 << 14);" as above * @todo add "I2C_OAR1(i2c) |= (1 << 14);" as above
*
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
@param[in] slave Unsigned int16. Slave address 0...1023. * @param[in] slave Unsigned int16. Slave address 0...1023.
*/ */
void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave) void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave)
{ {
@ -156,10 +158,10 @@ void i2c_set_own_10bit_slave_address(uint32_t i2c, uint16_t slave)
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief I2C Send Data. /** @brief I2C Send Data.
*
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
@param[in] data Unsigned int8. Byte to send. * @param[in] data Unsigned int8. Byte to send.
*/ */
void i2c_send_data(uint32_t i2c, uint8_t data) void i2c_send_data(uint32_t i2c, uint8_t data)
{ {
@ -168,9 +170,9 @@ void i2c_send_data(uint32_t i2c, uint8_t data)
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief I2C Get Data. /** @brief I2C Get Data.
*
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/ */
uint8_t i2c_get_data(uint32_t i2c) uint8_t i2c_get_data(uint32_t i2c)
{ {
return I2C_RXDR(i2c) & 0xff; return I2C_RXDR(i2c) & 0xff;
@ -346,10 +348,10 @@ uint8_t i2c_received_data(uint32_t i2c)
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief I2C Enable Interrupt /** @brief I2C Enable Interrupt
*
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
@param[in] interrupt Unsigned int32. Interrupt to enable. * @param[in] interrupt Unsigned int32. Interrupt to enable.
*/ */
void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt) void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt)
{ {
I2C_CR1(i2c) |= interrupt; I2C_CR1(i2c) |= interrupt;
@ -357,10 +359,10 @@ void i2c_enable_interrupt(uint32_t i2c, uint32_t interrupt)
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief I2C Disable Interrupt /** @brief I2C Disable Interrupt
*
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
@param[in] interrupt Unsigned int32. Interrupt to disable. * @param[in] interrupt Unsigned int32. Interrupt to disable.
*/ */
void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt) void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt)
{ {
I2C_CR1(i2c) &= ~interrupt; I2C_CR1(i2c) &= ~interrupt;
@ -368,9 +370,9 @@ void i2c_disable_interrupt(uint32_t i2c, uint32_t interrupt)
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief I2C Enable reception DMA /** @brief I2C Enable reception DMA
*
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/ */
void i2c_enable_rxdma(uint32_t i2c) void i2c_enable_rxdma(uint32_t i2c)
{ {
I2C_CR1(i2c) |= I2C_CR1_RXDMAEN; I2C_CR1(i2c) |= I2C_CR1_RXDMAEN;
@ -378,9 +380,9 @@ void i2c_enable_rxdma(uint32_t i2c)
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief I2C Disable reception DMA /** @brief I2C Disable reception DMA
*
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/ */
void i2c_disable_rxdma(uint32_t i2c) void i2c_disable_rxdma(uint32_t i2c)
{ {
I2C_CR1(i2c) &= ~I2C_CR1_RXDMAEN; I2C_CR1(i2c) &= ~I2C_CR1_RXDMAEN;
@ -388,9 +390,9 @@ void i2c_disable_rxdma(uint32_t i2c)
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief I2C Enable transmission DMA /** @brief I2C Enable transmission DMA
*
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/ */
void i2c_enable_txdma(uint32_t i2c) void i2c_enable_txdma(uint32_t i2c)
{ {
I2C_CR1(i2c) |= I2C_CR1_TXDMAEN; I2C_CR1(i2c) |= I2C_CR1_TXDMAEN;
@ -398,9 +400,9 @@ void i2c_enable_txdma(uint32_t i2c)
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief I2C Disable transmission DMA /** @brief I2C Disable transmission DMA
*
@param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. * @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base.
*/ */
void i2c_disable_txdma(uint32_t i2c) void i2c_disable_txdma(uint32_t i2c)
{ {
I2C_CR1(i2c) &= ~I2C_CR1_TXDMAEN; I2C_CR1(i2c) &= ~I2C_CR1_TXDMAEN;

22
lib/stm32/f3/iwdg.c
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@ -1,15 +1,15 @@
/** @defgroup iwdg_file IWDG /** @defgroup iwdg_file IWDG
*
@ingroup STM32F3xx * @ingroup STM32F3xx
*
@brief <b>libopencm3 STM32F3xx Independent Watchdog Timer</b> * @brief <b>libopencm3 STM32F3xx Independent Watchdog Timer</b>
*
@version 1.0.0 * @version 1.0.0
*
@date 18 August 2012 * @date 18 August 2012
*
LGPL License Terms @ref lgpl_license * LGPL License Terms @ref lgpl_license
*/ */
/* /*
* This file is part of the libopencm3 project. * This file is part of the libopencm3 project.

114
lib/stm32/f3/usart.c
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@ -1,15 +1,15 @@
/** @defgroup usart_file USART /** @defgroup usart_file USART
*
@ingroup STM32F3xx * @ingroup STM32F3xx
*
@brief <b>libopencm3 STM32F3xx USART</b> * @brief <b>libopencm3 STM32F3xx USART</b>
*
@version 1.0.0 * @version 1.0.0
*
@date 30 August 2012 * @date 30 August 2012
*
LGPL License Terms @ref lgpl_license * LGPL License Terms @ref lgpl_license
*/ */
/* /*
* This file is part of the libopencm3 project. * This file is part of the libopencm3 project.
@ -33,11 +33,11 @@ LGPL License Terms @ref lgpl_license
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief USART Send a Data Word. /** @brief USART Send a Data Word.
*
@param[in] usart unsigned 32 bit. USART block register address base @ref * @param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base * usart_reg_base
@param[in] data unsigned 16 bit. * @param[in] data unsigned 16 bit.
*/ */
void usart_send(uint32_t usart, uint16_t data) void usart_send(uint32_t usart, uint16_t data)
{ {
@ -47,14 +47,14 @@ void usart_send(uint32_t usart, uint16_t data)
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief USART Read a Received Data Word. /** @brief USART Read a Received Data Word.
*
If parity is enabled the MSB (bit 7 or 8 depending on the word length) is the * If parity is enabled the MSB (bit 7 or 8 depending on the word length) is
parity bit. * the parity bit.
*
@param[in] usart unsigned 32 bit. USART block register address base @ref * @param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base * usart_reg_base
@returns unsigned 16 bit data word. * @returns unsigned 16 bit data word.
*/ */
uint16_t usart_recv(uint32_t usart) uint16_t usart_recv(uint32_t usart)
{ {
@ -64,13 +64,13 @@ uint16_t usart_recv(uint32_t usart)
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief USART Wait for Transmit Data Buffer Empty /** @brief USART Wait for Transmit Data Buffer Empty
*
Blocks until the transmit data buffer becomes empty and is ready to accept the * Blocks until the transmit data buffer becomes empty and is ready to accept
next data word. * the next data word.
*
@param[in] usart unsigned 32 bit. USART block register address base @ref * @param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base * usart_reg_base
*/ */
void usart_wait_send_ready(uint32_t usart) void usart_wait_send_ready(uint32_t usart)
{ {
@ -80,12 +80,12 @@ void usart_wait_send_ready(uint32_t usart)
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief USART Wait for Received Data Available /** @brief USART Wait for Received Data Available
*
Blocks until the receive data buffer holds a valid received data word. * Blocks until the receive data buffer holds a valid received data word.
*
@param[in] usart unsigned 32 bit. USART block register address base @ref * @param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base * usart_reg_base
*/ */
void usart_wait_recv_ready(uint32_t usart) void usart_wait_recv_ready(uint32_t usart)
{ {
@ -95,12 +95,12 @@ void usart_wait_recv_ready(uint32_t usart)
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief USART Read a Status Flag. /** @brief USART Read a Status Flag.
*
@param[in] usart unsigned 32 bit. USART block register address base @ref * @param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base * usart_reg_base
@param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags. * @param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags.
@returns boolean: flag set. * @returns boolean: flag set.
*/ */
bool usart_get_flag(uint32_t usart, uint32_t flag) bool usart_get_flag(uint32_t usart, uint32_t flag)
{ {
@ -109,20 +109,20 @@ bool usart_get_flag(uint32_t usart, uint32_t flag)
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief USART Return Interrupt Source. /** @brief USART Return Interrupt Source.
*
Returns true if the specified interrupt flag (IDLE, RXNE, TC, TXE or OE) was * Returns true if the specified interrupt flag (IDLE, RXNE, TC, TXE or OE) was
set and the interrupt was enabled. If the specified flag is not an interrupt * set and the interrupt was enabled. If the specified flag is not an interrupt
flag, the function returns false. * flag, the function returns false.
*
@todo These are the most important interrupts likely to be used. Others * @todo These are the most important interrupts likely to be used. Others
relating to LIN break, and error conditions in multibuffer communication, need * relating to LIN break, and error conditions in multibuffer communication,
to be added for completeness. * need to be added for completeness.
*
@param[in] usart unsigned 32 bit. USART block register address base @ref * @param[in] usart unsigned 32 bit. USART block register address base @ref
usart_reg_base * usart_reg_base
@param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags. * @param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags.
@returns boolean: flag and interrupt enable both set. * @returns boolean: flag and interrupt enable both set.
*/ */
bool usart_get_interrupt_source(uint32_t usart, uint32_t flag) bool usart_get_interrupt_source(uint32_t usart, uint32_t flag)
{ {