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Some updates to the F2 GPIO header plus implementation of GPIO convenience functions.

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This commit is contained in:
Fergus Noble 2011-09-14 23:57:43 -07:00
parent aa3089e8c4
commit 6912cbe71f
2 changed files with 165 additions and 5 deletions
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14
include/libopencm3/stm32/f2/gpio.h
View File

@ -179,7 +179,8 @@
/* --- GPIOx_MODER values -------------------------------------------------- */
#define GPIO_MODE(n, mode) (mode << (2*n))
#define GPIO_MODE(n, mode) (mode << (2*(n)))
#define GPIO_MODE_MASK(n) (0x3 << (2*(n)))
#define GPIO_MODE_INPUT 0x0
#define GPIO_MODE_OUTPUT 0x1
#define GPIO_MODE_AF 0x2
@ -192,7 +193,8 @@
/* --- GPIOx_OSPEEDR values ------------------------------------------------ */
#define GPIO_OSPEED(n, speed) (speed << (2*n))
#define GPIO_OSPEED(n, speed) (speed << (2*(n)))
#define GPIO_OSPEED_MASK(n) (0x3 << (2*(n)))
#define GPIO_OSPEED_2MHZ 0x0
#define GPIO_OSPEED_25MHZ 0x1
#define GPIO_OSPEED_50MHZ 0x2
@ -200,7 +202,8 @@
/* --- GPIOx_PUPDR values -------------------------------------------------- */
#define GPIO_PUPD(n, pupd) (pupd << (2*n))
#define GPIO_PUPD(n, pupd) (pupd << (2*(n)))
#define GPIO_PUPD_MASK(n) (0x3 << (2*(n)))
#define GPIO_PUPD_NONE 0x0
#define GPIO_PUPD_PULLUP 0x1
#define GPIO_PUPD_PULLDOWN 0x2
@ -228,7 +231,8 @@
/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */
/* See Datasheet Table 6 (pg. 48) for alternate function mappings. */
#define GPIO_AFR(n, af) (af << (n*4))
#define GPIO_AFR(n, af) (af << ((n)*4))
#define GPIO_AFR_MASK(n) (0xF << ((n)*4))
#define GPIO_AF0 0x0
#define GPIO_AF1 0x1
#define GPIO_AF2 0x2
@ -262,7 +266,7 @@ void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios);
void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios);
void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios);
/* This part of the API is compatible with the F1 series */
/* This part of the API is compatible with the F1 series ------------------- */
void gpio_set(u32 gpioport, u16 gpios);
void gpio_clear(u32 gpioport, u16 gpios);
u16 gpio_get(u32 gpioport, u16 gpios);

156
lib/stm32f2/gpio.c Normal file
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@ -0,0 +1,156 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Basic GPIO handling API.
*
* Examples:
* gpio_set_mode(GPIOC, GPIO_MODE_OUTPUT_2_MHZ,
* GPIO_CNF_OUTPUT_PUSHPULL, GPIO12);
* gpio_set(GPIOB, GPIO4);
* gpio_clear(GPIOG, GPIO2 | GPIO9);
* gpio_get(GPIOC, GPIO1);
* gpio_toggle(GPIOA, GPIO7 | GPIO8);
* reg16 = gpio_port_read(GPIOD);
* gpio_port_write(GPIOF, 0xc8fe);
*
* TODO:
* - GPIO remapping support
*/
#include <libopencm3/stm32/f2/gpio.h>
void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios)
{
u16 i;
u16 moder, pupd;
/*
* We want to set the config only for the pins mentioned in gpios,
* but keeping the others, so read out the actual config first.
*/
moder = GPIO_MODER(gpioport);
pupd = GPIO_PUPDR(gpioport);
for (i = 0; i < 16; i++) {
if (!((1 << i) & gpios))
continue;
moder &= ~GPIO_MODE_MASK(i);
moder |= GPIO_MODE(i, mode);
pupd &= ~GPIO_PUPD_MASK(i);
pupd |= GPIO_PUPD(i, pull_up_down);
}
/* Set mode and pull up/down control registers. */
GPIO_MODER(gpioport) = moder;
GPIO_PUPDR(gpioport) = pupd;
}
void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios)
{
u16 i;
u16 ospeedr;
if (otype == 0x1)
GPIO_OTYPER(gpioport) |= gpios;
else
GPIO_OTYPER(gpioport) &= ~gpios;
ospeedr = GPIO_OSPEEDR(gpioport);
for (i = 0; i < 16; i++) {
if (!((1 << i) & gpios))
continue
ospeedr &= ~GPIO_OSPEEDR_MASK(i);
ospeedr |= GPIO_OSPEEDR(i, mode);
}
GPIO_OSPEEDR(gpioport) = ospeedr;
}
void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios)
{
u16 i;
u16 afrl, afrh;
afrl = GPIO_AFRL(gpioport);
afrh = GPIO_AFRH(gpioport);
for (i = 0; i < 8; i++) {
if (!((1 << i) & gpios))
continue
afrl &= GPIO_AFR_MASK(i);
afrl |= GPIO_AFR(i, alt_func_num);
}
for (i = 8; i < 16; i++) {
if (!((1 << i) & gpios))
continue
afrl &= GPIO_AFR_MASK(i-8);
afrh |= GPIO_AFR(i-8, alt_func_num);
}
GPIO_AFRL(gpioport) = afrl;
GPIO_AFRH(gpioport) = afrh;
}
void gpio_set(u32 gpioport, u16 gpios)
{
GPIO_BSRR(gpioport) = gpios;
}
void gpio_clear(u32 gpioport, u16 gpios)
{
GPIO_BSRR(gpioport) = gpios << 16;
}
u16 gpio_get(u32 gpioport, u16 gpios)
{
return gpio_port_read(gpioport) & gpios;
}
void gpio_toggle(u32 gpioport, u16 gpios)
{
GPIO_ODR(gpioport) = GPIO_IDR(gpioport) ^ gpios;
}
u16 gpio_port_read(u32 gpioport)
{
return (u16)GPIO_IDR(gpioport);
}
void gpio_port_write(u32 gpioport, u16 data)
{
GPIO_ODR(gpioport) = data;
}
void gpio_port_config_lock(u32 gpioport, u16 gpios)
{
u32 reg32;
/* Special "Lock Key Writing Sequence", see datasheet. */
GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */
GPIO_LCKR(gpioport) = ~GPIO_LCKK & gpios; /* Clear LCKK. */
GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */
reg32 = GPIO_LCKR(gpioport); /* Read LCKK. */
reg32 = GPIO_LCKR(gpioport); /* Read LCKK again. */
/* If (reg32 & GPIO_LCKK) is true, the lock is now active. */
}