diff --git a/include/libopencm3/stm32/flash.h b/include/libopencm3/stm32/flash.h index 36132dfb..88384980 100644 --- a/include/libopencm3/stm32/flash.h +++ b/include/libopencm3/stm32/flash.h @@ -32,6 +32,8 @@ # include #elif defined(STM32L1) # include +#elif defined(STM32L4) +# include #else # error "stm32 family not defined." #endif diff --git a/include/libopencm3/stm32/l4/flash.h b/include/libopencm3/stm32/l4/flash.h new file mode 100644 index 00000000..fa76e5fe --- /dev/null +++ b/include/libopencm3/stm32/l4/flash.h @@ -0,0 +1,254 @@ +/** @defgroup flash_defines FLASH Defines + * + * @ingroup STM32L4xx_defines + * + * @brief Defined Constants and Types for the STM32L4xx Flash Control + * + * @version 1.0.0 + * + * @author @htmlonly © @endhtmlonly 2016 Benjamin Levine + * + * @date 12 February 2016 + * + * LGPL License Terms @ref lgpl_license + * */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2016 Benjamin Levine + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/* + * For details see: + * RM0351 Reference manual: STM32L4x6 advanced ARM®-based 32-bit MCUs + * December 2015, Doc ID 024597 Rev 3 + */ + +/**@{*/ +#ifndef LIBOPENCM3_FLASH_H +#define LIBOPENCM3_FLASH_H + +/* --- FLASH registers ----------------------------------------------------- */ + +#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) +#define FLASH_PDKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04) +#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) +#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) +#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) +#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) +#define FLASH_ECCR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18) +#define FLASH_OPTR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20) +#define FLASH_PCROP1SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x24) +#define FLASH_PCROP1ER MMIO32(FLASH_MEM_INTERFACE_BASE + 0x28) +#define FLASH_WRP1AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x2C) +#define FLASH_WRP1BR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x30) +#define FLASH_PCROP2SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x44) +#define FLASH_PCROP2ER MMIO32(FLASH_MEM_INTERFACE_BASE + 0x48) +#define FLASH_WRP2AR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x4C) +#define FLASH_WRP2BR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x50) + +/* --- FLASH_ACR values ---------------------------------------------------- */ + +#define FLASH_ACR_SLEEP_PD (1 << 14) +#define FLASH_ACR_RUN_PD (1 << 13) +#define FLASH_ACR_DCRST (1 << 12) +#define FLASH_ACR_ICRST (1 << 11) +#define FLASH_ACR_DCEN (1 << 10) +#define FLASH_ACR_ICEN (1 << 9) +#define FLASH_ACR_PRFTEN (1 << 8) + +#define FLASH_ACR_LATENCY_SHIFT 0 +#define FLASH_ACR_LATENCY_MASK 0x03 + +#define FLASH_ACR_LATENCY_0WS 0x00 +#define FLASH_ACR_LATENCY_1WS 0x01 +#define FLASH_ACR_LATENCY_2WS 0x02 +#define FLASH_ACR_LATENCY_3WS 0x03 + +/* --- FLASH_SR values ----------------------------------------------------- */ + +#define FLASH_SR_BSY (1 << 16) +#define FLASH_SR_OPTVERR (1 << 15) +#define FLASH_SR_RDERR (1 << 14) +#define FLASH_SR_FASTERR (1 << 9) +#define FLASH_SR_MISERR (1 << 8) +#define FLASH_SR_PGSERR (1 << 7) +#define FLASH_SR_SIZERR (1 << 6) +#define FLASH_SR_PGAERR (1 << 5) +#define FLASH_SR_WRPERR (1 << 4) +#define FLASH_SR_PROGERR (1 << 3) +#define FLASH_SR_OPERR (1 << 1) +#define FLASH_SR_EOP (1 << 0) + +/* --- FLASH_CR values ----------------------------------------------------- */ + +#define FLASH_CR_LOCK (1 << 31) +#define FLASH_CR_OPTLOCK (1 << 30) +#define FLASH_CR_OBL_LAUNCH (1 << 27) +#define FLASH_CR_RDERRIE (1 << 26) +#define FLASH_CR_ERRIE (1 << 25) +#define FLASH_CR_EOPIE (1 << 24) +#define FLASH_CR_FSTPG (1 << 18) +#define FLASH_CR_OPTSTRT (1 << 17) +#define FLASH_CR_START (1 << 16) +#define FLASH_CR_MER2 (1 << 15) +#define FLASH_CR_BKER (1 << 11) +#define FLASH_CR_MER1 (1 << 2) +#define FLASH_CR_PER (1 << 1) +#define FLASH_CR_PG (1 << 0) + +#define FLASH_CR_PNB_SHIFT 3 +#define FLASH_CR_PNB_MASK 0xff + +/* --- FLASH_ECCR values -------------------------------------------------- */ + +#define FLASH_ECCR_ECCD (1 << 31) +#define FLASH_ECCR_ECCC (1 << 30) +#define FLASH_ECCR_ECCIE (1 << 24) +#define FLASH_ECCR_SYSF_ECC (1 << 20) +#define FLASH_ECCR_BK_ECC (1 << 19) + +#define FLASH_ECCR_ADDR_ECC_SHIFT 0 +#define FLASH_ECCR_ADDR_ECC_MASK 0x7ffff + +/* --- FLASH_OPTR values -------------------------------------------------- */ + +#define FLASH_OPTR_SRAM2_RST (1 << 25) +#define FLASH_OPTR_SRAM2_PE (1 << 24) +#define FLASH_OPTR_nBOOT1 (1 << 23) +#define FLASH_OPTR_DUALBANK (1 << 21) +#define FLASH_OPTR_BFB2 (1 << 20) +#define FLASH_OPTR_WWDG_SW (1 << 19) +#define FLASH_OPTR_IWDG_STDBY (1 << 18) +#define FLASH_OPTR_IWDG_STOP (1 << 17) +#define FLASH_OPTR_IDWG_SW (1 << 16) +#define FLASH_OPTR_nRST_SHDW (1 << 14) +#define FLASH_OPTR_nRST_STDBY (1 << 13) +#define FLASH_OPTR_nRST_STOP (1 << 12) + +#define FLASH_OPTR_BOR_SHIFT 8 +#define FLASH_OPTR_BOR_MASK 0x700 +#define FLASH_OPTR_BOR_LEVEL_0 0 +#define FLASH_OPTR_BOR_LEVEL_1 1 +#define FLASH_OPTR_BOR_LEVEL_2 2 +#define FLASH_OPTR_BOR_LEVEL_3 3 +#define FLASH_OPTR_BOR_LEVEL_4 4 + +#define FLASH_OPTR_RDP_SHIFT 0 +#define FLASH_OPTR_RDP_MASK 0xff +#define FLASH_OPTR_RDP_LEVEL_0 0xAA +#define FLASH_OPTR_RDP_LEVEL_1 0xBB +#define FLASH_OPTR_RDP_LEVEL_2 0xCC + +/* --- FLASH_PCROP1SR values -------------------------------------------------- */ + +#define FLASH_PCROP1SR_PCROP1_STRT_SHIFT 0 +#define FLASH_PCROP1SR_PCROP1_STRT_MASK 0xffff + +/* --- FLASH_PCROP1ER values -------------------------------------------------- */ + +#define FLASH_PCROP1ER_PCROP_RDP (1 << 31) +#define FLASH_PCROP1ER_PCROP1_END_SHIFT 0 +#define FLASH_PCROP1ER_PCROP1_END_MASK 0xffff + +/* --- FLASH_WRP1AR values -------------------------------------------------- */ + +#define FLASH_WRP1AR_WRP1A_END_SHIFT 16 +#define FLASH_WRP1AR_WRP1A_END_MASK 0xff + +#define FLASH_WRP1AR_WRP1A_STRT_SHIFT 0 +#define FLASH_WRP1AR_WRP1A_STRT_MASK 0xff + +/* --- FLASH_WRP1BR values -------------------------------------------------- */ + +#define FLASH_WRP1BR_WRP1B_END_SHIFT 16 +#define FLASH_WRP1BR_WRP1B_END_MASK 0xff + +#define FLASH_WRP1BR_WRP1B_STRT_SHIFT 0 +#define FLASH_WRP1BR_WRP1B_STRT_MASK 0xff + +/* --- FLASH_PCROP2SR values -------------------------------------------------- */ + +#define FLASH_PCROP2SR_PCROP2_STRT_SHIFT 0 +#define FLASH_PCROP2SR_PCROP2_STRT_MASK 0xffff + +/* --- FLASH_PCROP2ER values -------------------------------------------------- */ + +#define FLASH_PCROP2ER_PCROP2_END_SHIFT 0 +#define FLASH_PCROP2ER_PCROP2_END_MASK 0xffff + +/* --- FLASH_WRP2AR values -------------------------------------------------- */ + +#define FLASH_WRP2AR_WRP2A_END_SHIFT 16 +#define FLASH_WRP2AR_WRP2A_END_MASK 0xff + +#define FLASH_WRP2AR_WRP2A_STRT_SHIFT 0 +#define FLASH_WRP2AR_WRP2A_STRT_MASK 0xff + +/* --- FLASH_WRP2BR values -------------------------------------------------- */ + +#define FLASH_WRP2BR_WRP2B_END_SHIFT 16 +#define FLASH_WRP2BR_WRP2B_END_MASK 0xff + +#define FLASH_WRP2BR_WRP2B_STRT_SHIFT 0 +#define FLASH_WRP2BR_WRP2B_STRT_MASK 0xff + +/* --- FLASH Keys -----------------------------------------------------------*/ + +#define FLASH_PDKEYR_PDKEY1 ((uint32_t)0x04152637) +#define FLASH_PDKEYR_PDKEY2 ((uint32_t)0xfafbfcfd) + +#define FLASH_KEYR_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab) + +#define FLASH_OPTKEYR_KEY1 ((uint32_t)0x08192a3b) +#define FLASH_OPTKEYR_KEY2 ((uint32_t)0x4c5d6e7f) + +/* --- Function prototypes ------------------------------------------------- */ + +BEGIN_DECLS + +void flash_set_ws(uint32_t ws); +void flash_unlock(void); +void flash_lock(void); +void flash_clear_pgperr_flag(void); +void flash_clear_eop_flag(void); +void flash_clear_bsy_flag(void); +void flash_wait_for_last_operation(void); +void flash_dcache_enable(void); +void flash_dcache_disable(void); +void flash_icache_enable(void); +void flash_icache_disable(void); +void flash_prefetch_enable(void); +void flash_prefetch_disable(void); +void flash_dcache_reset(void); +void flash_icache_reset(void); +void flash_clear_pgserr_flag(void); +void flash_clear_pgaerr_flag(void); +void flash_clear_wrperr_flag(void); +void flash_clear_status_flags(void); +void flash_unlock_option_bytes(void); +void flash_lock_option_bytes(void); +void flash_program_word(uint32_t address, uint32_t data); +void flash_program(uint32_t address, uint8_t *data, uint32_t len); +void flash_erase_sector(uint8_t sector); +void flash_erase_all_sectors(void); +void flash_program_option_bytes(uint32_t data); + +END_DECLS + +#endif +/**@}*/ diff --git a/lib/stm32/l4/Makefile b/lib/stm32/l4/Makefile index 283ccb77..836bd8bc 100644 --- a/lib/stm32/l4/Makefile +++ b/lib/stm32/l4/Makefile @@ -37,7 +37,7 @@ TGT_CFLAGS += $(DEBUG_FLAGS) ARFLAGS = rcs # Specific objs -OBJS = adc.o pwr.o rcc.o +OBJS = adc.o flash.o pwr.o rcc.o # common/shared objs OBJS += rcc_common_all.o diff --git a/lib/stm32/l4/flash.c b/lib/stm32/l4/flash.c new file mode 100644 index 00000000..84d8c4cf --- /dev/null +++ b/lib/stm32/l4/flash.c @@ -0,0 +1,343 @@ +/** @defgroup flash_file FLASH + * + * @ingroup STM32L4xx + * + * @brief libopencm3 STM32L4xx FLASH + * + * @version 1.0.0 + * + * Benjamin Levine + * + * @date 12 February 2016 + * + * This library supports the FLASH memory controller in the STM32L4 + * series of ARM Cortex Microcontrollers by ST Microelectronics. + * + * For the STM32L4xx, accessing FLASH memory is described briefly in + * section 3 of the STM32L4x6 Reference Manual. + * + * LGPL License Terms @ref lgpl_license + */ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2016 Benjamin Levine + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ + +/**@{*/ + +#include + +/** @brief Enable the FLASH Prefetch Buffer + +This buffer is used for instruction fetches and is enabled by default after +reset. + +Note carefully the clock restrictions under which the prefetch buffer may be +enabled or disabled. Changes are normally made while the clock is running in +the power-on low frequency mode before being set to a higher speed mode. +See the reference manual for details. +*/ +void flash_prefetch_enable(void) +{ + FLASH_ACR |= FLASH_ACR_PRFTEN; +} + +/** @brief Disable the FLASH Prefetch Buffer + +Note carefully the clock restrictions under which the prefetch buffer may be +set to disabled. See the reference manual for details. +*/ +void flash_prefetch_disable(void) +{ + FLASH_ACR &= ~FLASH_ACR_PRFTEN; +} + +/** @brief Set the Number of Wait States + +Used to match the system clock to the FLASH memory access time. See the +programming manual for more information on clock speed ranges. The latency must +be changed to the appropriate value before any increase in clock +speed, or after any decrease in clock speed. + +@param[in] ws values from @ref flash_latency. +*/ +void flash_set_ws(uint32_t ws) +{ + uint32_t reg32; + + reg32 = FLASH_ACR; + reg32 &= ~(FLASH_ACR_LATENCY_MASK << FLASH_ACR_LATENCY_SHIFT); + reg32 |= (ws << FLASH_ACR_LATENCY_SHIFT); + FLASH_ACR = reg32; +} + +/** @brief Unlock the Flash Program and Erase Controller + * This enables write access to the Flash memory. It is locked by default on + * reset. + */ +void flash_unlock(void) +{ + /* Clear the unlock sequence state. */ + FLASH_CR |= FLASH_CR_LOCK; + + /* Authorize the FPEC access. */ + FLASH_KEYR = FLASH_KEYR_KEY1; + FLASH_KEYR = FLASH_KEYR_KEY2; +} + +/** @brief Lock the Flash Program and Erase Controller + * Used to prevent spurious writes to FLASH. + */ +void flash_lock(void) +{ + FLASH_CR |= FLASH_CR_LOCK; +} + +/** @brief Clear the Programming Error Status Flag + */ +void flash_clear_pgperr_flag(void) +{ + FLASH_SR |= FLASH_SR_PROGERR; +} + +/** @brief Clear the End of Operation Status Flag + */ +void flash_clear_eop_flag(void) +{ + FLASH_SR |= FLASH_SR_EOP; +} + +/** @brief Clear the Busy Status Flag + */ +void flash_clear_bsy_flag(void) +{ + FLASH_SR &= ~FLASH_SR_BSY; +} + + +/** @brief Wait until Last Operation has Ended + * This loops indefinitely until an operation (write or erase) has completed + * by testing the busy flag. + */ +void flash_wait_for_last_operation(void) +{ + while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY); +} + +/** @brief Enable the Data Cache + */ +void flash_dcache_enable(void) +{ + FLASH_ACR |= FLASH_ACR_DCEN; +} + +/** @brief Disable the Data Cache + */ +void flash_dcache_disable(void) +{ + FLASH_ACR &= ~FLASH_ACR_DCEN; +} + +/** @brief Enable the Instruction Cache + */ +void flash_icache_enable(void) +{ + FLASH_ACR |= FLASH_ACR_ICEN; +} + +/** @brief Disable the Instruction Cache + */ +void flash_icache_disable(void) +{ + FLASH_ACR &= ~FLASH_ACR_ICEN; +} + + +/** @brief Reset the Data Cache + * The data cache must be disabled for this to have effect. + */ +void flash_dcache_reset(void) +{ + FLASH_ACR |= FLASH_ACR_DCRST; +} + +/** @brief Reset the Instruction Cache + * The instruction cache must be disabled for this to have effect. + */ +void flash_icache_reset(void) +{ + FLASH_ACR |= FLASH_ACR_ICRST; +} + +/** @brief Clear the Programming Sequence Error Flag + * This flag is set when incorrect programming configuration has been made. + */ +void flash_clear_pgserr_flag(void) +{ + FLASH_SR |= FLASH_SR_PGSERR; +} + +/** @brief Clear the Programming Alignment Error Flag + */ +void flash_clear_pgaerr_flag(void) +{ + FLASH_SR |= FLASH_SR_PGAERR; +} + +/** @brief Clear the Write Protect Error Flag + */ +void flash_clear_wrperr_flag(void) +{ + FLASH_SR |= FLASH_SR_WRPERR; +} + +/** @brief Clear All Status Flags + * Program error, end of operation, write protect error, busy. + */ +void flash_clear_status_flags(void) +{ + flash_clear_pgserr_flag(); + flash_clear_pgaerr_flag(); + flash_clear_wrperr_flag(); + flash_clear_pgperr_flag(); + flash_clear_eop_flag(); + flash_clear_bsy_flag(); +} + +/** @brief Unlock the Option Byte Access + * This enables write access to the option bytes. It is locked by default on + * reset. + */ +void flash_unlock_option_bytes(void) +{ + /* Clear the unlock state. */ + FLASH_CR |= FLASH_CR_OPTLOCK; + + /* Unlock option bytes. */ + FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1; + FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2; +} + +/** @brief Lock the Option Byte Access + * This disables write access to the option bytes. It is locked by default on + * reset. + */ +void flash_lock_option_bytes(void) +{ + FLASH_CR |= FLASH_CR_OPTLOCK; +} + +/** @brief Program a 32 bit Word to FLASH + * This performs all operations necessary to program a 32 bit word to FLASH + * memory. The program error flag should be checked separately for the event + * that memory was not properly erased. + * + * @param[in] address Starting address in Flash. + * @param[in] data word to write + */ +void flash_program_word(uint32_t address, uint32_t data) +{ + /* Ensure that all flash operations are complete. */ + flash_wait_for_last_operation(); + + /* Enable writes to flash. */ + FLASH_CR |= FLASH_CR_PG; + + /* Program the word. */ + MMIO32(address) = data; + + /* Wait for the write to complete. */ + flash_wait_for_last_operation(); + + /* Disable writes to flash. */ + FLASH_CR &= ~FLASH_CR_PG; +} + +/** @brief Program a Data Block to FLASH + * This programs an arbitrary length data block to FLASH memory. + * The program error flag should be checked separately for the event that + * memory was not properly erased. + * @param[in] address Starting address in Flash. + * @param[in] data Pointer to start of data block. + * @param[in] len Length of data block. + */ +void flash_program(uint32_t address, uint8_t *data, uint32_t len) +{ + /* TODO: Use dword and word size program operations where possible for + * turbo speed. + */ + uint32_t i; + for (i = 0; i < len; i++) { + flash_program_word(address+i, data[i]); + } +} + +/** @brief Erase a Sector of FLASH + * This performs all operations necessary to erase a sector in FLASH memory. + * The page should be checked to ensure that it was properly erased. A sector + * must first be fully erased before attempting to program it. + * See the reference manual or the FLASH programming manual for details. + * @param[in] sector (0 - 11 for some parts, 0-23 on others) + */ +void flash_erase_sector(uint8_t sector) +{ + flash_wait_for_last_operation(); + + FLASH_CR &= ~(FLASH_CR_PNB_MASK << FLASH_CR_PNB_SHIFT); + FLASH_CR |= (sector & FLASH_CR_PNB_MASK) << FLASH_CR_PNB_SHIFT; + FLASH_CR |= FLASH_CR_PER; + FLASH_CR |= FLASH_CR_START; + + flash_wait_for_last_operation(); + FLASH_CR &= ~FLASH_CR_PER; + FLASH_CR &= ~(FLASH_CR_PNB_MASK << FLASH_CR_PNB_SHIFT); +} + +/** @brief Erase All FLASH + * This performs all operations necessary to erase all sectors in the FLASH + * memory. + */ +void flash_erase_all_sectors(void) +{ + flash_wait_for_last_operation(); + + FLASH_CR |= FLASH_CR_MER1 | FLASH_CR_MER2; + FLASH_CR |= FLASH_CR_START; + + flash_wait_for_last_operation(); + FLASH_CR &= ~FLASH_CR_MER1 & ~FLASH_CR_MER2; +} + +/** @brief Program the Option Bytes + * This performs all operations necessary to program the option bytes. + * The option bytes do not need to be erased first. + * @param[in] data value to be programmed. + */ +void flash_program_option_bytes(uint32_t data) +{ + flash_wait_for_last_operation(); + + if (FLASH_CR & FLASH_CR_OPTLOCK) { + flash_unlock_option_bytes(); + } + + FLASH_OPTR = data & ~0x3; + FLASH_OPTR |= FLASH_CR_OPTSTRT; + flash_wait_for_last_operation(); +} +/**@}*/ \ No newline at end of file