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Quiet adiv5 probe.

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This commit is contained in:
Gareth McMullin 2016-06-29 15:21:15 +12:00
parent 0480578391
commit 6b49fbe594
2 changed files with 12 additions and 11 deletions
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19
src/adiv5.c
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@ -277,8 +277,6 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr)
/* Extract Component ID class nibble */ /* Extract Component ID class nibble */
uint32_t cid_class = (cidr & CID_CLASS_MASK) >> CID_CLASS_SHIFT; uint32_t cid_class = (cidr & CID_CLASS_MASK) >> CID_CLASS_SHIFT;
DEBUG("0x%X: \"%s\"\n", addr, cidc_debug_strings[cid_class]);
if (cid_class == cidc_romtab) { /* ROM table, probe recursively */ if (cid_class == cidc_romtab) { /* ROM table, probe recursively */
for (int i = 0; i < 256; i++) { for (int i = 0; i < 256; i++) {
uint32_t entry = adiv5_mem_read32(ap, addr + i*4); uint32_t entry = adiv5_mem_read32(ap, addr + i*4);
@ -304,15 +302,18 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr)
/* Find the part number in our part list and run the appropriate probe /* Find the part number in our part list and run the appropriate probe
* routine if applicable. * routine if applicable.
*/ */
for (int i = 0; pidr_pn_bits[i].arch != aa_end; i++) { int i;
for (i = 0; pidr_pn_bits[i].arch != aa_end; i++) {
if (pidr_pn_bits[i].part_number == part_number) { if (pidr_pn_bits[i].part_number == part_number) {
DEBUG("0x%X: %s %s\n", addr, DEBUG("0x%X: %s - %s %s\n", addr,
cidc_debug_strings[cid_class],
pidr_pn_bits[i].type, pidr_pn_bits[i].type,
pidr_pn_bits[i].full); pidr_pn_bits[i].full);
/* Perform sanity check, if we know what to expect as component ID /* Perform sanity check, if we know what to expect as component ID
* class. * class.
*/ */
if (cid_class != pidr_pn_bits[i].cidc) { if ((pidr_pn_bits[i].cidc != cidc_unknown) &&
(cid_class != pidr_pn_bits[i].cidc)) {
DEBUG("WARNING: \"%s\" !match expected \"%s\"\n", DEBUG("WARNING: \"%s\" !match expected \"%s\"\n",
cidc_debug_strings[cid_class], cidc_debug_strings[cid_class],
cidc_debug_strings[pidr_pn_bits[i].cidc]); cidc_debug_strings[pidr_pn_bits[i].cidc]);
@ -327,11 +328,15 @@ static void adiv5_component_probe(ADIv5_AP_t *ap, uint32_t addr)
cortexa_probe(ap, addr); cortexa_probe(ap, addr);
break; break;
default: default:
DEBUG("-> skip\n"); break;
} }
break; break;
} }
} }
if (pidr_pn_bits[i].arch == aa_end) {
DEBUG("0x%X: %s - Unknown (PIDR = 0x%"PRIx64")\n", addr,
cidc_debug_strings[cid_class], pidr);
}
} }
} }
@ -372,7 +377,7 @@ ADIv5_AP_t *adiv5_new_ap(ADIv5_DP_t *dp, uint8_t apsel)
ap->csw &= ~ADIV5_AP_CSW_TRINPROG; ap->csw &= ~ADIV5_AP_CSW_TRINPROG;
} }
DEBUG("%3d: IDR=%08X CFG=%08X BASE=%08X CSW=%08X\n", DEBUG(" AP %3d: IDR=%08X CFG=%08X BASE=%08X CSW=%08X\n",
apsel, ap->idr, ap->cfg, ap->base, ap->csw); apsel, ap->idr, ap->cfg, ap->base, ap->csw);
return ap; return ap;

4
src/cortexa.c
View File

@ -360,9 +360,6 @@ bool cortexa_probe(ADIv5_AP_t *apb, uint32_t debug_base)
{ {
target *t; target *t;
DEBUG("%s base=0x%08"PRIx32"\n", __func__, debug_base);
/* Prepend to target list... */
t = target_new(sizeof(*t)); t = target_new(sizeof(*t));
adiv5_ap_ref(apb); adiv5_ap_ref(apb);
struct cortexa_priv *priv = calloc(1, sizeof(*priv)); struct cortexa_priv *priv = calloc(1, sizeof(*priv));
@ -391,7 +388,6 @@ bool cortexa_probe(ADIv5_AP_t *apb, uint32_t debug_base)
adiv5_ap_write(apb, ADIV5_AP_CSW, csw); adiv5_ap_write(apb, ADIV5_AP_CSW, csw);
uint32_t dbgdidr = apb_read(t, DBGDIDR); uint32_t dbgdidr = apb_read(t, DBGDIDR);
priv->hw_breakpoint_max = ((dbgdidr >> 24) & 15)+1; priv->hw_breakpoint_max = ((dbgdidr >> 24) & 15)+1;
DEBUG("Target has %d breakpoints\n", priv->hw_breakpoint_max);
t->check_error = cortexa_check_error; t->check_error = cortexa_check_error;