From 6eb846d356c5cee445e47972476e8d570cbe62d4 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Tue, 3 Nov 2015 23:43:06 +0000 Subject: [PATCH] stm32f3: adc: rationalize Sampling Time definitions. There are as many SMPRx registers are needed for channels supported, and on all other families, the field definitions are just ADC_SMPR_SMP_XXX. For consistency, and to avoid any confusion or duplication, use the same style here too. Drop silly unused per channel definitions that have no purpose. --- include/libopencm3/stm32/f3/adc.h | 44 +++++++------------------------ 1 file changed, 10 insertions(+), 34 deletions(-) diff --git a/include/libopencm3/stm32/f3/adc.h b/include/libopencm3/stm32/f3/adc.h index ac1e6c9e..f54b8d10 100644 --- a/include/libopencm3/stm32/f3/adc.h +++ b/include/libopencm3/stm32/f3/adc.h @@ -475,48 +475,24 @@ #define ADC_CFGR_DMAEN (1 << 0) -/*------- ADC_SMPR1 values ---------*/ -#define ADC_SMPR1_SMP8_LSB 24 -#define ADC_SMPR1_SMP7_LSB 21 -#define ADC_SMPR1_SMP6_LSB 18 -#define ADC_SMPR1_SMP5_LSB 15 -#define ADC_SMPR1_SMP4_LSB 12 -#define ADC_SMPR1_SMP3_LSB 9 -#define ADC_SMPR1_SMP2_LSB 6 -#define ADC_SMPR1_SMP1_LSB 3 -#define ADC_SMPR1_SMP8_MSK (0x7 << ADC_SMP8_LSB) -#define ADC_SMPR1_SMP7_MSK (0x7 << ADC_SMP7_LSB) -#define ADC_SMPR1_SMP6_MSK (0x7 << ADC_SMP6_LSB) -#define ADC_SMPR1_SMP5_MSK (0x7 << ADC_SMP5_LSB) -#define ADC_SMPR1_SMP4_MSK (0x7 << ADC_SMP4_LSB) -#define ADC_SMPR1_SMP3_MSK (0x7 << ADC_SMP3_LSB) -#define ADC_SMPR1_SMP2_MSK (0x7 << ADC_SMP2_LSB) -#define ADC_SMPR1_SMP1_MSK (0x7 << ADC_SMP1_LSB) /****************************************************************************/ -/* ADC_SMPR1 ADC Sample Time Selection for Channels */ -/** @defgroup adc_sample_r1 ADC Sample Time Selection for ADC1 +/* ADC_SMPRx ADC Sample Time Selection for Channels */ +/** @defgroup adc_sample ADC Sample Time Selection values @ingroup adc_defines @{*/ -#define ADC_SMPR1_SMP_1DOT5CYC 0x0 -#define ADC_SMPR1_SMP_2DOT5CYC 0x1 -#define ADC_SMPR1_SMP_4DOT5CYC 0x2 -#define ADC_SMPR1_SMP_7DOT5CYC 0x3 -#define ADC_SMPR1_SMP_19DOT5CYC 0x4 -#define ADC_SMPR1_SMP_61DOT5CYC 0x5 -#define ADC_SMPR1_SMP_181DOT5CYC 0x6 -#define ADC_SMPR1_SMP_601DOT5CYC 0x7 +#define ADC_SMPR_SMP_1DOT5CYC 0x0 +#define ADC_SMPR_SMP_2DOT5CYC 0x1 +#define ADC_SMPR_SMP_4DOT5CYC 0x2 +#define ADC_SMPR_SMP_7DOT5CYC 0x3 +#define ADC_SMPR_SMP_19DOT5CYC 0x4 +#define ADC_SMPR_SMP_61DOT5CYC 0x5 +#define ADC_SMPR_SMP_181DOT5CYC 0x6 +#define ADC_SMPR_SMP_601DOT5CYC 0x7 /**@}*/ /* SMPx[2:0]: Channel x sampling time selection */ - -/*------- ADC_SMPR2 values ---------*/ - -/* SMPx[2:0]: Channel x sampling time selection */ - - - /*------- ADC_TR1 values ---------*/ /* Bits 27:16 HT1[11:0]: Analog watchdog 1 higher threshold */