Added 12MHz external clock rcc setup routine.
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ef766da468
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7073637430
@ -24,7 +24,7 @@
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/* Set STM32 to 72 MHz. */
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void clock_setup(void)
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{
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rcc_clock_setup_in_hse_16mhz_out_72mhz();
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rcc_clock_setup_in_hse_12mhz_out_72mhz();
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/* Enable GPIOC clock. */
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rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPBEN);
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@ -531,6 +531,60 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
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}
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void rcc_clock_setup_in_hse_12mhz_out_72mhz(void)
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{
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/* Enable internal high-speed oscillator. */
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rcc_osc_on(HSI);
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rcc_wait_for_osc_ready(HSI);
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/* Select HSI as SYSCLK source. */
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSICLK);
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/* Enable external high-speed oscillator 16MHz. */
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rcc_osc_on(HSE);
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rcc_wait_for_osc_ready(HSE);
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_HSECLK);
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/*
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* Set prescalers for AHB, ADC, ABP1, ABP2.
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* Do this before touching the PLL (TODO: why?).
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*/
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rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Max. 72MHz */
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rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Max. 14MHz */
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rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Max. 36MHz */
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rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Max. 72MHz */
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/*
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* Sysclk runs with 72MHz -> 2 waitstates.
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* 0WS from 0-24MHz
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* 1WS from 24-48MHz
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* 2WS from 48-72MHz
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*/
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flash_set_ws(FLASH_LATENCY_2WS);
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/*
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* Set the PLL multiplication factor to 9.
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* 12MHz (external) * 6 (multiplier) / 1 (PLLXTPRE_HSE_CLK) = 72MHz
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*/
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rcc_set_pll_multiplication_factor(RCC_CFGR_PLLMUL_PLL_CLK_MUL6);
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/* Select HSI as PLL source. */
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rcc_set_pll_source(RCC_CFGR_PLLSRC_HSE_CLK);
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/*
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* Divide external frequency by 2 before entering PLL
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* (only valid/needed for HSE).
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*/
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rcc_set_pllxtpre(RCC_CFGR_PLLXTPRE_HSE_CLK);
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/* Enable PLL oscillator and wait for it to stabilize. */
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rcc_osc_on(PLL);
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rcc_wait_for_osc_ready(PLL);
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/* Select PLL as SYSCLK source. */
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rcc_set_sysclk_source(RCC_CFGR_SW_SYSCLKSEL_PLLCLK);
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}
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void rcc_clock_setup_in_hse_16mhz_out_72mhz(void)
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{
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/* Enable internal high-speed oscillator. */
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