atimer.csv

This commit is contained in:
Michael Ossmann 2012-09-29 21:37:01 -06:00 committed by Piotr Esden-Tempski
parent 299806bc4e
commit 7b0cc0c6a3

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ATIMER_DOWNCOUNTER,0,16,CVAL,When equal to zero an interrupt is raised,0,rw
ATIMER_PRESET,0,16,PRESETVAL,Value loaded in DOWNCOUNTER when DOWNCOUNTER equals zero,0,rw
ATIMER_CLR_EN,0,1,CLR_EN,Writing a 1 to this bit clears the interrupt enable bit in the ENABLE register,0,w
ATIMER_SET_EN,0,1,SET_EN,Writing a 1 to this bit sets the interrupt enable bit in the ENABLE register,0,w
ATIMER_STATUS,0,1,STAT,A 1 in this bit shows that the STATUS interrupt has been raised,0,r
ATIMER_ENABLE,0,1,ENA,A 1 in this bit shows that the STATUS interrupt has been enabled and that the STATUS interrupt request signal is asserted when STAT = 1 in the STATUS register,0,r
ATIMER_CLR_STAT,0,1,CSTAT,Writing a 1 to this bit clears the STATUS interrupt bit in the STATUS register,0,w
ATIMER_SET_STAT,0,1,SSTAT,Writing a 1 to this bit sets the STATUS interrupt bit in the STATUS register,0,w
1 ATIMER_DOWNCOUNTER 0 16 CVAL When equal to zero an interrupt is raised 0 rw
2 ATIMER_PRESET 0 16 PRESETVAL Value loaded in DOWNCOUNTER when DOWNCOUNTER equals zero 0 rw
3 ATIMER_CLR_EN 0 1 CLR_EN Writing a 1 to this bit clears the interrupt enable bit in the ENABLE register 0 w
4 ATIMER_SET_EN 0 1 SET_EN Writing a 1 to this bit sets the interrupt enable bit in the ENABLE register 0 w
5 ATIMER_STATUS 0 1 STAT A 1 in this bit shows that the STATUS interrupt has been raised 0 r
6 ATIMER_ENABLE 0 1 ENA A 1 in this bit shows that the STATUS interrupt has been enabled and that the STATUS interrupt request signal is asserted when STAT = 1 in the STATUS register 0 r
7 ATIMER_CLR_STAT 0 1 CSTAT Writing a 1 to this bit clears the STATUS interrupt bit in the STATUS register 0 w
8 ATIMER_SET_STAT 0 1 SSTAT Writing a 1 to this bit sets the STATUS interrupt bit in the STATUS register 0 w