Merge commit '8fb3b7b1a8d1cb2ac8b54204f452106939eb2ab7' into sam-update
# Conflicts: # src/target/adiv5_swdp.c
This commit is contained in:
commit
7bd7c3d0f5
@ -160,7 +160,6 @@ void gdb_putpacket2(const char *packet1, int size1,const char *packet2, int size
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{
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{
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int i;
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int i;
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unsigned char csum;
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unsigned char csum;
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unsigned char c;
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char xmit_csum[3];
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char xmit_csum[3];
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int tries = 0;
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int tries = 0;
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@ -185,7 +184,6 @@ void gdb_putpacket(const char *packet, int size)
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{
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{
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int i;
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int i;
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unsigned char csum;
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unsigned char csum;
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unsigned char c;
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char xmit_csum[3];
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char xmit_csum[3];
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int tries = 0;
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int tries = 0;
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@ -219,7 +217,6 @@ void gdb_putpacket_f(const char *fmt, ...)
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void gdb_out(const char *buf)
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void gdb_out(const char *buf)
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{
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{
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char *hexdata;
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char *hexdata;
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int i;
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int l=strlen(buf);
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int l=strlen(buf);
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hexdata = alloca(2*l+1);
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hexdata = alloca(2*l+1);
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@ -67,9 +67,8 @@ bool firmware_dp_low_write(ADIv5_DP_t *dp, uint16_t addr, const uint32_t data)
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*/
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*/
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int adiv5_swdp_scan(uint32_t targetid)
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int adiv5_swdp_scan(uint32_t targetid)
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{
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{
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volatile struct exception e;
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static bool scan_multidrop = true;
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static bool scan_multidrop = true;
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uint32_t idcode = 0;
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volatile uint32_t target_id;
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ADIv5_DP_t idp = {
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ADIv5_DP_t idp = {
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.dp_low_write = firmware_dp_low_write,
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.dp_low_write = firmware_dp_low_write,
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.error = firmware_swdp_error,
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.error = firmware_swdp_error,
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@ -93,11 +92,13 @@ int adiv5_swdp_scan(uint32_t targetid)
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* 0x1a Arm CoreSight SW-DP activation sequence
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* 0x1a Arm CoreSight SW-DP activation sequence
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* 20 bits start of reset another reset sequence*/
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* 20 bits start of reset another reset sequence*/
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initial_dp->seq_out(0x1a0, 12);
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initial_dp->seq_out(0x1a0, 12);
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uint32_t idcode = 0;
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volatile uint32_t target_id = 0;
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if (!targetid || !initial_dp->dp_low_write) {
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if (!targetid || !initial_dp->dp_low_write) {
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/* No targetID given on the command line or probe can not
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/* No targetID given on the command line or probe can not
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* handle multi-drop. Try to read ID */
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* handle multi-drop. Try to read ID */
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dp_line_reset(initial_dp);
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dp_line_reset(initial_dp);
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volatile struct exception e;
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TRY_CATCH (e, EXCEPTION_ALL) {
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TRY_CATCH (e, EXCEPTION_ALL) {
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idcode = initial_dp->dp_read(initial_dp, ADIV5_DP_IDCODE);
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idcode = initial_dp->dp_read(initial_dp, ADIV5_DP_IDCODE);
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}
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}
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@ -109,11 +110,11 @@ int adiv5_swdp_scan(uint32_t targetid)
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initial_dp->seq_out(0xE79E, 16); /* 0b0111100111100111 */
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initial_dp->seq_out(0xE79E, 16); /* 0b0111100111100111 */
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dp_line_reset(initial_dp);
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dp_line_reset(initial_dp);
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initial_dp->fault = 0;
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initial_dp->fault = 0;
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volatile struct exception e2;
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TRY_CATCH (e2, EXCEPTION_ALL) {
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TRY_CATCH (e, EXCEPTION_ALL) {
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idcode = initial_dp->dp_read(initial_dp, ADIV5_DP_IDCODE);
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idcode = initial_dp->dp_read(initial_dp, ADIV5_DP_IDCODE);
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}
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}
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if (e2.type || initial_dp->fault) {
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if (e.type || initial_dp->fault) {
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DEBUG_WARN("No usable DP found\n");
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DEBUG_WARN("No usable DP found\n");
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return -1;
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return -1;
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}
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}
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@ -150,7 +151,6 @@ int adiv5_swdp_scan(uint32_t targetid)
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dp_targetid = (i << 28) | (target_id & 0x0fffffff);
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dp_targetid = (i << 28) | (target_id & 0x0fffffff);
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initial_dp->dp_low_write(initial_dp, ADIV5_DP_TARGETSEL,
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initial_dp->dp_low_write(initial_dp, ADIV5_DP_TARGETSEL,
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dp_targetid);
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dp_targetid);
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volatile struct exception e;
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TRY_CATCH (e, EXCEPTION_ALL) {
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TRY_CATCH (e, EXCEPTION_ALL) {
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idcode = initial_dp->dp_read(initial_dp, ADIV5_DP_IDCODE);
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idcode = initial_dp->dp_read(initial_dp, ADIV5_DP_IDCODE);
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}
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}
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@ -252,8 +252,10 @@ uint32_t firmware_swdp_low_access(ADIv5_DP_t *dp, uint8_t RnW,
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raise_exception(EXCEPTION_ERROR, "SWDP invalid ACK");
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raise_exception(EXCEPTION_ERROR, "SWDP invalid ACK");
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if(RnW) {
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if(RnW) {
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if(dp->seq_in_parity(&response, 32)) /* Give up on parity error */
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if (dp->seq_in_parity(&response, 32)) { /* Give up on parity error */
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dp->fault = 1;
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raise_exception(EXCEPTION_ERROR, "SWDP Parity error");
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raise_exception(EXCEPTION_ERROR, "SWDP Parity error");
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}
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} else {
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} else {
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dp->seq_out_parity(value, 32);
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dp->seq_out_parity(value, 32);
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/* ARM Debug Interface Architecture Specification ADIv5.0 to ADIv5.2
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/* ARM Debug Interface Architecture Specification ADIv5.0 to ADIv5.2
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