Code changes to stm32f1 adc.c and adc.h
remove rcc_set_adc_clk - use rcc version Added functions: - adc_power_on - adc_start_conversion_direct - adc_set_dual_mode - adc_eoc - adc_eoc_injected - adc_read_regular - adc_read_injected - adc_set_injected_offset Tested dual mode scanned regular, but no tests of injected yet. Changes: "discontinuous" was misspelled. - adc_set_discontinuous_mode_regular - added "length" parameter - adc_disable_discontinuous_mode_regular - name change - adc_enable_discontinuous_mode_injected - name change - adc_enable_automatic_injected_group_conversion - disable triggers - adc_enable_jeoc_interrupt - name change to match common usage in lib - adc_disable_jeoc_interrupt - ditto - adc_enable_external_trigger_regular - remove incorrect test on parameter - adc_enable_external_trigger_injected - ditto - adc_set_sample_time - name change to match function's purpose - adc_set_conversion_time_on_all_channels - ditto - adc_set_injected_sequence - changed order of register loading (ref Barlow's issue) - adc_enable_analog_watchdog_on_all_channels - flipped AWDSGL - adc_enable_analog_watchdog_on_selected_channel - ditto added aliases for expected commonly used functions to avoid sudden user code breakage In adc.h, corrected errors in SQR names added "deprecated" compiler warnings to adc_on and to aliases defined in adc.c
This commit is contained in:
Ken Sarkies
parent
ecb0cbbf78
commit
7d0611609b
@ -3,6 +3,7 @@
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*
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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* Copyright (C) 2012 Piotr Esden-Tempski <piotr@esden.net>
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* Copyright (C) 2012 Ken Sarkies <ksarkies@internode.on.net>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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@ -71,14 +72,13 @@ void adc_setup(void)
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/* We configure everything for one single conversion. */
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adc_disable_scan_mode(ADC1);
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adc_set_single_conversion_mode(ADC1);
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adc_enable_discontinous_mode_regular(ADC1);
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adc_disable_external_trigger_regular(ADC1);
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adc_set_right_aligned(ADC1);
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/* We want to read the temperature sensor, so we have to enable it. */
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adc_enable_temperature_sensor(ADC1);
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adc_set_conversion_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC);
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adc_set_sample_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC);
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adc_on(ADC1);
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adc_power_on(ADC1);
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/* Wait for ADC starting up. */
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for (i = 0; i < 800000; i++) /* Wait a bit. */
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@ -138,10 +138,9 @@ int main(void)
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/* Continously convert and poll the temperature ADC. */
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while (1) {
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/*
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* If the ADC_CR2_ON bit is already set -> setting it another time
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* starts the conversion.
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* Start the conversion directly (ie without a trigger).
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*/
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adc_on(ADC1);
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adc_start_conversion_direct(ADC1);
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/* Wait for end of conversion. */
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while (!(ADC_SR(ADC1) & ADC_SR_EOC));
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@ -69,14 +69,13 @@ void adc_setup(void)
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/* We configure everything for one single conversion. */
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adc_disable_scan_mode(ADC1);
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adc_set_single_conversion_mode(ADC1);
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adc_enable_discontinous_mode_regular(ADC1);
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adc_disable_external_trigger_regular(ADC1);
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adc_set_right_aligned(ADC1);
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/* We want to read the temperature sensor, so we have to enable it. */
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adc_enable_temperature_sensor(ADC1);
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adc_set_conversion_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC);
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adc_set_sample_time_on_all_channels(ADC1, ADC_SMPR_SMP_28DOT5CYC);
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adc_on(ADC1);
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adc_power_on(ADC1);
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/* Wait for ADC starting up. */
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for (i = 0; i < 800000; i++) /* Wait a bit. */
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@ -131,10 +130,9 @@ int main(void)
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adc_set_regular_sequence(ADC1, 1, channel_array);
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/*
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* If the ADC_CR2_ON bit is already set -> setting it another time
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* starts the conversion.
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* Start the conversion directly (not trigger mode).
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*/
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adc_on(ADC1);
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adc_start_conversion_direct(ADC1);
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/* Wait for end of conversion. */
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while (!(ADC_SR(ADC1) & ADC_SR_EOC));
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@ -252,7 +252,7 @@ LGPL License Terms @ref lgpl_license
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#define ADC_CR1_DUALMOD_MASK (0xF << 16)
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#define ADC_CR1_DUALMOD_SHIFT 16
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/* DISCNUM[2:0]: Discontinous mode channel count. */
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/* DISCNUM[2:0]: Discontinuous mode channel count. */
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/****************************************************************************/
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/** @defgroup adc_cr1_discnum ADC Number of channels in discontinuous mode.
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@ingroup STM32F1xx_adc_defines
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@ -270,10 +270,10 @@ LGPL License Terms @ref lgpl_license
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#define ADC_CR1_DISCNUM_MASK (0x7 << 13)
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#define ADC_CR1_DISCNUM_SHIFT 13
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/* JDISCEN: */ /** Discontinous mode on injected channels. */
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/* JDISCEN: */ /** Discontinuous mode on injected channels. */
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#define ADC_CR1_JDISCEN (1 << 12)
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/* DISCEN: */ /** Discontinous mode on regular channels. */
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/* DISCEN: */ /** Discontinuous mode on regular channels. */
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#define ADC_CR1_DISCEN (1 << 11)
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/* JAUTO: */ /** Automatic Injection Group conversion. */
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@ -557,7 +557,7 @@ LGPL License Terms @ref lgpl_license
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/* --- ADC_SMPRx generic values -------------------------------------------- */
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/****************************************************************************/
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/* ADC_SMPRG ADC Sample Time Selection for Channels */
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/** @defgroup adc_sample_rg ADC Sample Time Selection Generic
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/** @defgroup adc_sample_rg ADC Sample Time Selection for All Channels
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@ingroup STM32F1xx_adc_defines
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@{*/
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@ -587,18 +587,11 @@ LGPL License Terms @ref lgpl_license
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#define ADC_SQR1_SQ15_LSB 10
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#define ADC_SQR1_SQ14_LSB 5
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#define ADC_SQR1_SQ13_LSB 0
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#define ADC_SQR1_L_MSK (0xf << ADC_L_LSB)
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#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQ16_LSB)
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#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQ15_LSB)
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#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQ14_LSB)
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#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQ13_LSB)
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/* TODO Fix error
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#define ADC_SQR1_L_MSK (0xf << ADC_SQR1_L_LSB)
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#define ADC_SQR1_SQ16_MSK (0x1f << ADC_SQR1_SQ16_LSB)
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#define ADC_SQR1_SQ15_MSK (0x1f << ADC_SQR1_SQ15_LSB)
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#define ADC_SQR1_SQ14_MSK (0x1f << ADC_SQR1_SQ14_LSB)
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#define ADC_SQR1_SQ13_MSK (0x1f << ADC_SQR1_SQ13_LSB)
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*/
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/* --- ADC_SQR2 values ----------------------------------------------------- */
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@ -608,20 +601,12 @@ LGPL License Terms @ref lgpl_license
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#define ADC_SQR2_SQ9_LSB 10
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#define ADC_SQR2_SQ8_LSB 5
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#define ADC_SQR2_SQ7_LSB 0
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#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQ12_LSB)
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#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQ11_LSB)
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#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQ10_LSB)
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#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQ9_LSB)
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#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQ8_LSB)
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#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQ7_LSB)
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/* TODO Fix error
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#define ADC_SQR2_SQ12_MSK (0x1f << ADC_SQR2_SQ12_LSB)
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#define ADC_SQR2_SQ11_MSK (0x1f << ADC_SQR2_SQ11_LSB)
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#define ADC_SQR2_SQ10_MSK (0x1f << ADC_SQR2_SQ10_LSB)
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#define ADC_SQR2_SQ9_MSK (0x1f << ADC_SQR2_SQ9_LSB)
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#define ADC_SQR2_SQ8_MSK (0x1f << ADC_SQR2_SQ8_LSB)
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#define ADC_SQR2_SQ7_MSK (0x1f << ADC_SQR2_SQ7_LSB)
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*/
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/* --- ADC_SQR3 values ----------------------------------------------------- */
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@ -631,20 +616,12 @@ LGPL License Terms @ref lgpl_license
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#define ADC_SQR3_SQ3_LSB 10
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#define ADC_SQR3_SQ2_LSB 5
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#define ADC_SQR3_SQ1_LSB 0
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#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQ6_LSB)
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#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQ5_LSB)
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#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQ4_LSB)
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#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQ3_LSB)
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#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQ2_LSB)
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#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQ1_LSB)
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/* TODO Fix error
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#define ADC_SQR3_SQ6_MSK (0x1f << ADC_SQR3_SQ6_LSB)
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#define ADC_SQR3_SQ5_MSK (0x1f << ADC_SQR3_SQ5_LSB)
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#define ADC_SQR3_SQ4_MSK (0x1f << ADC_SQR3_SQ4_LSB)
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#define ADC_SQR3_SQ3_MSK (0x1f << ADC_SQR3_SQ3_LSB)
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#define ADC_SQR3_SQ2_MSK (0x1f << ADC_SQR3_SQ2_LSB)
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#define ADC_SQR3_SQ1_MSK (0x1f << ADC_SQR3_SQ1_LSB)
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*/
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/* --- ADC_JSQR values ----------------------------------------------------- */
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#define ADC_JSQR_JL_LSB 20
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@ -652,18 +629,24 @@ LGPL License Terms @ref lgpl_license
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#define ADC_JSQR_JSQ3_LSB 10
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#define ADC_JSQR_JSQ2_LSB 5
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#define ADC_JSQR_JSQ1_LSB 0
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#define ADC_JSQR_JL_MSK (0x2 << ADC_JL_LSB)
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#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQ4_LSB)
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#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQ3_LSB)
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#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQ2_LSB)
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#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQ1_LSB)
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/* TODO Fix error
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/* JL[2:0]: Discontinous mode channel count injected channels. */
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/****************************************************************************/
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/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode fro injected channels.
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@ingroup STM32F1xx_adc_defines
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@{*/
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#define ADC_JSQR_JL_1CHANNELS (0x0 << ADC_JSQR_JL_LSB)
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#define ADC_JSQR_JL_2CHANNELS (0x1 << ADC_JSQR_JL_LSB)
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#define ADC_JSQR_JL_3CHANNELS (0x2 << ADC_JSQR_JL_LSB)
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#define ADC_JSQR_JL_4CHANNELS (0x3 << ADC_JSQR_JL_LSB)
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/**@}*/
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#define ADC_JSQR_JL_SHIFT 13
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#define ADC_JSQR_JL_MSK (0x2 << ADC_JSQR_JL_LSB)
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#define ADC_JSQR_JSQ4_MSK (0x1f << ADC_JSQR_JSQ4_LSB)
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#define ADC_JSQR_JSQ3_MSK (0x1f << ADC_JSQR_JSQ3_LSB)
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#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB)
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#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB)
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*/
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/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */
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@ -679,22 +662,31 @@ LGPL License Terms @ref lgpl_license
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BEGIN_DECLS
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void adc_power_on(u32 adc);
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void adc_start_conversion_direct(u32 adc);
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void adc_set_single_channel(u32 adc, u8 channel);
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void adc_set_dual_mode(u32 mode);
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bool adc_eoc(u32 adc);
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bool adc_eoc_injected(u32 adc);
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u32 adc_read_regular(u32 adc);
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u32 adc_read_injected(u32 adc, u8 reg);
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void adc_set_injected_offset(u32 adc, u8 reg, u32 offset);
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void adc_enable_analog_watchdog_regular(u32 adc);
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void adc_disable_analog_watchdog_regular(u32 adc);
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void adc_enable_analog_watchdog_injected(u32 adc);
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void adc_disable_analog_watchdog_injected(u32 adc);
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void adc_enable_discontinous_mode_regular(u32 adc);
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void adc_disable_discontinous_mode_regular(u32 adc);
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void adc_enable_discontinous_mode_injected(u32 adc);
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void adc_disable_discontinous_mode_injected(u32 adc);
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void adc_enable_discontinuous_mode_regular(u32 adc, u8 length);
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void adc_disable_discontinuous_mode_regular(u32 adc);
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void adc_enable_discontinuous_mode_injected(u32 adc);
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void adc_disable_discontinuous_mode_injected(u32 adc);
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void adc_enable_automatic_injected_group_conversion(u32 adc);
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void adc_disable_automatic_injected_group_conversion(u32 adc);
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void adc_enable_analog_watchdog_on_all_channels(u32 adc);
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void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel);
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void adc_enable_scan_mode(u32 adc);
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void adc_disable_scan_mode(u32 adc);
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void adc_enable_jeoc_interrupt(u32 adc);
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void adc_disable_jeoc_interrupt(u32 adc);
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void adc_enable_eoc_interrupt_injected(u32 adc);
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void adc_disable_eoc_interrupt_injected(u32 adc);
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void adc_enable_awd_interrupt(u32 adc);
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void adc_disable_awd_interrupt(u32 adc);
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void adc_enable_eoc_interrupt(u32 adc);
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@ -713,17 +705,28 @@ void adc_enable_dma(u32 adc);
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void adc_disable_dma(u32 adc);
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void adc_reset_calibration(u32 adc);
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void adc_calibration(u32 adc);
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void adc_set_continous_conversion_mode(u32 adc);
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void adc_set_continuous_conversion_mode(u32 adc);
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void adc_set_single_conversion_mode(u32 adc);
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#ifdef __GNUC__
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void adc_on(u32 adc) __attribute__ ((deprecated ("will be removed in the first release")));
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#else
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void adc_on(u32 adc);
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#endif
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void adc_off(u32 adc);
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void adc_set_conversion_time(u32 adc, u8 channel, u8 time);
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void adc_set_conversion_time_on_all_channels(u32 adc, u8 time);
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void adc_set_sample_time(u32 adc, u8 channel, u8 time);
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void adc_set_sample_time_on_all_channels(u32 adc, u8 time);
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void adc_set_watchdog_high_threshold(u32 adc, u16 threshold);
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void adc_set_watchdog_low_threshold(u32 adc, u16 threshold);
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void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]);
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void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]);
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#ifdef __GNUC__
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void adc_set_continous_conversion_mode(u32 adc) __attribute__ ((deprecated ("change to adc_set_continuous_conversion_mode")));
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void adc_set_conversion_time(u32 adc, u8 channel, u8 time) __attribute__ ((deprecated ("change to adc_set_sample_time")));
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void adc_set_conversion_time_on_all_channels(u32 adc, u8 time) __attribute__ ((deprecated ("change to adc_set_sample_time_on_all_channels")));
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void adc_enable_jeoc_interrupt(u32 adc) __attribute__ ((deprecated ("change to adc_enable_eoc_interrupt_injected")));
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void adc_disable_jeoc_interrupt(u32 adc) __attribute__ ((deprecated ("change to adc_disable_eoc_interrupt_injected")));
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#endif
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END_DECLS
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#endif
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@ -102,38 +102,156 @@ LGPL License Terms @ref lgpl_license
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#include <libopencm3/stm32/f1/adc.h>
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void rcc_set_adc_clk(u32 prescaler)
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/*-----------------------------------------------------------------------------*/
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/** @brief ADC Power On
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If the ADC is in power-down mode then it is powered up. The application needs
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to wait a time of about 3 microseconds for stabilization before using the ADC.
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If the ADC is already on this function call has no effect.
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@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
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*/
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void adc_power_on(u32 adc)
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{
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/* TODO */
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/* FIXME: QUICK HACK to prevent compiler warnings. */
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prescaler = prescaler;
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}
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void adc_set_mode(u32 block, /* TODO */ u8 mode)
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{
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/* TODO */
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/* FIXME: QUICK HACK to prevent compiler warnings. */
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block = block;
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mode = mode;
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if (!(ADC_CR2(adc) & ADC_CR2_ADON))
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ADC_CR2(adc) |= ADC_CR2_ADON;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief ADC Read from a Conversion Result Register
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/** @brief ADC Start a Conversion Without Trigger
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This initiates a conversion by software without a trigger. The ADC needs to be
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powered on before this is called, otherwise this function has no effect.
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Note that this is not available in other STM32F families. To ensure code compatibility,
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enable triggering and use a software trigger source @see adc_start_conversion_regular.
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@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
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*/
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void adc_start_conversion_direct(u32 adc)
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{
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if (ADC_CR2(adc) & ADC_CR2_ADON)
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ADC_CR2(adc) |= ADC_CR2_ADON;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief ADC Set Dual A/D Mode
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The dual mode uses ADC1 as master and ADC2 in a slave arrangement. This setting
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is applied to ADC1 only. Start of conversion when triggered can cause simultaneous
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conversion with ADC2, or alternate conversion. Regular and injected conversions
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can be configured, each one being separately simultaneous or alternate.
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@param[in] mode Unsigned int32. Dual mode selection from @ref adc_cr1_dualmod
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*/
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void adc_set_dual_mode(u32 mode)
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{
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ADC1_CR1 |= mode;
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}
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/*-----------------------------------------------------------------------------*/
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/** @brief ADC Read the End-of-Conversion Flag
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This flag is set after all channels of a regular or injected group have been
|
||||
converted.
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
@returns bool. End of conversion flag.
|
||||
*/
|
||||
|
||||
bool adc_eoc(u32 adc)
|
||||
{
|
||||
return ((ADC_SR(adc) & ADC_SR_EOC) != 0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief ADC Read the End-of-Conversion Flag for Injected Conversion
|
||||
|
||||
This flag is set after all channels of an injected group have been converted.
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
@returns bool. End of conversion flag.
|
||||
*/
|
||||
|
||||
bool adc_eoc_injected(u32 adc)
|
||||
{
|
||||
return ((ADC_SR(adc) & ADC_SR_JEOC) != 0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief ADC Read from the Regular Conversion Result Register
|
||||
|
||||
The result read back is 12 bits, right or left aligned within the first 16 bits.
|
||||
For ADC1 only, the higher 16 bits will hold the result from ADC2 if
|
||||
an appropriate dual mode has been set @see adc_set_dual_mode.
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
@returns Unsigned int32 conversion result.
|
||||
*/
|
||||
|
||||
u32 adc_read_regular(u32 adc)
|
||||
{
|
||||
return ADC_DR(adc);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief ADC Read from an Injected Conversion Result Register
|
||||
|
||||
The result read back from the selected injected result register (one of four) is
|
||||
12 bits, right or left aligned within the first 16 bits. The result can have a
|
||||
negative value if the injected channel offset has been set @see adc_set_injected_offset.
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
@param[in] reg Unsigned int8. Register number (1 ... 4).
|
||||
@returns Unsigned int32 conversion result.
|
||||
*/
|
||||
|
||||
void adc_read(u32 block, u32 channel)
|
||||
u32 adc_read_injected(u32 adc, u8 reg)
|
||||
{
|
||||
/* TODO */
|
||||
switch (reg) {
|
||||
case 1:
|
||||
return ADC_JDR1(adc);
|
||||
case 2:
|
||||
return ADC_JDR2(adc);
|
||||
case 3:
|
||||
return ADC_JDR3(adc);
|
||||
case 4:
|
||||
return ADC_JDR4(adc);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* FIXME: QUICK HACK to prevent compiler warnings. */
|
||||
block = block;
|
||||
channel = channel;
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief ADC Set the Injected Channel Data Offset
|
||||
|
||||
This value is subtracted from the injected channel results after conversion
|
||||
is complete, and can result in negative results. A separate value can be specified
|
||||
for each injected data register.
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
@param[in] reg Unsigned int8. Register number (1 ... 4).
|
||||
@param[in] offset Unsigned int32.
|
||||
*/
|
||||
|
||||
void adc_set_injected_offset(u32 adc, u8 reg, u32 offset)
|
||||
{
|
||||
switch (reg) {
|
||||
case 1:
|
||||
ADC_JOFR1(adc) = offset;
|
||||
break;
|
||||
case 2:
|
||||
ADC_JOFR2(adc) = offset;
|
||||
break;
|
||||
case 3:
|
||||
ADC_JOFR3(adc) = offset;
|
||||
break;
|
||||
case 4:
|
||||
ADC_JOFR4(adc) = offset;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
@ -203,9 +321,11 @@ of the subgroup at the beginning of the whole group.
|
||||
@param[in] length Unsigned int8. Number of channels in the group @ref adc_cr1_discnum
|
||||
*/
|
||||
|
||||
void adc_enable_discontinous_mode_regular(u32 adc)
|
||||
void adc_enable_discontinuous_mode_regular(u32 adc, u8 length)
|
||||
{
|
||||
ADC_CR1(adc) |= ADC_CR1_DISCEN;
|
||||
if ( (length-1) > 7 ) return;
|
||||
ADC_CR1(adc) |= ADC_CR1_DISCEN;
|
||||
ADC_CR2(adc) |= ((length-1) << ADC_CR1_DISCNUM_SHIFT);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
@ -214,7 +334,7 @@ void adc_enable_discontinous_mode_regular(u32 adc)
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_disable_discontinous_mode_regular(u32 adc)
|
||||
void adc_disable_discontinuous_mode_regular(u32 adc)
|
||||
{
|
||||
ADC_CR1(adc) &= ~ADC_CR1_DISCEN;
|
||||
}
|
||||
@ -229,7 +349,7 @@ entire group has been converted.
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_enable_discontinous_mode_injected(u32 adc)
|
||||
void adc_enable_discontinuous_mode_injected(u32 adc)
|
||||
{
|
||||
ADC_CR1(adc) |= ADC_CR1_JDISCEN;
|
||||
}
|
||||
@ -240,7 +360,7 @@ void adc_enable_discontinous_mode_injected(u32 adc)
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_disable_discontinous_mode_injected(u32 adc)
|
||||
void adc_disable_discontinuous_mode_injected(u32 adc)
|
||||
{
|
||||
ADC_CR1(adc) &= ~ADC_CR1_JDISCEN;
|
||||
}
|
||||
@ -257,6 +377,7 @@ channels is disabled as required.
|
||||
|
||||
void adc_enable_automatic_injected_group_conversion(u32 adc)
|
||||
{
|
||||
adc_disable_external_trigger_injected(adc);
|
||||
ADC_CR1(adc) |= ADC_CR1_JAUTO;
|
||||
}
|
||||
|
||||
@ -288,7 +409,7 @@ disabled.
|
||||
|
||||
void adc_enable_analog_watchdog_on_all_channels(u32 adc)
|
||||
{
|
||||
ADC_CR1(adc) |= ADC_CR1_AWDSGL;
|
||||
ADC_CR1(adc) &= ~ADC_CR1_AWDSGL;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
@ -315,7 +436,7 @@ void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel)
|
||||
if (channel < 18)
|
||||
reg32 |= channel;
|
||||
ADC_CR1(adc) = reg32;
|
||||
ADC_CR1(adc) &= ~ADC_CR1_AWDSGL;
|
||||
ADC_CR1(adc) |= ADC_CR1_AWDSGL;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
@ -350,7 +471,7 @@ void adc_disable_scan_mode(u32 adc)
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_enable_jeoc_interrupt(u32 adc)
|
||||
void adc_enable_eoc_interrupt_injected(u32 adc)
|
||||
{
|
||||
ADC_CR1(adc) |= ADC_CR1_JEOCIE;
|
||||
}
|
||||
@ -361,7 +482,7 @@ void adc_enable_jeoc_interrupt(u32 adc)
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_disable_jeoc_interrupt(u32 adc)
|
||||
void adc_disable_eoc_interrupt_injected(u32 adc)
|
||||
{
|
||||
ADC_CR1(adc) &= ~ADC_CR1_JEOCIE;
|
||||
}
|
||||
@ -519,8 +640,7 @@ void adc_enable_external_trigger_regular(u32 adc, u32 trigger)
|
||||
u32 reg32;
|
||||
|
||||
reg32 = (ADC_CR2(adc) & ~(ADC_CR2_EXTSEL_MASK));
|
||||
if (trigger < 8)
|
||||
reg32 |= (trigger);
|
||||
reg32 |= (trigger);
|
||||
ADC_CR2(adc) = reg32;
|
||||
ADC_CR2(adc) |= ADC_CR2_EXTTRIG;
|
||||
}
|
||||
@ -565,14 +685,12 @@ For ADC3
|
||||
@param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_injected_12
|
||||
for ADC1 and ADC2, or @ref adc_trigger_injected_3 for ADC3
|
||||
*/
|
||||
|
||||
void adc_enable_external_trigger_injected(u32 adc, u32 trigger)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
reg32 = (ADC_CR2(adc) & ~(ADC_CR2_JEXTSEL_MASK)); /* Clear bits [12:14]. */
|
||||
if (trigger < 8)
|
||||
reg32 |= (trigger);
|
||||
reg32 |= (trigger);
|
||||
ADC_CR2(adc) = reg32;
|
||||
ADC_CR2(adc) |= ADC_CR2_JEXTTRIG;
|
||||
}
|
||||
@ -681,7 +799,7 @@ group immediately following completion of the previous channel group conversion.
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
|
||||
void adc_set_continous_conversion_mode(u32 adc)
|
||||
void adc_set_continuous_conversion_mode(u32 adc)
|
||||
{
|
||||
ADC_CR2(adc) |= ADC_CR2_CONT;
|
||||
}
|
||||
@ -707,7 +825,7 @@ If the ADC is in power-down mode then it is powered up. The application needs
|
||||
to wait a time of about 3 microseconds for stabilization before using the ADC.
|
||||
If the ADC is already on this function call will initiate a conversion.
|
||||
|
||||
@todo fix this.
|
||||
@deprecated to be removed in a later release
|
||||
|
||||
@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base
|
||||
*/
|
||||
@ -740,7 +858,7 @@ The sampling time can be selected in ADC clock cycles from 1.5 to 239.5.
|
||||
@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg
|
||||
*/
|
||||
|
||||
void adc_set_conversion_time(u32 adc, u8 channel, u8 time)
|
||||
void adc_set_sample_time(u32 adc, u8 channel, u8 time)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
@ -767,7 +885,7 @@ all channels.
|
||||
@param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg
|
||||
*/
|
||||
|
||||
void adc_set_conversion_time_on_all_channels(u32 adc, u8 time)
|
||||
void adc_set_sample_time_on_all_channels(u32 adc, u8 time)
|
||||
{
|
||||
u8 i;
|
||||
u32 reg32 = 0;
|
||||
@ -871,12 +989,24 @@ void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[])
|
||||
return;
|
||||
|
||||
for (i = 1; i <= length; i++)
|
||||
reg32 |= (channel[i - 1] << ((i - 1) * 5));
|
||||
reg32 |= (channel[4 - i] << ((4 - i) * 5));
|
||||
|
||||
reg32 |= ((length - 1) << ADC_JSQR_JL_LSB);
|
||||
|
||||
ADC_JSQR(adc) = reg32;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
|
||||
/* Aliases */
|
||||
|
||||
#ifdef __GNUC__
|
||||
void adc_set_continous_conversion_mode(u32 adc) __attribute__ ((alias("adc_set_continuous_conversion_mode")));
|
||||
void adc_set_conversion_time(u32 adc, u8 channel, u8 time) __attribute__ ((alias ("adc_set_sample_time")));
|
||||
void adc_set_conversion_time_on_all_channels(u32 adc, u8 time) __attribute__ ((alias ("adc_set_sample_time_on_all_channels")));
|
||||
void adc_enable_jeoc_interrupt(u32 adc) __attribute__ ((alias ("adc_enable_eoc_interrupt_injected")));
|
||||
void adc_disable_jeoc_interrupt(u32 adc) __attribute__ ((alias ("adc_disable_eoc_interrupt_injected")));
|
||||
#endif
|
||||
|
||||
/**@}*/
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user