diff --git a/Makefile b/Makefile index ceef9652..45f2ef27 100644 --- a/Makefile +++ b/Makefile @@ -21,7 +21,7 @@ PREFIX ?= arm-none-eabi #PREFIX ?= arm-elf STYLECHECK := scripts/checkpatch.pl -STYLECHECKFLAGS := --no-tree -f +STYLECHECKFLAGS := --no-tree -f --terse --mailback ifeq ($(DETECT_TOOLCHAIN),) DESTDIR ?= /usr/local @@ -102,7 +102,7 @@ clean: cleanheaders stylecheck: $(Q)for i in `find . -name '*.[ch]'` ; do \ if ! grep -q "* It was generated by the irq2nvic_h script." $$i ; then \ - $(STYLECHECK) $(STYLECHECKFLAGS) $$i || exit $?; \ + $(STYLECHECK) $(STYLECHECKFLAGS) $$i; \ fi ; \ done diff --git a/include/libopencm3/cm3/assert.h b/include/libopencm3/cm3/assert.h index 0ccb0f72..f1aabc3c 100644 --- a/include/libopencm3/cm3/assert.h +++ b/include/libopencm3/cm3/assert.h @@ -49,25 +49,26 @@ LGPL License Terms @ref lgpl_license #include -#define CM3_LIKELY(expr) (__builtin_expect (!!(expr), 1)) +#define CM3_LIKELY(expr) (__builtin_expect(!!(expr), 1)) #ifdef NDEBUG -# define cm3_assert(expr) do { (void)0; } while(0) -# define cm3_assert_not_reached() while(1) +# define cm3_assert(expr) (void)0 +# define cm3_assert_not_reached() do { } while (1) #else # ifdef CM3_ASSERT_VERBOSE # define cm3_assert(expr) do { \ - if(CM3_LIKELY(expr)) { (void)0; } else { \ + if (CM3_LIKELY(expr)) { \ + (void)0; \ + } else { \ cm3_assert_failed_verbose( \ __FILE__, __LINE__, \ __func__, #expr); \ } \ - } while(0) -# define cm3_assert_not_reached() do { \ - cm3_assert_failed_verbose( \ - __FILE__, __LINE__, \ - __func__, 0); \ - } while(0) + } while (0) +# define cm3_assert_not_reached() \ + cm3_assert_failed_verbose( \ + __FILE__, __LINE__, \ + __func__, 0) # else /** @brief Check if assertion is true. * @@ -82,10 +83,12 @@ LGPL License Terms @ref lgpl_license * * @param expr expression to check */ # define cm3_assert(expr) do { \ - if(CM3_LIKELY(expr)) { (void)0; } else { \ + if (CM3_LIKELY(expr)) { \ + (void)0; \ + } else { \ cm3_assert_failed(); \ } \ - } while(0) + } while (0) /** @brief Check if unreachable code is reached. * * If NDEBUG macro is defined, this macro generates code for an infinite loop. @@ -95,9 +98,7 @@ LGPL License Terms @ref lgpl_license * The purpose of this macro is to aid in debugging libopencm3 and * applications using it. It can be used for example to stop execution if an * unreachable portion of code is reached. */ -# define cm3_assert_not_reached() do { \ - cm3_assert_failed(); \ - } while(0) +# define cm3_assert_not_reached() cm3_assert_failed() # endif #endif @@ -111,7 +112,7 @@ BEGIN_DECLS * implementation. Usually, a custom implementation of this function should * report an error in some way (print a message to a debug console, display, * LED, ...) and halt execution or reboot the device. */ -void cm3_assert_failed(void) __attribute__ ((__noreturn__)); +void cm3_assert_failed(void) __attribute__((__noreturn__)); /** @brief Called on a failed assertion with verbose messages enabled. * @@ -127,7 +128,7 @@ void cm3_assert_failed(void) __attribute__ ((__noreturn__)); * @param func Name of the function where the failed assertion occurred * @param assert_expr Expression that evaluated to false (can be NULL) */ void cm3_assert_failed_verbose(const char *file, int line, const char *func, - const char *assert_expr) __attribute__ ((__noreturn__)); + const char *assert_expr) __attribute__((__noreturn__)); END_DECLS diff --git a/include/libopencm3/cm3/common.h b/include/libopencm3/cm3/common.h index 20a5dde7..818452be 100644 --- a/include/libopencm3/cm3/common.h +++ b/include/libopencm3/cm3/common.h @@ -46,9 +46,9 @@ typedef uint64_t u64; #ifdef __GNUC__ # if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ > 4) -# define LIBOPENCM3_DEPRECATED(x) __attribute__ ((deprecated (x))) +# define LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated(x))) # else -# define LIBOPENCM3_DEPRECATED(x) __attribute__ ((deprecated)) +# define LIBOPENCM3_DEPRECATED(x) __attribute__((deprecated)) # endif #else # define LIBOPENCM3_DEPRECATED(x) @@ -95,4 +95,7 @@ typedef uint64_t u64; #define BIT30 (1<<30) #define BIT31 (1<<31) +#define __packed __attribute__((packed)) +#define __aligned(x) __attribute__((aligned(x))) + #endif diff --git a/include/libopencm3/cm3/nvic.h b/include/libopencm3/cm3/nvic.h index fe68a11e..6014b604 100644 --- a/include/libopencm3/cm3/nvic.h +++ b/include/libopencm3/cm3/nvic.h @@ -44,37 +44,43 @@ LGPL License Terms @ref lgpl_license /* ISER: Interrupt Set Enable Registers */ /* Note: 8 32bit Registers */ -#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + (iser_id * 4)) +#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + \ + (iser_id * 4)) /* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */ /* ICER: Interrupt Clear Enable Registers */ /* Note: 8 32bit Registers */ -#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + (icer_id * 4)) +#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + \ + (icer_id * 4)) /* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */ /* ISPR: Interrupt Set Pending Registers */ /* Note: 8 32bit Registers */ -#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + (ispr_id * 4)) +#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + \ + (ispr_id * 4)) /* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */ /* ICPR: Interrupt Clear Pending Registers */ /* Note: 8 32bit Registers */ -#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + (icpr_id * 4)) +#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + \ + (icpr_id * 4)) /* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */ /* IABR: Interrupt Active Bit Register */ /* Note: 8 32bit Registers */ -#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + (iabr_id * 4)) +#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + \ + (iabr_id * 4)) /* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */ /* IPR: Interrupt Priority Registers */ /* Note: 240 8bit Registers */ -#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + ipr_id) +#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + \ + ipr_id) /* STIR: Software Trigger Interrupt Register */ #define NVIC_STIR MMIO32(STIR_BASE) @@ -104,12 +110,12 @@ IRQ numbers -3 and -6 to -9 are reserved * specific header file in the corresponding subfolder. */ +#define WEAK __attribute__((weak)) + #include /* --- NVIC functions ------------------------------------------------------ */ -#define WEAK __attribute__ ((weak)) - BEGIN_DECLS void nvic_enable_irq(u8 irqn); diff --git a/include/libopencm3/cm3/scb.h b/include/libopencm3/cm3/scb.h index febb863c..a46d097b 100644 --- a/include/libopencm3/cm3/scb.h +++ b/include/libopencm3/cm3/scb.h @@ -374,7 +374,7 @@ struct scb_exception_stack_frame { u32 lr; u32 pc; u32 xpsr; -} __attribute__((packed)); +} __packed; #define SCB_GET_EXCEPTION_STACK_FRAME(f) \ do { \ diff --git a/include/libopencm3/cm3/scs.h b/include/libopencm3/cm3/scs.h index fff4a1b8..56cfb436 100644 --- a/include/libopencm3/cm3/scs.h +++ b/include/libopencm3/cm3/scs.h @@ -21,15 +21,17 @@ #ifndef LIBOPENCM3_CM3_SCS_H #define LIBOPENCM3_CM3_SCS_H -/* +/* * All the definition hereafter are generic for CortexMx ARMv7-M * See ARM document "ARMv7-M Architecture Reference Manual" for more details. - * See also ARM document "ARM Compiler toolchain Developing Software for ARM Processors" for details on System Timer/SysTick. + * See also ARM document "ARM Compiler toolchain Developing Software for ARM + * Processors" for details on System Timer/SysTick. */ /* - * The System Control Space (SCS) is a memory-mapped 4KB address space that provides 32-bit registers for - * configuration, status reporting and control. The SCS registers divide into the following groups: + * The System Control Space (SCS) is a memory-mapped 4KB address space that + * provides 32-bit registers for configuration, status reporting and control. + * The SCS registers divide into the following groups: * - system control and identification * - the CPUID processor identification space * - system configuration and status @@ -46,25 +48,27 @@ /* * Debug Halting Control and Status Register (DHCSR). - * + * * Purpose Controls halting debug. - * Usage constraints: The effect of modifying the C_STEP or C_MASKINTS bit when the system - * is running with halting debug enabled is UNPREDICTABLE. - * Halting debug is enabled when C_DEBUGEN is set to 1. The system is running when S_HALT is set to 0. - * - When C_DEBUGEN is set to 0, the processor ignores the values of all other bits in this register. - * - For more information about the use of DHCSR see Debug stepping on - * page C1-824. + * Usage constraints: The effect of modifying the C_STEP or C_MASKINTS bit when + * the system is running with halting debug enabled is UNPREDICTABLE. + * Halting debug is enabled when C_DEBUGEN is set to 1. The system is running + * when S_HALT is set to 0. + * - When C_DEBUGEN is set to 0, the processor ignores the values of all other + * bits in this register. + * - For more information about the use of DHCSR see Debug stepping on page + * C1-824. * Configurations Always implemented. */ /* SCS_DHCSR register */ #define SCS_DHCSR MMIO32(SCS_BASE + 0xDF0) /* * Debug Core Register Selector Register (DCRSR). - * - * Purpose With the DCRDR, the DCRSR provides debug access to the ARM core registers, - * special-purpose registers, and Floating-point extension registers. A write to DCRSR - * specifies the register to transfer, whether the transfer is a read or a write, and starts - * the transfer. + * + * Purpose With the DCRDR, the DCRSR provides debug access to the ARM core + * registers, special-purpose registers, and Floating-point extension + * registers. A write to DCRSR specifies the register to transfer, whether the + * transfer is a read or a write, and starts the transfer. * Usage constraints: Only accessible in Debug state. * Configurations Always implemented. * @@ -73,15 +77,16 @@ #define SCS_DCRSR MMIO32(SCS_BASE + 0xDF4) /* * Debug Core Register Data Register (DCRDR) - * - * Purpose With the DCRSR, see Debug Core Register Selector Register, - * the DCRDR provides debug access to the ARM core registers, - * special-purpose registers, and Floating-point extension registers. The - * DCRDR is the data register for these accesses. - * - Used on its own, the DCRDR provides a message passing resource between - * an external debugger and a debug agent running on the processor. + * + * Purpose With the DCRSR, see Debug Core Register Selector Register, the DCRDR + * provides debug access to the ARM core registers, special-purpose registers, + * and Floating-point extension registers. The DCRDR is the data register for + * these accesses. + * - Used on its own, the DCRDR provides a message passing resource between an + * external debugger and a debug agent running on the processor. * Note: - * The architecture does not define any handshaking mechanism for this use of DCRDR. + * The architecture does not define any handshaking mechanism for this use of + * DCRDR. * Usage constraints: See Use of DCRSR and DCRDR for constraints that apply to * particular transfers using the DCRSR and DCRDR. * Configurations Always implemented. @@ -92,12 +97,13 @@ /* * Debug Exception and Monitor Control Register (DEMCR). * - * Purpose Manages vector catch behavior and DebugMonitor handling when debugging. + * Purpose Manages vector catch behavior and DebugMonitor handling when + * debugging. * Usage constraints: * - Bits [23:16] provide DebugMonitor exception control. * - Bits [15:0] provide Debug state, halting debug, control. * Configurations Always implemented. - * + * */ /* SCS_DEMCR register */ #define SCS_DEMCR MMIO32(SCS_BASE + 0xDFC) @@ -143,20 +149,22 @@ /* * System Control Space (SCS) => System timer register support in the SCS. - * To configure SysTick, load the interval required between SysTick events to the SysTick Reload - * Value register. The timer interrupt, or COUNTFLAG bit in the SysTick Control and Status - * register, is activated on the transition from 1 to 0, therefore it activates every n+1 clock ticks. - * If you require a period of 100, write 99 to the SysTick Reload Value register. The SysTick Reload - * Value register supports values between 0x1 and 0x00FFFFFF. + * To configure SysTick, load the interval required between SysTick events to + * the SysTick Reload Value register. The timer interrupt, or COUNTFLAG bit in + * the SysTick Control and Status register, is activated on the transition from + * 1 to 0, therefore it activates every n+1 clock ticks. If you require a + * period of 100, write 99 to the SysTick Reload Value register. The SysTick + * Reload Value register supports values between 0x1 and 0x00FFFFFF. * - * If you want to use SysTick to generate an event at a timed interval, for example 1ms, you can - * use the SysTick Calibration Value Register to scale your value for the Reload register. The - * SysTick Calibration Value Register is a read-only register that contains the number of pulses for - * a period of 10ms, in the TENMS field, bits[23:0]. + * If you want to use SysTick to generate an event at a timed interval, for + * example 1ms, you can use the SysTick Calibration Value Register to scale + * your value for the Reload register. The SysTick Calibration Value Register + * is a read-only register that contains the number of pulses for a period of + * 10ms, in the TENMS field, bits[23:0]. * - * This register also has a SKEW bit. Bit[30] == 1 indicates that the calibration for 10ms in the - * TENMS section is not exactly 10ms due to clock frequency. Bit[31] == 1 indicates that the - * reference clock is not provided. + * This register also has a SKEW bit. Bit[30] == 1 indicates that the + * calibration for 10ms in the TENMS section is not exactly 10ms due to clock + * frequency. Bit[31] == 1 indicates that the reference clock is not provided. */ /* * SysTick Control and Status Register (CSR). @@ -176,14 +184,14 @@ */ #define CM_SCS_SYST_RVR MMIO32(SCS_BASE + 0x14) -/* SysTick Current Value Register (RVR). +/* SysTick Current Value Register (RVR). * Purpose Holds the reload value of the SYST_CVR. * Usage constraints There are no usage constraints. * Configurations Always implemented. */ #define CM_SCS_SYST_CVR MMIO32(SCS_BASE + 0x18) -/* +/* * SysTick Calibration value Register(Read Only) (CALIB) * Purpose Reads the calibration value and parameters for SysTick. * Usage constraints: There are no usage constraints. @@ -198,72 +206,86 @@ #define SCS_SYST_CSR_TICKINT (BIT1) /* SysTick uses the processor clock. */ #define SCS_SYST_CSR_CLKSOURCE (BIT2) -/* - * Indicates whether the counter has counted to 0 since the last read of this register: +/* + * Indicates whether the counter has counted to 0 since the last read of this + * register: * 0 = Timer has not counted to 0 - * 1 = Timer has counted to 0. + * 1 = Timer has counted to 0. */ #define SCS_SYST_CSR_COUNTFLAG (BIT16) -/* --- CM_SCS_SYST_RVR values ----------------------------------------------- */ -/* Bit 0 to 23 => RELOAD The value to load into the SYST_CVR when the counter reaches 0. */ +/* --- CM_SCS_SYST_RVR values ---------------------------------------------- */ +/* Bit 0 to 23 => RELOAD The value to load into the SYST_CVR when the counter + * reaches 0. + */ /* Bit 24 to 31 are Reserved */ -/* --- CM_SCS_SYST_CVR values ----------------------------------------------- */ +/* --- CM_SCS_SYST_CVR values ---------------------------------------------- */ /* Bit0 to 31 => Reads or clears the current counter value. */ -/* --- CM_SCS_SYST_CALIB values ----------------------------------------------- */ -/* - * Bit0 to 23 => TENMS Optionally, holds a reload value to be used for 10ms (100Hz) timing, subject to system clock - * skew errors. If this field is zero, the calibration value is not known. +/* --- CM_SCS_SYST_CALIB values -------------------------------------------- */ +/* + * Bit0 to 23 => TENMS Optionally, holds a reload value to be used for 10ms + * (100Hz) timing, subject to system clock skew errors. If this field is zero, + * the calibration value is not known. */ #define SCS_SYST_SYST_CALIB_TENMS_MASK (BIT24-1) -/* +/* * Bit30 => SKEW Indicates whether the 10ms calibration value is exact: * 0 = 10ms calibration value is exact. * 1 = 10ms calibration value is inexact, because of the clock frequency */ #define SCS_SYST_SYST_CALIB_VALUE_INEXACT (BIT30) -/* - * Bit31 => NOREF Indicates whether the IMPLEMENTATION DEFINED reference clock is implemented: +/* + * Bit31 => NOREF Indicates whether the IMPLEMENTATION DEFINED reference clock + * is implemented: * 0 = The reference clock is implemented. * 1 = The reference clock is not implemented. - * When this bit is 1, the CLKSOURCE bit of the SYST_CSR register is forced to 1 and cannot - * be cleared to 0. + * When this bit is 1, the CLKSOURCE bit of the SYST_CSR register is forced to + * 1 and cannot be cleared to 0. */ #define SCS_SYST_SYST_CALIB_REF_NOT_IMPLEMENTED (BIT31) -/* +/* * System Control Space (SCS) => Data Watchpoint and Trace (DWT). - * See http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0403c/index.html (ARMv7-M Architecture Reference Manual) - * The DWT is an optional debug unit that provides watchpoints, data tracing, and system profiling - * for the processor. + * See http://goo.gl/mZm30 (ARMv7-M Architecture Reference Manual) + * The DWT is an optional debug unit that provides watchpoints, data tracing, + * and system profiling for the processor. */ -/* - * DWT Control register - * Purpose Provides configuration and status information for the DWT block, and used to control features of the block +/* + * DWT Control register + * Purpose Provides configuration and status information for the DWT block, and + * used to control features of the block * Usage constraints: There are no usage constraints. * Configurations Always implemented. */ #define SCS_DWT_CTRL MMIO32(DWT_BASE + 0x00) /* * DWT_CYCCNT register - * Cycle Count Register (Shows or sets the value of the processor cycle counter, CYCCNT) - * When enabled, CYCCNT increments on each processor clock cycle. On overflow, CYCCNT wraps to zero. + * Cycle Count Register (Shows or sets the value of the processor cycle + * counter, CYCCNT) + * When enabled, CYCCNT increments on each processor clock cycle. On overflow, + * CYCCNT wraps to zero. * * Purpose Shows or sets the value of the processor cycle counter, CYCCNT. - * Usage constraints: The DWT unit suspends CYCCNT counting when the processor is in Debug state. - * Configurations Implemented: only when DWT_CTRL.NOCYCCNT is RAZ, see Control register, DWT_CTRL. - * When DWT_CTRL.NOCYCCNT is RAO no cycle counter is implemented and this register is UNK/SBZP. + * Usage constraints: The DWT unit suspends CYCCNT counting when the processor + * is in Debug state. + * Configurations Implemented: only when DWT_CTRL.NOCYCCNT is RAZ, see Control + * register, DWT_CTRL. + * When DWT_CTRL.NOCYCCNT is RAO no cycle counter is implemented and this + * register is UNK/SBZP. */ #define SCS_DWT_CYCCNT MMIO32(DWT_BASE + 0x04) -/* DWT_CPICNT register - * Purpose Counts additional cycles required to execute multi-cycle instructions and instruction fetch stalls. - * Usage constraints: The counter initializes to 0 when software enables its counter overflow event by +/* DWT_CPICNT register + * Purpose Counts additional cycles required to execute multi-cycle + * instructions and instruction fetch stalls. + * Usage constraints: The counter initializes to 0 when software enables its + * counter overflow event by * setting the DWT_CTRL.CPIEVTENA bit to 1. - * Configurations Implemented: only when DWT_CTRL.NOPRFCNT is RAZ, see Control register, DWT_CTRL. + * Configurations Implemented: only when DWT_CTRL.NOPRFCNT is RAZ, see Control + * register, DWT_CTRL. * If DWT_CTRL.NOPRFCNT is RAO, indicating that the implementation does not * include the profiling counters, this register is UNK/SBZP. */ @@ -284,8 +306,8 @@ /* DWT_PCSR register */ #define SCS_DWT_PCSR MMIO32(DWT_BASE + 0x18) -/* --- SCS_DWT_CTRL values ----------------------------------------------- */ -/* +/* --- SCS_DWT_CTRL values ------------------------------------------------- */ +/* * Enables CYCCNT: * 0 = Disabled, 1 = Enabled * This bit is UNK/SBZP if the NOCYCCNT bit is RAO. @@ -295,15 +317,20 @@ /* TODO bit definition values for other DWT_XXX register */ /* Macro to be called at startup to enable SCS & Cycle Counter */ -#define SCS_DWT_CYCLE_COUNTER_ENABLED() ( (SCS_DEMCR |= SCS_DEMCR_TRCENA)\ - (SCS_DWT_CTRL |= SCS_DWT_CTRL_CYCCNTENA) ) +#define SCS_DWT_CYCLE_COUNTER_ENABLED() ((SCS_DEMCR |= SCS_DEMCR_TRCENA)\ + (SCS_DWT_CTRL |= SCS_DWT_CTRL_CYCCNTENA)) -#define SCS_SYSTICK_DISABLED() (SCS_SYST_CSR=0) +#define SCS_SYSTICK_DISABLED() (SCS_SYST_CSR = 0) -/* Macro to be called at startup to Enable CortexMx SysTick (but IRQ not enabled) */ -#define SCS_SYSTICK_ENABLED() (SCS_SYST_CSR=(SCS_SYST_CSR_ENABLE | SCS_SYST_CSR_CLKSOURCE)) +/* Macro to be called at startup to Enable CortexMx SysTick (but IRQ not + * enabled) + */ +#define SCS_SYSTICK_ENABLED() (SCS_SYST_CSR = (SCS_SYST_CSR_ENABLE | \ + SCS_SYST_CSR_CLKSOURCE)) /* Macro to be called at startup to Enable CortexMx SysTick and IRQ */ -#define SCS_SYSTICK_AND_IRQ_ENABLED() (SCS_SYST_CSR=(SCS_SYST_CSR_ENABLE | SCS_SYST_CSR_CLKSOURCE | SCS_SYST_CSR_TICKINT)) +#define SCS_SYSTICK_AND_IRQ_ENABLED() (SCS_SYST_CSR = (SCS_SYST_CSR_ENABLE | \ + SCS_SYST_CSR_CLKSOURCE | \ + SCS_SYST_CSR_TICKINT)) #endif diff --git a/include/libopencm3/cm3/sync.h b/include/libopencm3/cm3/sync.h index ccec5e8c..93b88dcd 100644 --- a/include/libopencm3/cm3/sync.h +++ b/include/libopencm3/cm3/sync.h @@ -29,8 +29,8 @@ /* --- Exclusive load and store instructions ------------------------------- */ -u32 __ldrex(volatile u32* addr); -u32 __strex(u32 val, volatile u32* addr); +u32 __ldrex(volatile u32 *addr); +u32 __strex(u32 val, volatile u32 *addr); void __dmb(void); /* --- Convenience functions ----------------------------------------------- */ @@ -42,7 +42,7 @@ typedef u32 mutex_t; #define MUTEX_UNLOCKED 0 #define MUTEX_LOCKED 1 -void mutex_lock(mutex_t* m); -void mutex_unlock(mutex_t* m); +void mutex_lock(mutex_t *m); +void mutex_unlock(mutex_t *m); #endif diff --git a/include/libopencm3/cm3/tpiu.h b/include/libopencm3/cm3/tpiu.h index 003eb6d0..63522eb2 100644 --- a/include/libopencm3/cm3/tpiu.h +++ b/include/libopencm3/cm3/tpiu.h @@ -53,14 +53,14 @@ * bit[N] == 0, trace port width of (N+1) not supported * bit[N] == 1, trace port width of (N+1) supported */ -#define TPIU_SSPSR_BYTE (1 << 0) +#define TPIU_SSPSR_BYTE (1 << 0) #define TPIU_SSPSR_HALFWORD (1 << 1) #define TPIU_SSPSR_WORD (1 << 3) /* --- TPIU_SSPSR values --------------------------------------------------- */ /* Same format as TPIU_SSPSR, except only one is set */ -#define TPIU_CSPSR_BYTE (1 << 0) +#define TPIU_CSPSR_BYTE (1 << 0) #define TPIU_CSPSR_HALFWORD (1 << 1) #define TPIU_CSPSR_WORD (1 << 3) diff --git a/include/libopencm3/cm3/vector.h b/include/libopencm3/cm3/vector.h index f78e9d84..abbfb0cc 100644 --- a/include/libopencm3/cm3/vector.h +++ b/include/libopencm3/cm3/vector.h @@ -45,7 +45,7 @@ typedef void (*vector_table_entry_t)(void); typedef struct { - unsigned int *initial_sp_value; /**< The value the stack pointer is set to initially */ + unsigned int *initial_sp_value; /**< Initial stack pointer value. */ vector_table_entry_t reset; vector_table_entry_t nmi; vector_table_entry_t hard_fault; diff --git a/include/libopencm3/lm3s/gpio.h b/include/libopencm3/lm3s/gpio.h index e261b6a0..928f1e83 100644 --- a/include/libopencm3/lm3s/gpio.h +++ b/include/libopencm3/lm3s/gpio.h @@ -6,7 +6,8 @@ @version 1.0.0 -@author @htmlonly © @endhtmlonly 2011 Gareth McMullin +@author @htmlonly © @endhtmlonly 2011 +Gareth McMullin @date 10 March 2013 diff --git a/include/libopencm3/lm3s/systemcontrol.h b/include/libopencm3/lm3s/systemcontrol.h index 15e4d603..dd02f0f3 100644 --- a/include/libopencm3/lm3s/systemcontrol.h +++ b/include/libopencm3/lm3s/systemcontrol.h @@ -6,7 +6,8 @@ @version 1.0.0 -@author @htmlonly © @endhtmlonly 2011 Gareth McMullin +@author @htmlonly © @endhtmlonly 2011 +Gareth McMullin @date 10 March 2013 diff --git a/include/libopencm3/lm4f/gpio.h b/include/libopencm3/lm4f/gpio.h index 491b54b6..0b8966b4 100644 --- a/include/libopencm3/lm4f/gpio.h +++ b/include/libopencm3/lm4f/gpio.h @@ -6,8 +6,10 @@ * * @version 1.0.0 * - * @author @htmlonly © @endhtmlonly 2011 Gareth McMullin - * @author @htmlonly © @endhtmlonly 2013 Alexandru Gagniuc + * @author @htmlonly © @endhtmlonly 2011 + * Gareth McMullin + * @author @htmlonly © @endhtmlonly 2013 + * Alexandru Gagniuc * * @date 16 March 2013 * diff --git a/include/libopencm3/lm4f/nvic.h b/include/libopencm3/lm4f/nvic.h index 7bf37ca6..841367f9 100644 --- a/include/libopencm3/lm4f/nvic.h +++ b/include/libopencm3/lm4f/nvic.h @@ -1,12 +1,14 @@ /** @defgroup nvic_defines Nested Vectored Interrupt Controller -@brief Defined Constants and Types for the LM4F Nested Vectored Interrupt Controller +@brief Defined Constants and Types for the LM4F Nested Vectored Interrupt +Controller @ingroup LM4Fxx_defines @version 1.0.0 -@author @htmlonly © @endhtmlonly 2012 Alexandru Gagniuc +@author @htmlonly © @endhtmlonly 2012 +Alexandru Gagniuc @date 10 March 2013 @@ -40,9 +42,9 @@ LGPL License Terms @ref lgpl_license #include /** @ingroup nvic_defines - * The LM3S interrupt table applies to the LM4F as well. - * Some interrupt vectors marked as reserved in LM3S are used in LM4F, and some - * vectors in LM3S are marked reserved for LM4F. However, the common vectors are + * The LM3S interrupt table applies to the LM4F as well. Some interrupt + * vectors marked as reserved in LM3S are used in LM4F, and some vectors in + * LM3S are marked reserved for LM4F. However, the common vectors are * identical, and we can safely use the same interrupt table. Reserved vectors * will never be triggered, so having them is perfectly safe. */ diff --git a/include/libopencm3/lm4f/rcc.h b/include/libopencm3/lm4f/rcc.h index c667d334..f7f22cb8 100644 --- a/include/libopencm3/lm4f/rcc.h +++ b/include/libopencm3/lm4f/rcc.h @@ -6,7 +6,8 @@ @version 1.0.0 -@author @htmlonly © @endhtmlonly 2012 Alexandru Gagniuc +@author @htmlonly © @endhtmlonly 2012 +Alexandru Gagniuc @date 10 March 2013 diff --git a/include/libopencm3/lm4f/systemcontrol.h b/include/libopencm3/lm4f/systemcontrol.h index 44208a02..64d98192 100644 --- a/include/libopencm3/lm4f/systemcontrol.h +++ b/include/libopencm3/lm4f/systemcontrol.h @@ -6,7 +6,8 @@ @version 1.0.0 -@author @htmlonly © @endhtmlonly 2012 Alexandru Gagniuc +@author @htmlonly © @endhtmlonly 2012 +Alexandru Gagniuc @date 10 March 2013 @@ -726,9 +727,9 @@ typedef enum { } clken_t; -/* ============================================================================= +/* ============================================================================ * Function prototypes - * ---------------------------------------------------------------------------*/ + * --------------------------------------------------------------------------*/ BEGIN_DECLS void periph_clock_enable(clken_t periph); @@ -740,5 +741,3 @@ END_DECLS #endif /* LM4F_SYSTEMCONTROL_H */ - - diff --git a/include/libopencm3/lm4f/uart.h b/include/libopencm3/lm4f/uart.h index 967b33ac..f35d0e04 100644 --- a/include/libopencm3/lm4f/uart.h +++ b/include/libopencm3/lm4f/uart.h @@ -6,7 +6,8 @@ * * @version 1.0.0 * - * @author @htmlonly © @endhtmlonly 2013 Alexandru Gagniuc + * @author @htmlonly © @endhtmlonly 2013 + * Alexandru Gagniuc * * @date 07 May 2013 * @@ -479,7 +480,8 @@ void uart_set_fifo_trigger_levels(u32 uart, * @param[in] uart UART block register address base @ref uart_reg_base */ static inline -bool uart_is_tx_fifo_full(u32 uart) { +bool uart_is_tx_fifo_full(u32 uart) +{ return UART_FR(uart) & UART_FR_TXFF; } @@ -490,7 +492,8 @@ bool uart_is_tx_fifo_full(u32 uart) { * @param[in] uart UART block register address base @ref uart_reg_base */ static inline -bool uart_is_tx_fifo_empty(u32 uart) { +bool uart_is_tx_fifo_empty(u32 uart) +{ return UART_FR(uart) & UART_FR_TXFE; } @@ -500,7 +503,8 @@ bool uart_is_tx_fifo_empty(u32 uart) { * @param[in] uart UART block register address base @ref uart_reg_base */ static inline -bool uart_is_rx_fifo_full(u32 uart) { +bool uart_is_rx_fifo_full(u32 uart) +{ return UART_FR(uart) & UART_FR_RXFF; } @@ -510,7 +514,8 @@ bool uart_is_rx_fifo_full(u32 uart) { * @param[in] uart UART block register address base @ref uart_reg_base */ static inline -bool uart_is_rx_fifo_empty(u32 uart) { +bool uart_is_rx_fifo_empty(u32 uart) +{ return UART_FR(uart) & UART_FR_RXFE; } /**@}*/ diff --git a/include/libopencm3/lm4f/usb.h b/include/libopencm3/lm4f/usb.h index ae741735..f22d7995 100644 --- a/include/libopencm3/lm4f/usb.h +++ b/include/libopencm3/lm4f/usb.h @@ -41,15 +41,15 @@ #include #include -/* ============================================================================= +/* ============================================================================ * USB registers - * ---------------------------------------------------------------------------*/ + * --------------------------------------------------------------------------*/ /* USB Device Functional Address */ -#define USB_FADDR MMIO8 (USB_BASE + 0x00) +#define USB_FADDR MMIO8(USB_BASE + 0x00) /* USB Power */ -#define USB_POWER MMIO8 (USB_BASE + 0x01) +#define USB_POWER MMIO8(USB_BASE + 0x01) /* USB Transmit Interrupt Status */ #define USB_TXIS MMIO16(USB_BASE + 0x02) @@ -64,19 +64,19 @@ #define USB_RXIE MMIO16(USB_BASE + 0x08) /* USB General Interrupt Status */ -#define USB_IS MMIO8 (USB_BASE + 0x0A) +#define USB_IS MMIO8(USB_BASE + 0x0A) /* USB Interrupt Enable */ -#define USB_IE MMIO8 (USB_BASE + 0x0B) +#define USB_IE MMIO8(USB_BASE + 0x0B) /* USB Frame Value */ #define USB_FRAME MMIO16(USB_BASE + 0x0C) /* USB Endpoint Index */ -#define USB_EPIDX MMIO8 (USB_BASE + 0x0E) +#define USB_EPIDX MMIO8(USB_BASE + 0x0E) /* USB Test Mode */ -#define USB_TEST MMIO8 (USB_BASE + 0x0F) +#define USB_TEST MMIO8(USB_BASE + 0x0F) /* USB FIFO Endpoint [0-7] */ #define USB_FIFO8(n) MMIO8(USB_BASE + 0x20 + n*0x04) @@ -84,10 +84,10 @@ #define USB_FIFO32(n) MMIO32(USB_BASE + 0x20 + n*0x04) /* USB Transmit Dynamic FIFO Sizing */ -#define USB_TXFIFOSZ MMIO8 (USB_BASE + 0x62) +#define USB_TXFIFOSZ MMIO8(USB_BASE + 0x62) /* USB Receive Dynamic FIFO Sizing */ -#define USB_RXFIFOSZ MMIO8 (USB_BASE + 0x63) +#define USB_RXFIFOSZ MMIO8(USB_BASE + 0x63) /* USB Transmit FIFO Start Address */ #define USB_TXFIFOADD MMIO16(USB_BASE + 0x64) @@ -96,40 +96,40 @@ #define USB_RXFIFOADD MMIO16(USB_BASE + 0x66) /* USB Connect Timing */ -#define USB_CONTIM MMIO8 (USB_BASE + 0x7A) +#define USB_CONTIM MMIO8(USB_BASE + 0x7A) /* USB Full-Speed Last Transaction to End of Frame Timing */ -#define USB_FSEOF MMIO8 (USB_BASE + 0x7D) +#define USB_FSEOF MMIO8(USB_BASE + 0x7D) /* USB Low-Speed Last Transaction to End of Frame Timing */ -#define USB_LSEOF MMIO8 (USB_BASE + 0x7E) +#define USB_LSEOF MMIO8(USB_BASE + 0x7E) /* USB Control and Status Endpoint 0 Low */ -#define USB_CSRL0 MMIO8 (USB_BASE + 0x102) +#define USB_CSRL0 MMIO8(USB_BASE + 0x102) /* USB Control and Status Endpoint 0 High */ -#define USB_CSRH0 MMIO8 (USB_BASE + 0x103) +#define USB_CSRH0 MMIO8(USB_BASE + 0x103) /* USB Receive Byte Count Endpoint 0 */ -#define USB_COUNT0 MMIO8 (USB_BASE + 0x108) +#define USB_COUNT0 MMIO8(USB_BASE + 0x108) /* USB Maximum Transmit Data Endpoint [1-7] */ #define USB_TXMAXP(n) MMIO16(USB_BASE + 0x100 + n*0x10) /* USB Transmit Control and Status Endpoint [1-7] Low */ -#define USB_TXCSRL(n) MMIO8 (USB_BASE + 0x102 + n*0x10) +#define USB_TXCSRL(n) MMIO8(USB_BASE + 0x102 + n*0x10) /* USB Transmit Control and Status Endpoint [1-7] High */ -#define USB_TXCSRH(n) MMIO8 (USB_BASE + 0x103 + n*0x10) +#define USB_TXCSRH(n) MMIO8(USB_BASE + 0x103 + n*0x10) /* USB Maximum Receive Data Endpoint [1-7] */ #define USB_RXMAXP(n) MMIO16(USB_BASE + 0x104 + n*0x10) /* USB Receive Control and Status Endpoint [1-7] Low */ -#define USB_RXCSRL(n) MMIO8 (USB_BASE + 0x106 + n*0x10) +#define USB_RXCSRL(n) MMIO8(USB_BASE + 0x106 + n*0x10) /* USB Receive Control and Status Endpoint [1-7] High */ -#define USB_RXCSRH(n) MMIO8 (USB_BASE + 0x107 + n*0x10) +#define USB_RXCSRH(n) MMIO8(USB_BASE + 0x107 + n*0x10) /* USB Receive Byte Count Endpoint [1-7] */ #define USB_RXCOUNT(n) MMIO16(USB_BASE + 0x108 + n*0x10) @@ -419,4 +419,4 @@ END_DECLS /**@}*/ -#endif /* LIBOPENCM3_LM4F_USB_H */ \ No newline at end of file +#endif /* LIBOPENCM3_LM4F_USB_H */ diff --git a/include/libopencm3/lpc17xx/gpio.h b/include/libopencm3/lpc17xx/gpio.h index 852ad2a9..664a3a1c 100644 --- a/include/libopencm3/lpc17xx/gpio.h +++ b/include/libopencm3/lpc17xx/gpio.h @@ -151,7 +151,7 @@ LGPL License Terms @ref lgpl_license BEGIN_DECLS void gpio_set(u32 gpioport, u32 gpios); -void gpio_clear(u32 gpioport, u32 gpios); +void gpio_clear(u32 gpioport, u32 gpios); END_DECLS diff --git a/include/libopencm3/lpc17xx/memorymap.h b/include/libopencm3/lpc17xx/memorymap.h index cbb2acb2..9dce5dd8 100644 --- a/include/libopencm3/lpc17xx/memorymap.h +++ b/include/libopencm3/lpc17xx/memorymap.h @@ -33,12 +33,12 @@ /* APB0 */ #define WDT_BASE (PERIPH_BASE_APB0 + 0x00000) -#define TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000) +#define TIMER0_BASE (PERIPH_BASE_APB0 + 0x04000) #define TIMER1_BASE (PERIPH_BASE_APB0 + 0x08000) -#define UART0_BASE (PERIPH_BASE_APB0 + 0x0c000) -#define UART1_BASE (PERIPH_BASE_APB0 + 0x10000) +#define UART0_BASE (PERIPH_BASE_APB0 + 0x0c000) +#define UART1_BASE (PERIPH_BASE_APB0 + 0x10000) /* PERIPH_BASE_APB0 + 0X14000 (0x4001 4000 - 0x4001 7FFF): Reserved */ -#define PWM1_BASE (PERIPH_BASE_APB0 + 0x18000) +#define PWM1_BASE (PERIPH_BASE_APB0 + 0x18000) #define I2C0_BASE (PERIPH_BASE_APB0 + 0x1c000) #define SPI_BASE (PERIPH_BASE_APB0 + 0x20000) #define RTC_BASE (PERIPH_BASE_APB0 + 0x24000) @@ -46,13 +46,13 @@ #define PINCONNECT_BASE (PERIPH_BASE_APB0 + 0x2c000) #define SSP1_BASE (PERIPH_BASE_APB0 + 0x30000) #define ADC_BASE (PERIPH_BASE_APB0 + 0x34000) -#define CANAFRAM_BASE (PERIPH_BASE_APB0 + 0x38000) -#define CANAFREG_BASE (PERIPH_BASE_APB0 + 0x3C000) -#define CANCOMMONREG_BASE (PERIPH_BASE_APB0 + 0x40000) -#define CAN1_BASE (PERIPH_BASE_APB0 + 0x44000) -#define CAN2_BASE (PERIPH_BASE_APB0 + 0x48000) +#define CANAFRAM_BASE (PERIPH_BASE_APB0 + 0x38000) +#define CANAFREG_BASE (PERIPH_BASE_APB0 + 0x3C000) +#define CANCOMMONREG_BASE (PERIPH_BASE_APB0 + 0x40000) +#define CAN1_BASE (PERIPH_BASE_APB0 + 0x44000) +#define CAN2_BASE (PERIPH_BASE_APB0 + 0x48000) /* PERIPH_BASE_APB0 + 0X4C000 (0x4004 C000 - 0x4005 BFFF): Reserved */ -#define I2C1_BASE (PERIPH_BASE_APB0 + 0x5C000) +#define I2C1_BASE (PERIPH_BASE_APB0 + 0x5C000) /* PERIPH_BASE_APB0 + 0X60000 (0x6000 0000 - 0x4007 BFFF): Reserved */ /* AHB */ diff --git a/include/libopencm3/lpc43xx/creg.h b/include/libopencm3/lpc43xx/creg.h index 2213c6f9..3f899186 100644 --- a/include/libopencm3/lpc43xx/creg.h +++ b/include/libopencm3/lpc43xx/creg.h @@ -1,6 +1,7 @@ /** @defgroup creg_defines Configuration Registers Defines -@brief Defined Constants and Types for the LPC43xx Configuration Registers +@brief Defined Constants and Types for the LPC43xx Configuration +Registers @ingroup LPC43xx_defines diff --git a/include/libopencm3/lpc43xx/gima.h b/include/libopencm3/lpc43xx/gima.h index c54df67c..6a36c76c 100644 --- a/include/libopencm3/lpc43xx/gima.h +++ b/include/libopencm3/lpc43xx/gima.h @@ -1,6 +1,7 @@ /** @defgroup gima_defines Global Input Multiplexer Array Defines -@brief Defined Constants and Types for the LPC43xx Global Input Multiplexer Array +@brief Defined Constants and Types for the LPC43xx Global Input Multiplexer +Array @ingroup LPC43xx_defines diff --git a/include/libopencm3/lpc43xx/gpio.h b/include/libopencm3/lpc43xx/gpio.h index 397d7e5a..7f8d1b5f 100644 --- a/include/libopencm3/lpc43xx/gpio.h +++ b/include/libopencm3/lpc43xx/gpio.h @@ -88,7 +88,7 @@ LGPL License Terms @ref lgpl_license /* --- GPIO registers ------------------------------------------------------ */ -//TODO byte/word access registers +/* TODO byte/word access registers */ /* GPIO data direction register (GPIOn_DIR) */ #define GPIO_DIR(port) MMIO32(port + 0x00) @@ -167,7 +167,7 @@ LGPL License Terms @ref lgpl_license #define GPIO6_NOT GPIO_NOT(GPIO6) #define GPIO7_NOT GPIO_NOT(GPIO7) -//TODO interrupts +/* TODO interrupts */ BEGIN_DECLS diff --git a/include/libopencm3/lpc43xx/i2s.h b/include/libopencm3/lpc43xx/i2s.h index 52f5c740..63f7afb6 100644 --- a/include/libopencm3/lpc43xx/i2s.h +++ b/include/libopencm3/lpc43xx/i2s.h @@ -45,7 +45,6 @@ LGPL License Terms @ref lgpl_license #define I2S0 I2S0_BASE #define I2S1 I2S1_BASE - /* --- I2S registers ------------------------------------------------------- */ /* I2S Digital Audio Output Register */ diff --git a/include/libopencm3/lpc43xx/ritimer.h b/include/libopencm3/lpc43xx/ritimer.h index e7308787..e736bc30 100644 --- a/include/libopencm3/lpc43xx/ritimer.h +++ b/include/libopencm3/lpc43xx/ritimer.h @@ -1,6 +1,7 @@ /** @defgroup ritimer_defines Repetitive Interrupt Timer Defines -@brief Defined Constants and Types for the LPC43xx Repetitive Interrupt Timer +@brief Defined Constants and Types for the LPC43xx Repetitive Interrupt +Timer @ingroup LPC43xx_defines diff --git a/include/libopencm3/lpc43xx/scu.h b/include/libopencm3/lpc43xx/scu.h index 755fd8df..668f4fe3 100644 --- a/include/libopencm3/lpc43xx/scu.h +++ b/include/libopencm3/lpc43xx/scu.h @@ -406,12 +406,13 @@ LGPL License Terms @ref lgpl_license #define SCU_I2C0_NOMINAL (SCU_SCL_EZI_EN | SCU_SDA_EZI_EN) /* Standard mode for I2C SCL/SDA Fast-mode Plus transmit */ -#define SCU_I2C0_FAST (SCU_SCL_EFP | SCU_SCL_EHD | SCU_SCL_EZI_EN | SCU_SCL_ZIF_DIS \ - SCU_SDA_EFP | SCU_SDA_EHD | SCU_SDA_EZI_EN) +#define SCU_I2C0_FAST (SCU_SCL_EFP | SCU_SCL_EHD | SCU_SCL_EZI_EN | \ + SCU_SCL_ZIF_DIS | SCU_SDA_EFP | SCU_SDA_EHD | \ + SCU_SDA_EZI_EN) /* * SCU PIN Normal Drive: -* The pin configuration registers for normal-drive pins control the following pins: +* The configuration registers for normal-drive pins control the following pins: * - P0_0 and P0_1 * - P1_0 to P1_16 and P1_18 to P1_20 * - P2_0 to P2_2 and P2_6 to P2_13 @@ -429,7 +430,7 @@ LGPL License Terms @ref lgpl_license * - PF_0 to PF_11 * * Pin configuration registers for High-Drive pins. -* The pin configuration registers for high-drive pins control the following pins: +* The configuration registers for high-drive pins control the following pins: * - P1_17 * - P2_3 to P2_5 * - P8_0 to P8_2 @@ -607,7 +608,9 @@ typedef enum { PC_13 = (PIN_GROUPC+PIN13), PC_14 = (PIN_GROUPC+PIN14), - /* Group Port D (seems not configurable through SCU, not defined in UM10503.pdf Rev.1, keep it here) */ + /* Group Port D (seems not configurable through SCU, not defined in + * UM10503.pdf Rev.1, keep it here) + */ PD_0 = (PIN_GROUPD+PIN0), PD_1 = (PIN_GROUPD+PIN1), PD_2 = (PIN_GROUPD+PIN2), @@ -700,21 +703,23 @@ typedef enum { /* * Select Slew Rate. * By Default=0 Slow. -* Available to normal-drive pins and high-speed pins, reserved for high-drive pins. +* Available to normal-drive and high-speed pins, reserved for high-drive pins. */ #define SCU_CONF_EHS_FAST (BIT5) /* * Input buffer enable. * By Default=0 Disable Input Buffer. -* The input buffer is disabled by default at reset and must be enabled. -* for receiving(in normal/highspeed-drive) or to transfer data from the I/O buffer to the pad(in high-drive pins). +* The input buffer is disabled by default at reset and must be enabled for +* receiving(in normal/highspeed-drive) or to transfer data from the I/O buffer +* to the pad(in high-drive pins). * Available to normal-drive pins, high-drive pins, high-speed pins. */ #define SCU_CONF_EZI_EN_IN_BUFFER (BIT6) /* -* Input glitch filter. Disable the input glitch filter for clocking signals higher than 30 MHz. +* Input glitch filter. Disable the input glitch filter for clocking signals +* higher than 30 MHz. * Available to normal-drive pins, high-drive pins, high-speed pins. */ #define SCU_CONF_ZIF_DIS_IN_GLITCH_FILT (BIT7) @@ -730,16 +735,39 @@ typedef enum { /* BIT10 to 31 are Reserved */ /* Configuration for different I/O pins types */ -#define SCU_EMC_IO (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) -#define SCU_LCD (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) -#define SCU_CLK_IN (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) -#define SCU_CLK_OUT (SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_EMC_IO (SCU_CONF_EPD_EN_PULLDOWN | \ + SCU_CONF_EHS_FAST | \ + SCU_CONF_EZI_EN_IN_BUFFER | \ + SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_LCD (SCU_CONF_EPUN_DIS_PULLUP | \ + SCU_CONF_EHS_FAST | \ + SCU_CONF_EZI_EN_IN_BUFFER | \ + SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_CLK_IN (SCU_CONF_EPD_EN_PULLDOWN | \ + SCU_CONF_EHS_FAST | \ + SCU_CONF_EZI_EN_IN_BUFFER | \ + SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_CLK_OUT (SCU_CONF_EPD_EN_PULLDOWN | \ + SCU_CONF_EHS_FAST | \ + SCU_CONF_EZI_EN_IN_BUFFER | \ + SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) #define SCU_GPIO_PUP (SCU_CONF_EZI_EN_IN_BUFFER) -#define SCU_GPIO_PDN (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER) -#define SCU_GPIO_NOPULL (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EZI_EN_IN_BUFFER) -#define SCU_GPIO_FAST (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) -#define SCU_UART_RX_TX (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EPD_EN_PULLDOWN | SCU_CONF_EZI_EN_IN_BUFFER) -#define SCU_SSP_IO (SCU_CONF_EPUN_DIS_PULLUP | SCU_CONF_EHS_FAST | SCU_CONF_EZI_EN_IN_BUFFER | SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_GPIO_PDN (SCU_CONF_EPUN_DIS_PULLUP | \ + SCU_CONF_EPD_EN_PULLDOWN | \ + SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_GPIO_NOPULL (SCU_CONF_EPUN_DIS_PULLUP | \ + SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_GPIO_FAST (SCU_CONF_EPUN_DIS_PULLUP | \ + SCU_CONF_EHS_FAST | \ + SCU_CONF_EZI_EN_IN_BUFFER | \ + SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) +#define SCU_UART_RX_TX (SCU_CONF_EPUN_DIS_PULLUP | \ + SCU_CONF_EPD_EN_PULLDOWN | \ + SCU_CONF_EZI_EN_IN_BUFFER) +#define SCU_SSP_IO (SCU_CONF_EPUN_DIS_PULLUP | \ + SCU_CONF_EHS_FAST | \ + SCU_CONF_EZI_EN_IN_BUFFER | \ + SCU_CONF_ZIF_DIS_IN_GLITCH_FILT) BEGIN_DECLS diff --git a/include/libopencm3/lpc43xx/sgpio.h b/include/libopencm3/lpc43xx/sgpio.h index 686108af..cee08d8e 100644 --- a/include/libopencm3/lpc43xx/sgpio.h +++ b/include/libopencm3/lpc43xx/sgpio.h @@ -1,6 +1,7 @@ /** @defgroup sgpio_defines Serial General Purpose I/O -@brief Defined Constants and Types for the LPC43xx Serial General Purpose I/O +@brief Defined Constants and Types for the LPC43xx Serial General Purpose +I/O @ingroup LPC43xx_defines @@ -76,7 +77,8 @@ LGPL License Terms @ref lgpl_license #define SGPIO_OUT_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0x3C) /* SGPIO multiplexer configuration registers (SGPIO_MUX_CFG0 to 15) */ -#define SGPIO_MUX_CFG(slice) MMIO32(SGPIO_PORT_BASE + 0x40 + (slice * 0x04)) +#define SGPIO_MUX_CFG(slice) MMIO32(SGPIO_PORT_BASE + 0x40 + \ + (slice * 0x04)) #define SGPIO_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x40) #define SGPIO_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x44) #define SGPIO_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x48) @@ -95,7 +97,8 @@ LGPL License Terms @ref lgpl_license #define SGPIO_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0x7C) /* Slice multiplexer configuration registers (SLICE_MUX_CFG0 to 15) */ -#define SGPIO_SLICE_MUX_CFG(slice) MMIO32(SGPIO_PORT_BASE + 0x80 + (slice * 0x04)) +#define SGPIO_SLICE_MUX_CFG(slice) MMIO32(SGPIO_PORT_BASE + 0x80 + \ + (slice * 0x04)) #define SGPIO_SLICE_MUX_CFG0 MMIO32(SGPIO_PORT_BASE + 0x80) #define SGPIO_SLICE_MUX_CFG1 MMIO32(SGPIO_PORT_BASE + 0x84) #define SGPIO_SLICE_MUX_CFG2 MMIO32(SGPIO_PORT_BASE + 0x88) @@ -114,7 +117,8 @@ LGPL License Terms @ref lgpl_license #define SGPIO_SLICE_MUX_CFG15 MMIO32(SGPIO_PORT_BASE + 0xBC) /* Slice data registers (REG0 to 15) */ -#define SGPIO_REG(slice) MMIO32(SGPIO_PORT_BASE + 0xC0 + (slice * 0x04)) +#define SGPIO_REG(slice) MMIO32(SGPIO_PORT_BASE + 0xC0 + \ + (slice * 0x04)) #define SGPIO_REG0 MMIO32(SGPIO_PORT_BASE + 0xC0) #define SGPIO_REG1 MMIO32(SGPIO_PORT_BASE + 0xC4) #define SGPIO_REG2 MMIO32(SGPIO_PORT_BASE + 0xC8) @@ -133,7 +137,8 @@ LGPL License Terms @ref lgpl_license #define SGPIO_REG15 MMIO32(SGPIO_PORT_BASE + 0xFC) /* Slice data shadow registers (REG_SS0 to 15) */ -#define SGPIO_REG_SS(slice) MMIO32(SGPIO_PORT_BASE + 0x100 + (slice * 0x04)) +#define SGPIO_REG_SS(slice) MMIO32(SGPIO_PORT_BASE + 0x100 + \ + (slice * 0x04)) #define SGPIO_REG_SS0 MMIO32(SGPIO_PORT_BASE + 0x100) #define SGPIO_REG_SS1 MMIO32(SGPIO_PORT_BASE + 0x104) #define SGPIO_REG_SS2 MMIO32(SGPIO_PORT_BASE + 0x108) @@ -152,7 +157,8 @@ LGPL License Terms @ref lgpl_license #define SGPIO_REG_SS15 MMIO32(SGPIO_PORT_BASE + 0x13C) /* Reload registers (PRESET0 to 15) */ -#define SGPIO_PRESET(slice) MMIO32(SGPIO_PORT_BASE + 0x140 + (slice * 0x04)) +#define SGPIO_PRESET(slice) MMIO32(SGPIO_PORT_BASE + 0x140 + \ + (slice * 0x04)) #define SGPIO_PRESET0 MMIO32(SGPIO_PORT_BASE + 0x140) #define SGPIO_PRESET1 MMIO32(SGPIO_PORT_BASE + 0x144) #define SGPIO_PRESET2 MMIO32(SGPIO_PORT_BASE + 0x148) @@ -171,7 +177,8 @@ LGPL License Terms @ref lgpl_license #define SGPIO_PRESET15 MMIO32(SGPIO_PORT_BASE + 0x17C) /* Down counter registers (COUNT0 to 15) */ -#define SGPIO_COUNT(slice) MMIO32(SGPIO_PORT_BASE + 0x180 + (slice * 0x04)) +#define SGPIO_COUNT(slice) MMIO32(SGPIO_PORT_BASE + 0x180 + \ + (slice * 0x04)) #define SGPIO_COUNT0 MMIO32(SGPIO_PORT_BASE + 0x180) #define SGPIO_COUNT1 MMIO32(SGPIO_PORT_BASE + 0x184) #define SGPIO_COUNT2 MMIO32(SGPIO_PORT_BASE + 0x188) @@ -190,7 +197,8 @@ LGPL License Terms @ref lgpl_license #define SGPIO_COUNT15 MMIO32(SGPIO_PORT_BASE + 0x1BC) /* Position registers (POS0 to 15) */ -#define SGPIO_POS(slice) MMIO32(SGPIO_PORT_BASE + 0x1C0 + (slice * 0x04)) +#define SGPIO_POS(slice) MMIO32(SGPIO_PORT_BASE + 0x1C0 + \ + (slice * 0x04)) #define SGPIO_POS0 MMIO32(SGPIO_PORT_BASE + 0x1C0) #define SGPIO_POS1 MMIO32(SGPIO_PORT_BASE + 0x1C4) #define SGPIO_POS2 MMIO32(SGPIO_PORT_BASE + 0x1C8) diff --git a/include/libopencm3/lpc43xx/ssp.h b/include/libopencm3/lpc43xx/ssp.h index 64e048c6..6ba8200b 100644 --- a/include/libopencm3/lpc43xx/ssp.h +++ b/include/libopencm3/lpc43xx/ssp.h @@ -1,6 +1,7 @@ /** @defgroup ssp_defines Synchronous Serial Port -@brief Defined Constants and Types for the LPC43xx Synchronous Serial Port +@brief Defined Constants and Types for the LPC43xx Synchronous Serial +Port @ingroup LPC43xx_defines @@ -109,9 +110,9 @@ typedef enum { SSP1_NUM = 0x1 } ssp_num_t; -/* -* SSP Control Register 0 -*/ +/* + * SSP Control Register 0 + */ /* SSP Data Size Bits 0 to 3 */ typedef enum { SSP_DATA_4BITS = 0x3, @@ -126,7 +127,7 @@ typedef enum { SSP_DATA_13BITS = 0xC, SSP_DATA_14BITS = 0xD, SSP_DATA_15BITS = 0xE, - SSP_DATA_16BITS = 0xF + SSP_DATA_16BITS = 0xF } ssp_datasize_t; /* SSP Frame Format/Type Bits 4 & 5 */ @@ -144,9 +145,9 @@ typedef enum { SSP_CPOL_1_CPHA_1 = (BIT6|BIT7) } ssp_cpol_cpha_t; -/* -* SSP Control Register 1 -*/ +/* + * SSP Control Register 1 + */ /* SSP Mode Bit0 */ typedef enum { SSP_MODE_NORMAL = 0x0, @@ -177,10 +178,11 @@ BEGIN_DECLS void ssp_disable(ssp_num_t ssp_num); -/* +/* * SSP Init * clk_prescale shall be in range 2 to 254 (even number only). - * Clock computation: PCLK / (CPSDVSR * [SCR+1]) => CPSDVSR=clk_prescale, SCR=serial_clock_rate + * Clock computation: PCLK / (CPSDVSR * [SCR+1]) => CPSDVSR=clk_prescale, + * SCR=serial_clock_rate */ void ssp_init(ssp_num_t ssp_num, ssp_datasize_t data_size, diff --git a/include/libopencm3/lpc43xx/usb.h b/include/libopencm3/lpc43xx/usb.h index 96982e44..7c832a02 100644 --- a/include/libopencm3/lpc43xx/usb.h +++ b/include/libopencm3/lpc43xx/usb.h @@ -152,6 +152,6 @@ /* --- USB1 registers ------------------------------------------------------ */ -//TODO +/* TODO */ #endif diff --git a/include/libopencm3/lpc43xx/wwdt.h b/include/libopencm3/lpc43xx/wwdt.h index a6c0123c..30ff6a7e 100644 --- a/include/libopencm3/lpc43xx/wwdt.h +++ b/include/libopencm3/lpc43xx/wwdt.h @@ -1,6 +1,7 @@ /** @defgroup wwdt_defines Windowed Watchdog Timer -@brief Defined Constants and Types for the LPC43xx Windowed Watchdog Timer +@brief Defined Constants and Types for the LPC43xx Windowed Watchdog +Timer @ingroup LPC43xx_defines diff --git a/include/libopencm3/sam/eefc.h b/include/libopencm3/sam/eefc.h index d0ba095d..18785b69 100644 --- a/include/libopencm3/sam/eefc.h +++ b/include/libopencm3/sam/eefc.h @@ -48,7 +48,7 @@ #define EEFC_FCR_FKEY (0x5A << 24) #define EEFC_FCR_FARG_MASK (0xFFFF << 8) #define EEFC_FCR_FCMD_MASK (0xFF << 0) -#define EEFC_FCR_FCMD_GETD (0x00 << 0) +#define EEFC_FCR_FCMD_GETD (0x00 << 0) #define EEFC_FCR_FCMD_WP (0x01 << 0) #define EEFC_FCR_FCMD_WPL (0x02 << 0) #define EEFC_FCR_FCMD_EWP (0x03 << 0) diff --git a/include/libopencm3/stm32/can.h b/include/libopencm3/stm32/can.h index a6d4cfda..0ffdedab 100644 --- a/include/libopencm3/stm32/can.h +++ b/include/libopencm3/stm32/can.h @@ -159,8 +159,10 @@ LGPL License Terms @ref lgpl_license * Connectivity line devices have 28 banks so the bank ID spans 0..27 * all other devices have 14 banks so the bank ID spans 0..13. */ -#define CAN_FiR1(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x0) -#define CAN_FiR2(can_base, bank) MMIO32(can_base + 0x240 + (bank * 0x8) + 0x4) +#define CAN_FiR1(can_base, bank) MMIO32(can_base + 0x240 + \ + (bank * 0x8) + 0x0) +#define CAN_FiR2(can_base, bank) MMIO32(can_base + 0x240 + \ + (bank * 0x8) + 0x4) /* --- CAN_MCR values ------------------------------------------------------ */ diff --git a/include/libopencm3/stm32/common/crc_common_all.h b/include/libopencm3/stm32/common/crc_common_all.h index 5f9bd651..a37a22d2 100644 --- a/include/libopencm3/stm32/common/crc_common_all.h +++ b/include/libopencm3/stm32/common/crc_common_all.h @@ -23,7 +23,7 @@ * along with this library. If not, see . */ -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA CRC.H +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA CRC.H The order of header inclusion is important. crc.h includes the device specific memorymap.h header before including this header file.*/ diff --git a/include/libopencm3/stm32/common/dac_common_all.h b/include/libopencm3/stm32/common/dac_common_all.h index 706a2fa8..1652b9ae 100644 --- a/include/libopencm3/stm32/common/dac_common_all.h +++ b/include/libopencm3/stm32/common/dac_common_all.h @@ -1,6 +1,7 @@ /** @addtogroup dac_defines -@author @htmlonly © @endhtmlonly 2012 Felix Held +@author @htmlonly © @endhtmlonly 2012 +Felix Held */ @@ -25,7 +26,7 @@ /**@{*/ -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DAC.H +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DAC.H The order of header inclusion is important. dac.h includes the device specific memorymap.h header before including this header file.*/ diff --git a/include/libopencm3/stm32/common/dma_common_f13.h b/include/libopencm3/stm32/common/dma_common_f13.h index f7294bcb..5bf95c1b 100644 --- a/include/libopencm3/stm32/common/dma_common_f13.h +++ b/include/libopencm3/stm32/common/dma_common_f13.h @@ -1,7 +1,9 @@ -/** @addtogroup dma_defines +/** @addtogroup dma_defines -@author @htmlonly © @endhtmlonly 2010 Thomas Otto -@author @htmlonly © @endhtmlonly 2012 Piotr Esden-Tempski +@author @htmlonly © @endhtmlonly 2010 +Thomas Otto +@author @htmlonly © @endhtmlonly 2012 +Piotr Esden-Tempski */ @@ -27,7 +29,7 @@ /**@{*/ -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DMA.H +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DMA.H The order of header inclusion is important. dma.h includes the device specific memorymap.h header before including this header file.*/ @@ -141,29 +143,36 @@ specific memorymap.h header before including this header file.*/ /* --- DMA_ISR values ------------------------------------------------------ */ /* --- DMA Interrupt Flag offset values ------------------------------------- */ -/* These are based on every interrupt flag and flag clear being at the same relative location */ -/** @defgroup dma_if_offset DMA Interrupt Flag Offsets within channel flag group. +/* These are based on every interrupt flag and flag clear being at the same + * relative location + */ +/** @defgroup dma_if_offset DMA Interrupt Flag Offsets within channel flag +group. @ingroup dma_defines @{*/ /** Transfer Error Interrupt Flag */ -#define DMA_TEIF (1 << 3) +#define DMA_TEIF (1 << 3) /** Half Transfer Interrupt Flag */ -#define DMA_HTIF (1 << 2) +#define DMA_HTIF (1 << 2) /** Transfer Complete Interrupt Flag */ -#define DMA_TCIF (1 << 1) +#define DMA_TCIF (1 << 1) /** Global Interrupt Flag */ -#define DMA_GIF (1 << 0) +#define DMA_GIF (1 << 0) /**@}*/ -/* Offset within interrupt status register to start of channel interrupt flag field */ -#define DMA_FLAG_OFFSET(channel) (4*(channel - 1)) -#define DMA_FLAGS (DMA_TEIF | DMA_TCIF | DMA_HTIF | DMA_GIF) -#define DMA_ISR_MASK(channel) DMA_FLAGS << DMA_FLAG_OFFSET(channel) +/* Offset within interrupt status register to start of channel interrupt flag + * field + */ +#define DMA_FLAG_OFFSET(channel) (4*(channel - 1)) +#define DMA_FLAGS (DMA_TEIF | DMA_TCIF | DMA_HTIF | \ + DMA_GIF) +#define DMA_ISR_MASK(channel) (DMA_FLAGS << DMA_FLAG_OFFSET(channel)) /* TEIF: Transfer error interrupt flag */ -#define DMA_ISR_TEIF_BIT DMA_TEIF -#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << (DMA_FLAG_OFFSET(channel))) +#define DMA_ISR_TEIF_BIT DMA_TEIF +#define DMA_ISR_TEIF(channel) (DMA_ISR_TEIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) #define DMA_ISR_TEIF1 DMA_ISR_TEIF(DMA_CHANNEL1) #define DMA_ISR_TEIF2 DMA_ISR_TEIF(DMA_CHANNEL2) @@ -174,8 +183,9 @@ specific memorymap.h header before including this header file.*/ #define DMA_ISR_TEIF7 DMA_ISR_TEIF(DMA_CHANNEL7) /* HTIF: Half transfer interrupt flag */ -#define DMA_ISR_HTIF_BIT DMA_HTIF -#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << (DMA_FLAG_OFFSET(channel))) +#define DMA_ISR_HTIF_BIT DMA_HTIF +#define DMA_ISR_HTIF(channel) (DMA_ISR_HTIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) #define DMA_ISR_HTIF1 DMA_ISR_HTIF(DMA_CHANNEL1) #define DMA_ISR_HTIF2 DMA_ISR_HTIF(DMA_CHANNEL2) @@ -186,8 +196,9 @@ specific memorymap.h header before including this header file.*/ #define DMA_ISR_HTIF7 DMA_ISR_HTIF(DMA_CHANNEL7) /* TCIF: Transfer complete interrupt flag */ -#define DMA_ISR_TCIF_BIT DMA_TCIF -#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << (DMA_FLAG_OFFSET(channel))) +#define DMA_ISR_TCIF_BIT DMA_TCIF +#define DMA_ISR_TCIF(channel) (DMA_ISR_TCIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) #define DMA_ISR_TCIF1 DMA_ISR_TCIF(DMA_CHANNEL1) #define DMA_ISR_TCIF2 DMA_ISR_TCIF(DMA_CHANNEL2) @@ -199,7 +210,8 @@ specific memorymap.h header before including this header file.*/ /* GIF: Global interrupt flag */ #define DMA_ISR_GIF_BIT DMA_GIF -#define DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << (DMA_FLAG_OFFSET(channel))) +#define DMA_ISR_GIF(channel) (DMA_ISR_GIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) #define DMA_ISR_GIF1 DMA_ISR_GIF(DMA_CHANNEL1) #define DMA_ISR_GIF2 DMA_ISR_GIF(DMA_CHANNEL2) @@ -212,8 +224,9 @@ specific memorymap.h header before including this header file.*/ /* --- DMA_IFCR values ----------------------------------------------------- */ /* CTEIF: Transfer error clear */ -#define DMA_IFCR_CTEIF_BIT DMA_TEIF -#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << (DMA_FLAG_OFFSET(channel))) +#define DMA_IFCR_CTEIF_BIT DMA_TEIF +#define DMA_IFCR_CTEIF(channel) (DMA_IFCR_CTEIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF(DMA_CHANNEL1) #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF(DMA_CHANNEL2) @@ -224,8 +237,9 @@ specific memorymap.h header before including this header file.*/ #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF(DMA_CHANNEL7) /* CHTIF: Half transfer clear */ -#define DMA_IFCR_CHTIF_BIT DMA_HTIF -#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << (DMA_FLAG_OFFSET(channel))) +#define DMA_IFCR_CHTIF_BIT DMA_HTIF +#define DMA_IFCR_CHTIF(channel) (DMA_IFCR_CHTIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF(DMA_CHANNEL1) #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF(DMA_CHANNEL2) @@ -236,8 +250,9 @@ specific memorymap.h header before including this header file.*/ #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF(DMA_CHANNEL7) /* CTCIF: Transfer complete clear */ -#define DMA_IFCR_CTCIF_BIT DMA_TCIF -#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << (DMA_FLAG_OFFSET(channel))) +#define DMA_IFCR_CTCIF_BIT DMA_TCIF +#define DMA_IFCR_CTCIF(channel) (DMA_IFCR_CTCIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF(DMA_CHANNEL1) #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF(DMA_CHANNEL2) @@ -248,8 +263,9 @@ specific memorymap.h header before including this header file.*/ #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF(DMA_CHANNEL7) /* CGIF: Global interrupt clear */ -#define DMA_IFCR_CGIF_BIT DMA_GIF -#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << (DMA_FLAG_OFFSET(channel))) +#define DMA_IFCR_CGIF_BIT DMA_GIF +#define DMA_IFCR_CGIF(channel) (DMA_IFCR_CGIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF(DMA_CHANNEL1) #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF(DMA_CHANNEL2) @@ -260,8 +276,9 @@ specific memorymap.h header before including this header file.*/ #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF(DMA_CHANNEL7) /* Clear interrupts mask */ -#define DMA_IFCR_CIF_BIT 0xF -#define DMA_IFCR_CIF(channel) (DMA_IFCR_CIF_BIT << (DMA_FLAG_OFFSET(channel))) +#define DMA_IFCR_CIF_BIT 0xF +#define DMA_IFCR_CIF(channel) (DMA_IFCR_CIF_BIT << \ + (DMA_FLAG_OFFSET(channel))) #define DMA_IFCR_CIF1 DMA_IFCR_CIF(DMA_CHANNEL1) #define DMA_IFCR_CIF2 DMA_IFCR_CIF(DMA_CHANNEL2) diff --git a/include/libopencm3/stm32/common/dma_common_f24.h b/include/libopencm3/stm32/common/dma_common_f24.h index 4915f621..832eedce 100644 --- a/include/libopencm3/stm32/common/dma_common_f24.h +++ b/include/libopencm3/stm32/common/dma_common_f24.h @@ -1,7 +1,9 @@ /** @addtogroup dma_defines -@author @htmlonly © @endhtmlonly 2011 Fergus Noble -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies +@author @htmlonly © @endhtmlonly 2011 +Fergus Noble +@author @htmlonly © @endhtmlonly 2012 +Ken Sarkies */ /* @@ -24,7 +26,7 @@ * along with this library. If not, see . */ -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DMA.H +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA DMA.H The order of header inclusion is important. dma.h includes the device specific memorymap.h header before including this header file.*/ @@ -152,7 +154,8 @@ specific memorymap.h header before including this header file.*/ #define DMA2_S7NDTR DMA2_SNDTR(7) /* DMA Stream x peripheral address register (DMA_SxPAR) */ -#define DMA_SPAR(port, n) *(volatile void **)(DMA_STREAM(port, n) + 0x08) +#define DMA_SPAR(port, n) (*(volatile void **)\ + (DMA_STREAM(port, n) + 0x08)) #define DMA1_SPAR(n) DMA_SPAR(DMA1, n) #define DMA2_SPAR(n) DMA_SPAR(DMA2, n) @@ -175,7 +178,8 @@ specific memorymap.h header before including this header file.*/ #define DMA2_S7PAR DMA2_SPAR(7) /* DMA Stream x memory address 0 register (DMA_SxM0AR) */ -#define DMA_SM0AR(port, n) *(volatile void **)(DMA_STREAM(port, n) + 0x0c) +#define DMA_SM0AR(port, n) (*(volatile void **) \ + (DMA_STREAM(port, n) + 0x0c)) #define DMA1_SM0AR(n) DMA_SM0AR(DMA1, n) #define DMA2_SM0AR(n) DMA_SM0AR(DMA2, n) @@ -198,7 +202,8 @@ specific memorymap.h header before including this header file.*/ #define DMA2_S7M0AR DMA2_SM0AR(7) /* DMA Stream x memory address 1 register (DMA_SxM1AR) */ -#define DMA_SM1AR(port, n) *(volatile void **)(DMA_STREAM(port, n) + 0x10) +#define DMA_SM1AR(port, n) (*(volatile void **)\ + (DMA_STREAM(port, n) + 0x10)) #define DMA1_SM1AR(n) DMA_SM1AR(DMA1, n) #define DMA2_SM1AR(n) DMA_SM1AR(DMA2, n) @@ -252,21 +257,24 @@ being at the same relative location */ @{*/ /** Transfer Complete Interrupt Flag */ -#define DMA_TCIF (1 << 5) +#define DMA_TCIF (1 << 5) /** Half Transfer Interrupt Flag */ -#define DMA_HTIF (1 << 4) +#define DMA_HTIF (1 << 4) /** Transfer Error Interrupt Flag */ -#define DMA_TEIF (1 << 3) +#define DMA_TEIF (1 << 3) /** Direct Mode Error Interrupt Flag */ -#define DMA_DMEIF (1 << 2) +#define DMA_DMEIF (1 << 2) /** FIFO Error Interrupt Flag */ -#define DMA_FEIF (1 << 0) +#define DMA_FEIF (1 << 0) /**@}*/ -/* Offset within interrupt status register to start of stream interrupt flag field */ -#define DMA_ISR_OFFSET(stream) (6*(stream & 0x01)+16*((stream & 0x02) >> 1)) -#define DMA_ISR_FLAGS (DMA_TCIF | DMA_HTIF | DMA_TEIF | DMA_DMEIF | DMA_FEIF) -#define DMA_ISR_MASK(stream) DMA_ISR_FLAGS << DMA_ISR_OFFSET(stream) +/* Offset within interrupt status register to start of stream interrupt flag + * field + */ +#define DMA_ISR_OFFSET(stream) (6*(stream & 0x01)+16*((stream & 0x02) >> 1)) +#define DMA_ISR_FLAGS (DMA_TCIF | DMA_HTIF | DMA_TEIF | DMA_DMEIF | \ + DMA_FEIF) +#define DMA_ISR_MASK(stream) (DMA_ISR_FLAGS << DMA_ISR_OFFSET(stream)) /* --- DMA_LISR values ----------------------------------------------------- */ @@ -560,8 +568,8 @@ being at the same relative location */ BEGIN_DECLS /* - * Note: The F2 and F4 series have a completely new DMA peripheral with different - * configuration options. + * Note: The F2 and F4 series have a completely new DMA peripheral with + * different configuration options. */ void dma_stream_reset(u32 dma, u8 stream); diff --git a/include/libopencm3/stm32/common/flash_common_f24.h b/include/libopencm3/stm32/common/flash_common_f24.h index 587691eb..ca05d517 100644 --- a/include/libopencm3/stm32/common/flash_common_f24.h +++ b/include/libopencm3/stm32/common/flash_common_f24.h @@ -22,7 +22,7 @@ * For details see: * PM0081 Programming manual: STM32F40xxx and STM32F41xxx Flash programming * September 2011, Doc ID 018520 Rev 1 - * http://www.st.com/st-web-ui/static/active/en/resource/technical/document/programming_manual/DM00023388.pdf + * http://goo.gl/3ylKe */ /** @cond */ @@ -145,7 +145,7 @@ void flash_program_double_word(u32 address, u64 data); void flash_program_word(u32 address, u32 data); void flash_program_half_word(u32 address, u16 data); void flash_program_byte(u32 address, u8 data); -void flash_program(u32 address, u8* data, u32 len); +void flash_program(u32 address, u8 *data, u32 len); void flash_wait_for_last_operation(void); void flash_program_option_bytes(u32 data); @@ -154,7 +154,7 @@ END_DECLS #endif /** @cond */ #else -#warning "flash_common_f24.h should not be included explicitly, only via flash.h" +#warning "flash_common_f24.h should not be included direcitly, only via flash.h" #endif /** @endcond */ diff --git a/include/libopencm3/stm32/common/gpio_common_all.h b/include/libopencm3/stm32/common/gpio_common_all.h index 862a7379..a9fed84e 100644 --- a/include/libopencm3/stm32/common/gpio_common_all.h +++ b/include/libopencm3/stm32/common/gpio_common_all.h @@ -1,7 +1,9 @@ /** @addtogroup gpio_defines -@author @htmlonly © @endhtmlonly 2011 Fergus Noble -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies +@author @htmlonly © @endhtmlonly 2011 +Fergus Noble +@author @htmlonly © @endhtmlonly 2012 +Ken Sarkies */ @@ -25,12 +27,12 @@ * along with this library. If not, see . */ -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H The order of header inclusion is important. gpio.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ -#if defined (LIBOPENCM3_GPIO_H) || defined (LIBOPENCM3_GPIO_COMMON_F24_H) +#if defined(LIBOPENCM3_GPIO_H) || defined(LIBOPENCM3_GPIO_COMMON_F24_H) /** @endcond */ #ifndef LIBOPENCM3_GPIO_COMMON_ALL_H #define LIBOPENCM3_GPIO_COMMON_ALL_H diff --git a/include/libopencm3/stm32/common/gpio_common_f24.h b/include/libopencm3/stm32/common/gpio_common_f24.h index ae50b984..9f0e3e24 100644 --- a/include/libopencm3/stm32/common/gpio_common_f24.h +++ b/include/libopencm3/stm32/common/gpio_common_f24.h @@ -1,7 +1,9 @@ /** @addtogroup gpio_defines -@author @htmlonly © @endhtmlonly 2011 Fergus Noble -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies +@author @htmlonly © @endhtmlonly 2011 +Fergus Noble +@author @htmlonly © @endhtmlonly 2012 +Ken Sarkies */ /* @@ -24,7 +26,7 @@ * along with this library. If not, see . */ -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA GPIO.H The order of header inclusion is important. gpio.h includes the device specific memorymap.h header before including this header file.*/ @@ -278,10 +280,10 @@ specific memorymap.h header before including this header file.*/ BEGIN_DECLS /* - * Note: The F2 and F4 series have a completely new GPIO peripheral with different - * configuration options. Here we implement a different API partly to more - * closely match the peripheral capabilities and also to deliberately break - * compatibility with old F1 code so there is no confusion with similar + * Note: The F2 and F4 series have a completely new GPIO peripheral with + * different configuration options. Here we implement a different API partly to + * more closely match the peripheral capabilities and also to deliberately + * break compatibility with old F1 code so there is no confusion with similar * sounding functions that have very different functionality. */ diff --git a/include/libopencm3/stm32/common/hash_common_f24.h b/include/libopencm3/stm32/common/hash_common_f24.h index 8614ed21..0643f9d0 100644 --- a/include/libopencm3/stm32/common/hash_common_f24.h +++ b/include/libopencm3/stm32/common/hash_common_f24.h @@ -1,6 +1,7 @@ /** @addtogroup hash_defines -@author @htmlonly © @endhtmlonly 2013 Mikhail Avkhimenia +@author @htmlonly © @endhtmlonly 2013 +Mikhail Avkhimenia */ @@ -38,32 +39,32 @@ @ingroup STM32F_hash_defines @{*/ -#define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400) +#define HASH_BASE (PERIPH_BASE_AHB2 + 0x60400) #define HASH HASH_BASE /**@}*/ /* --- HASH registers ------------------------------------------------------ */ /* HASH control register (HASH_CR) */ -#define HASH_CR MMIO32(HASH + 0x00) +#define HASH_CR MMIO32(HASH + 0x00) /* HASH data input register (HASH_DIR) */ -#define HASH_DIN MMIO32(HASH + 0x04) +#define HASH_DIN MMIO32(HASH + 0x04) /* HASH start register (HASH_STR) */ -#define HASH_STR MMIO32(HASH + 0x08) +#define HASH_STR MMIO32(HASH + 0x08) /* HASH digest registers (HASH_HR[5]) */ -#define HASH_HR ((volatile uint32_t*)(HASH + 0x0C)) //x5 +#define HASH_HR ((volatile uint32_t*)(HASH + 0x0C)) /* x5 */ /* HASH interrupt enable register (HASH_IMR) */ -#define HASH_IMR MMIO32(HASH + 0x20) +#define HASH_IMR MMIO32(HASH + 0x20) /* HASH status register (HASH_SR) */ -#define HASH_SR MMIO32(HASH + 0x28) +#define HASH_SR MMIO32(HASH + 0x28) /* HASH context swap registers (HASH_CSR[51]) */ -#define HASH_CSR ((volatile uint32_t*)(HASH + 0xF8)) //x51 +#define HASH_CSR ((volatile uint32_t*)(HASH + 0xF8)) /* x51 */ /* --- HASH_CR values ------------------------------------------------------ */ @@ -127,7 +128,8 @@ /* --- HASH_STR values ----------------------------------------------------- */ -/* NBLW: Number of valid bits in the last word of the message in the bit string */ +/* NBLW: Number of valid bits in the last word of the message in the bit string + */ #define HASH_STR_NBW (31 << 0) /* DCAL: Digest calculation */ @@ -155,7 +157,7 @@ /* BUSY: Busy bit */ #define HASH_SR_BUSY (1 << 3) -/* --- HASH function prototypes ------------------------------------------------------- */ +/* --- HASH function prototypes -------------------------------------------- */ BEGIN_DECLS diff --git a/include/libopencm3/stm32/common/i2c_common_all.h b/include/libopencm3/stm32/common/i2c_common_all.h index 8381ae06..dad6a86a 100644 --- a/include/libopencm3/stm32/common/i2c_common_all.h +++ b/include/libopencm3/stm32/common/i2c_common_all.h @@ -23,12 +23,12 @@ * along with this library. If not, see . */ -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H The order of header inclusion is important. i2c.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ -#if defined (LIBOPENCM3_I2C_H) || defined (LIBOPENCM3_I2C_COMMON_F24_H) +#if defined(LIBOPENCM3_I2C_H) || defined(LIBOPENCM3_I2C_COMMON_F24_H) /** @endcond */ #ifndef LIBOPENCM3_I2C_COMMON_ALL_H #define LIBOPENCM3_I2C_COMMON_ALL_H diff --git a/include/libopencm3/stm32/common/i2c_common_f24.h b/include/libopencm3/stm32/common/i2c_common_f24.h index f9a41738..a056114c 100644 --- a/include/libopencm3/stm32/common/i2c_common_f24.h +++ b/include/libopencm3/stm32/common/i2c_common_f24.h @@ -1,6 +1,7 @@ /** @addtogroup i2c_defines -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies +@author @htmlonly © @endhtmlonly 2012 +Ken Sarkies */ @@ -23,7 +24,7 @@ * along with this library. If not, see . */ -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA I2C.H The order of header inclusion is important. i2c.h includes the device specific memorymap.h header before including this header file.*/ diff --git a/include/libopencm3/stm32/common/iwdg_common_all.h b/include/libopencm3/stm32/common/iwdg_common_all.h index d21b3540..9c565704 100644 --- a/include/libopencm3/stm32/common/iwdg_common_all.h +++ b/include/libopencm3/stm32/common/iwdg_common_all.h @@ -22,7 +22,7 @@ * along with this library. If not, see . */ -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA IWDG.H +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA IWDG.H The order of header inclusion is important. iwdg.h includes the device specific memorymap.h header before including this header file.*/ diff --git a/include/libopencm3/stm32/common/pwr_common_all.h b/include/libopencm3/stm32/common/pwr_common_all.h index b8866447..7675f542 100644 --- a/include/libopencm3/stm32/common/pwr_common_all.h +++ b/include/libopencm3/stm32/common/pwr_common_all.h @@ -23,7 +23,7 @@ * along with this library. If not, see . */ -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA PWR.H +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA PWR.H The order of header inclusion is important. pwr.h includes the device specific memorymap.h header before including this header file.*/ diff --git a/include/libopencm3/stm32/common/rng_common_f24.h b/include/libopencm3/stm32/common/rng_common_f24.h index 003e3022..0fa6c2f6 100644 --- a/include/libopencm3/stm32/common/rng_common_f24.h +++ b/include/libopencm3/stm32/common/rng_common_f24.h @@ -16,7 +16,7 @@ * along with this library. If not, see . */ -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA RNG.H +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA RNG.H The order of header inclusion is important. rng.h includes the device specific memorymap.h header before including this header file.*/ @@ -32,7 +32,7 @@ specific memorymap.h header before including this header file.*/ /* --- Random number generator registers ----------------------------------- */ /* Control register */ -#define RNG_CR MMIO32(RNG_BASE + 0x00) +#define RNG_CR MMIO32(RNG_BASE + 0x00) /* Status register */ #define RNG_SR MMIO32(RNG_BASE + 0x04) diff --git a/include/libopencm3/stm32/common/rtc_common_bcd.h b/include/libopencm3/stm32/common/rtc_common_bcd.h index a31711a2..97c643e3 100644 --- a/include/libopencm3/stm32/common/rtc_common_bcd.h +++ b/include/libopencm3/stm32/common/rtc_common_bcd.h @@ -30,7 +30,7 @@ * only support a subset. */ -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA RTC.H +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA RTC.H The order of header inclusion is important. rtc.h includes the device specific memorymap.h header before including this header file.*/ @@ -102,7 +102,8 @@ specific memorymap.h header before including this header file.*/ /* RTC time register (RTC_TR) ----------------------------------- */ -/* Note: Bits [31:23], 15, and 7 are reserved, and must be kept at reset value. */ +/* Note: Bits [31:23], 15, and 7 are reserved, and must be kept at reset value. + */ #define RTC_TR_PM (1 << 22) /* AM/PM notation */ #define RTC_TR_HT_SHIFT (20) /* Hour tens in BCD format shift */ #define RTC_TR_HT_MASK (0x3) /* Hour tens in BCD format mask */ @@ -118,7 +119,8 @@ specific memorymap.h header before including this header file.*/ #define RTC_TR_SU_MASK (0xf) /* Second units in BCD format mask */ /* RTC date register (RTC_DR) ----------------------------------- */ -/* Note: Bits [31:24] and [7:6] are reserved, and must be kept at reset value. */ +/* Note: Bits [31:24] and [7:6] are reserved, and must be kept at reset value. + */ #define RTC_DR_YT_SHIFT (20) /* Year tens in BCD format shift */ #define RTC_DR_YT_MASK (0xf) /* Year tens in BCD format mask */ #define RTC_DR_YU_SHIFT (16) /* Year units in BCD format shift */ @@ -136,12 +138,18 @@ specific memorymap.h header before including this header file.*/ /* RTC control register (RTC_CR) -------------------------------- */ /* Note: Bits [31:24] are reserved, and must be kept at reset value. */ -/* Note: Bits 7, 6 and 4 of this register can be written in initialization mode only (RTC_ISR/INITF = 1). */ -/* Note: Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1. */ +/* Note: Bits 7, 6 and 4 of this register can be written in initialization mode + * only (RTC_ISR/INITF = 1). + */ +/* Note: Bits 2 to 0 of this register can be written only when RTC_CR WUTE bit + * = 0 and RTC_ISR WUTWF bit = 1. + */ #define RTC_CR_COE (1<<23) /* RTC_CR_COE: Calibration output enable */ /* RTC_CR_OSEL: Output selection values */ -/* Note: These bits are used to select the flag to be routed to AFO_ALARM RTC output */ +/* Note: These bits are used to select the flag to be routed to AFO_ALARM RTC + * output + */ #define RTC_CR_OSEL_SHIFT 21 #define RTC_CR_OSEL_MASK (0x3) #define RTC_CR_OSEL_DISABLED (0x0) @@ -150,23 +158,34 @@ specific memorymap.h header before including this header file.*/ #define RTC_CR_OSEL_WAKEUP (0x3) #define RTC_CR_POL (1<<20) /* RTC_CR_POL: Output polarity */ -#define RTC_CR_COSEL (1<<19) /* RTC_CR_COSEL: Calibration output selection */ +#define RTC_CR_COSEL (1<<19) /* RTC_CR_COSEL: Calibration output + selection */ #define RTC_CR_BKP (1<<18) /* RTC_CR_BKP: Backup */ -#define RTC_CR_SUB1H (1<<17) /* RTC_CR_SUB1H: Subtract 1 hour (winter time change) */ -#define RTC_CR_ADD1H (1<<16) /* RTC_CR_ADD1H: Add 1 hour (summer time change) */ -#define RTC_CR_TSIE (1<<15) /* RTC_CR_TSIE: Timestamp interrupt enable */ -#define RTC_CR_WUTIE (1<<14) /* RTC_CR_WUTIE: Wakeup timer interrupt enable */ -#define RTC_CR_ALRBIE (1<<13) /* RTC_CR_ALRBIE: Alarm B interrupt enable */ -#define RTC_CR_ALRAIE (1<<12) /* RTC_CR_ALRAIE: Alarm A interrupt enable */ +#define RTC_CR_SUB1H (1<<17) /* RTC_CR_SUB1H: Subtract 1 hour + (winter time change) */ +#define RTC_CR_ADD1H (1<<16) /* RTC_CR_ADD1H: Add 1 hour (summer + time change) */ +#define RTC_CR_TSIE (1<<15) /* RTC_CR_TSIE: Timestamp interrupt + enable */ +#define RTC_CR_WUTIE (1<<14) /* RTC_CR_WUTIE: Wakeup timer + interrupt enable */ +#define RTC_CR_ALRBIE (1<<13) /* RTC_CR_ALRBIE: Alarm B interrupt + enable */ +#define RTC_CR_ALRAIE (1<<12) /* RTC_CR_ALRAIE: Alarm A interrupt + enable */ #define RTC_CR_TSE (1<<11) /* RTC_CR_TSE: Time stamp enable */ #define RTC_CR_WUTE (1<<10) /* RTC_CR_WUTE: Wakeup timer enable */ #define RTC_CR_ALRBE (1<<9) /* RTC_CR_ALRBIE: Alarm B enable */ #define RTC_CR_ALRAE (1<<8) /* RTC_CR_ALRAE: Alarm A enable */ -#define RTC_CR_DCE (1<<7) /* RTC_CR_DCE: Course digital calibration enable */ +#define RTC_CR_DCE (1<<7) /* RTC_CR_DCE: Course digital + calibration enable */ #define RTC_CR_FMT (1<<6) /* RTC_CR_FMT: Hour format */ -#define RTC_CR_BYPSHAD (1<<5) /* RTC_CR_BYPSHAD: Bypass the shadow registers */ -#define RTC_CR_REFCKON (1<<4) /* RTC_CR_REFCKON: Reference clock detection enable */ -#define RTC_CR_TSEDGE (1<<3) /* RTC_CR_TSEDGE: Timestamp event active edge */ +#define RTC_CR_BYPSHAD (1<<5) /* RTC_CR_BYPSHAD: Bypass the shadow + registers */ +#define RTC_CR_REFCKON (1<<4) /* RTC_CR_REFCKON: Reference clock + detection enable */ +#define RTC_CR_TSEDGE (1<<3) /* RTC_CR_TSEDGE: Timestamp event + active edge */ /* RTC_CR_WUCKSEL: Wakeup clock selection */ #define RTC_CR_WUCLKSEL_SHIFT (0) @@ -181,8 +200,9 @@ specific memorymap.h header before including this header file.*/ /* RTC initialization and status register (RTC_ISR) ------------- */ /* Note: Bits [31:17] and [15] are reserved, and must be kept at reset value. */ /* Note: This register is write protected (except for RTC_ISR[13:8] bits). */ -#define RTC_ISR_RECALPF (1<<16) /* RECALPF: Recalibration pending flag */ -#define RTC_ISR_TAMP3F (1<<15) /* TAMP3F: TAMPER3 detection flag (not available on F4)*/ +#define RTC_ISR_RECALPF (1<<16) /* RECALPF: Recalib pending flag */ +#define RTC_ISR_TAMP3F (1<<15) /* TAMP3F: TAMPER3 detection flag + (not on F4)*/ #define RTC_ISR_TAMP2F (1<<14) /* TAMP2F: TAMPER2 detection flag */ #define RTC_ISR_TAMP1F (1<<13) /* TAMP1F: TAMPER detection flag */ #define RTC_ISR_TSOVF (1<<12) /* TSOVF: Timestamp overflow flag */ @@ -192,21 +212,21 @@ specific memorymap.h header before including this header file.*/ #define RTC_ISR_ALRAF (1<<8) /* ALRAF: Alarm A flag */ #define RTC_ISR_INIT (1<<7) /* INIT: Initialization mode */ #define RTC_ISR_INITF (1<<6) /* INITF: Initialization flag */ -#define RTC_ISR_RSF (1<<5) /* RSF: Registers synchronization flag */ -#define RTC_ISR_INITS (1<<4) /* INITS: Initialization status flag */ +#define RTC_ISR_RSF (1<<5) /* RSF: Registers sync flag */ +#define RTC_ISR_INITS (1<<4) /* INITS: Init status flag */ #define RTC_ISR_SHPF (1<<3) /* SHPF: Shift operation pending */ #define RTC_ISR_WUTWF (1<<2) /* WUTWF: Wakeup timer write flag */ #define RTC_ISR_ALRBWF (1<<1) /* ALRBWF: Alarm B write flag */ #define RTC_ISR_ALRAWF (1<<0) /* ALRAWF: Alarm A write flag */ /* RTC prescaler register (RTC_PRER) ---------------------------- */ -#define RTC_PRER_PREDIV_A_SHIFT (16) /* Asynchronous prescaler factor shift */ -#define RTC_PRER_PREDIV_A_MASK (0x7f) /* Asynchronous prescaler factor mask */ -#define RTC_PRER_PREDIV_S_SHIFT (0) /* Synchronous prescaler factor shift */ -#define RTC_PRER_PREDIV_S_MASK (0x7fff) /* Synchronous prescaler factor mask */ +#define RTC_PRER_PREDIV_A_SHIFT (16) /* Async prescaler factor shift */ +#define RTC_PRER_PREDIV_A_MASK (0x7f) /* Async prescaler factor mask */ +#define RTC_PRER_PREDIV_S_SHIFT (0) /* Sync prescaler factor shift */ +#define RTC_PRER_PREDIV_S_MASK (0x7fff) /* Sync prescaler factor mask */ /* RTC calibration register (RTC_CALIBR) ------------------------ */ -// FIXME - TODO +/* FIXME - TODO */ /* RTC Alarm register ------------------------------------------- */ /* Note: Applies to RTC_ALRMAR and RTC_ALRMBR */ @@ -234,7 +254,7 @@ specific memorymap.h header before including this header file.*/ #define RTC_ALRMXR_SU_MASK (0xf) /* RTC shift control register (RTC_SHIFTR) */ -// FIXME - TODO +/* FIXME - TODO */ /* RTC time stamp time register (RTC_TSTR) ---------------------- */ #define RTC_TSTR_PM (1<<22) @@ -263,7 +283,7 @@ specific memorymap.h header before including this header file.*/ #define RTC_TSDR_DU_MASK (0xf) /* RTC calibration register (RTC_CALR) -------------------------- */ -// FIXME - TODO +/* FIXME - TODO */ /* RTC tamper and alternate function configuration register (RTC_TAFCR) --- */ #define RTC_TAFCR_ALARMOUTTYPE (1<<18) @@ -304,7 +324,7 @@ specific memorymap.h header before including this header file.*/ #define RTC_TAFCR_TAMP1E (1<<0) /* RTC alarm X sub second register */ -// FIXME - TODO +/* FIXME - TODO */ diff --git a/include/libopencm3/stm32/common/spi_common_all.h b/include/libopencm3/stm32/common/spi_common_all.h index 0a510f3f..4141a8fa 100644 --- a/include/libopencm3/stm32/common/spi_common_all.h +++ b/include/libopencm3/stm32/common/spi_common_all.h @@ -23,12 +23,12 @@ * along with this library. If not, see . */ -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H The order of header inclusion is important. spi.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ -#if defined (LIBOPENCM3_SPI_H) || defined (LIBOPENCM3_SPI_COMMON_F24_H) +#if defined(LIBOPENCM3_SPI_H) || defined(LIBOPENCM3_SPI_COMMON_F24_H) /** @endcond */ #ifndef LIBOPENCM3_SPI_COMMON_ALL_H #define LIBOPENCM3_SPI_COMMON_ALL_H diff --git a/include/libopencm3/stm32/common/spi_common_f24.h b/include/libopencm3/stm32/common/spi_common_f24.h index a31c5c47..2fc45ed9 100644 --- a/include/libopencm3/stm32/common/spi_common_f24.h +++ b/include/libopencm3/stm32/common/spi_common_f24.h @@ -22,7 +22,7 @@ * along with this library. If not, see . */ -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA SPI.H The order of header inclusion is important. spi.h includes the device specific memorymap.h header before including this header file.*/ diff --git a/include/libopencm3/stm32/common/timer_common_all.h b/include/libopencm3/stm32/common/timer_common_all.h index 493d842e..a4741cf7 100644 --- a/include/libopencm3/stm32/common/timer_common_all.h +++ b/include/libopencm3/stm32/common/timer_common_all.h @@ -25,12 +25,12 @@ /**@{*/ -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA TIMER.H +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA TIMER.H The order of header inclusion is important. timer.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ -#if defined (LIBOPENCM3_TIMER_H) || defined (LIBOPENCM3_TIMER_COMMON_F24_H) +#if defined(LIBOPENCM3_TIMER_H) || defined(LIBOPENCM3_TIMER_COMMON_F24_H) /** @endcond */ #ifndef LIBOPENCM3_TIMER_COMMON_H #define LIBOPENCM3_TIMER_COMMON_H @@ -434,14 +434,19 @@ level. */ /** Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the complementary input. */ #define TIM_SMCR_SMS_EM3 (0x3 << 0) -/** Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter -and generates an update of the registers. */ +/** Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes + * the counter and generates an update of the registers. + */ #define TIM_SMCR_SMS_RM (0x4 << 0) -/** Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. */ +/** Gated Mode - The counter clock is enabled when the trigger input (TRGI) is + * high. + */ #define TIM_SMCR_SMS_GM (0x5 << 0) /** Trigger Mode - The counter starts at a rising edge of the trigger TRGI. */ #define TIM_SMCR_SMS_TM (0x6 << 0) -/** External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. */ +/** External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock + * the counter. + */ #define TIM_SMCR_SMS_ECM1 (0x7 << 0) #define TIM_SMCR_SMS_MASK (0x7 << 0) /**@}*/ @@ -936,7 +941,7 @@ and generates an update of the registers. */ /** Output Compare channel designators */ enum tim_oc_id { - TIM_OC1=0, + TIM_OC1 = 0, TIM_OC1N, TIM_OC2, TIM_OC2N, @@ -968,8 +973,8 @@ enum tim_ic_id { /** Input Capture input filter. The frequency used to sample the input and the number of events needed to validate an output transition. -TIM_IC_CK_INT_N_x No division from the Deadtime and Sampling Clock frequency (DTF), -filter length x +TIM_IC_CK_INT_N_x No division from the Deadtime and Sampling Clock frequency +(DTF), filter length x TIM_IC_DTF_DIV_y_N_x Division by y from the DTF, filter length x */ enum tim_ic_filter { @@ -1020,7 +1025,7 @@ enum tim_et_pol { TIM_ET_FALLING, }; -/* --- TIM function prototypes ------------------------------------------------------- */ +/* --- TIM function prototypes --------------------------------------------- */ BEGIN_DECLS @@ -1064,7 +1069,8 @@ void timer_enable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id); void timer_disable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id); void timer_set_oc_fast_mode(u32 timer_peripheral, enum tim_oc_id oc_id); void timer_set_oc_slow_mode(u32 timer_peripheral, enum tim_oc_id oc_id); -void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id, enum tim_oc_mode oc_mode); +void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id, + enum tim_oc_mode oc_mode); void timer_enable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id); void timer_disable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id); void timer_set_oc_polarity_high(u32 timer_peripheral, enum tim_oc_id oc_id); @@ -1109,7 +1115,7 @@ END_DECLS #endif /** @cond */ #else -#warning "timer_common_all.h should not be included explicitly, only via timer.h" +#warning "timer_common_all.h should not be included directly, only via timer.h" #endif /** @endcond */ /**@}*/ diff --git a/include/libopencm3/stm32/common/timer_common_f24.h b/include/libopencm3/stm32/common/timer_common_f24.h index b42960c5..b929d564 100644 --- a/include/libopencm3/stm32/common/timer_common_f24.h +++ b/include/libopencm3/stm32/common/timer_common_f24.h @@ -23,7 +23,7 @@ * along with this library. If not, see . */ -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA TIMER.H +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA TIMER.H The order of header inclusion is important. timer.h includes the device specific memorymap.h header before including this header file.*/ @@ -106,7 +106,7 @@ END_DECLS #endif /** @cond */ #else -#warning "timer_common_f24.h should not be included explicitly, only via timer.h" +#warning "timer_common_f24.h should not be included directly, only via timer.h" #endif /** @endcond */ diff --git a/include/libopencm3/stm32/common/usart_common_all.h b/include/libopencm3/stm32/common/usart_common_all.h index 373e0de1..b412efcf 100644 --- a/include/libopencm3/stm32/common/usart_common_all.h +++ b/include/libopencm3/stm32/common/usart_common_all.h @@ -25,12 +25,12 @@ /**@{*/ -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA USART.H +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA USART.H The order of header inclusion is important. usart.h includes the device specific memorymap.h header before including this header file.*/ /** @cond */ -#if defined (LIBOPENCM3_USART_H) || defined (LIBOPENCM3_USART_COMMON_F24_H) +#if defined(LIBOPENCM3_USART_H) || defined(LIBOPENCM3_USART_COMMON_F24_H) /** @endcond */ #ifndef LIBOPENCM3_USART_COMMON_ALL_H #define LIBOPENCM3_USART_COMMON_ALL_H @@ -324,9 +324,9 @@ specific memorymap.h header before including this header file.*/ @{*/ #define USART_STOPBITS_1 USART_CR2_STOPBITS_1 /* 1 stop bit */ -#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* 0.5 stop bits */ +#define USART_STOPBITS_0_5 USART_CR2_STOPBITS_0_5 /* .5 stop bit */ #define USART_STOPBITS_2 USART_CR2_STOPBITS_2 /* 2 stop bits */ -#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bits */ +#define USART_STOPBITS_1_5 USART_CR2_STOPBITS_1_5 /* 1.5 stop bit*/ /**@}*/ /* CR3_CTSE/CR3_RTSE combined values */ @@ -378,7 +378,7 @@ END_DECLS #endif /** @cond */ #else -#warning "usart_common_all.h should not be included explicitly, only via usart.h" +#warning "usart_common_all.h should not be included directly, only via usart.h" #endif /** @endcond */ /**@}*/ diff --git a/include/libopencm3/stm32/common/usart_common_f24.h b/include/libopencm3/stm32/common/usart_common_f24.h index 6800230b..5637a522 100644 --- a/include/libopencm3/stm32/common/usart_common_f24.h +++ b/include/libopencm3/stm32/common/usart_common_f24.h @@ -24,7 +24,7 @@ * along with this library. If not, see . */ -/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA USART.H +/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA USART.H The order of header inclusion is important. usart.h includes the device specific memorymap.h header before including this header file.*/ @@ -76,7 +76,7 @@ specific memorymap.h header before including this header file.*/ #endif /** @cond */ #else -#warning "usart_common_f24.h should not be included explicitly, only via usart.h" +#warning "usart_common_f24.h should not be included directly, only via usart.h" #endif /** @endcond */ diff --git a/include/libopencm3/stm32/f1/adc.h b/include/libopencm3/stm32/f1/adc.h index 0550bfd3..cf6fd7c3 100644 --- a/include/libopencm3/stm32/f1/adc.h +++ b/include/libopencm3/stm32/f1/adc.h @@ -1,12 +1,14 @@ /** @defgroup adc_defines ADC Defines -@brief Defined Constants and Types for the STM32F1xx Analog to Digital Converters +@brief Defined Constants and Types for the STM32F1xx Analog to Digital +Converters @ingroup STM32F1xx_defines @version 1.0.0 -@author @htmlonly © @endhtmlonly 2009 Edward Cheeseman +@author @htmlonly © @endhtmlonly 2009 +Edward Cheeseman @date 18 August 2012 @@ -404,7 +406,8 @@ LGPL License Terms @ref lgpl_license /* The following are only valid for ADC1 and ADC2. */ /****************************************************************************/ /* ADC_CR2 JEXTSEL[2:0] ADC Injected Trigger Identifier for ADC1 and ADC2 */ -/** @defgroup adc_trigger_injected_12 ADC Injected Trigger Identifier for ADC1 and ADC2 +/** @defgroup adc_trigger_injected_12 ADC Injected Trigger Identifier for ADC1 +and ADC2 @ingroup adc_defines @{*/ @@ -677,7 +680,8 @@ void adc_reset_calibration(u32 adc); void adc_calibration(u32 adc); void adc_set_continuous_conversion_mode(u32 adc); void adc_set_single_conversion_mode(u32 adc); -void adc_on(u32 adc) LIBOPENCM3_DEPRECATED("will be removed in the first release"); +void adc_on(u32 adc) + LIBOPENCM3_DEPRECATED("will be removed in the first release"); void adc_off(u32 adc); void adc_set_sample_time(u32 adc, u8 channel, u8 time); void adc_set_sample_time_on_all_channels(u32 adc, u8 time); @@ -686,11 +690,16 @@ void adc_set_watchdog_low_threshold(u32 adc, u16 threshold); void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]); void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]); -void adc_set_continous_conversion_mode(u32 adc) LIBOPENCM3_DEPRECATED("change to adc_set_continuous_conversion_mode"); -void adc_set_conversion_time(u32 adc, u8 channel, u8 time) LIBOPENCM3_DEPRECATED("change to adc_set_sample_time"); -void adc_set_conversion_time_on_all_channels(u32 adc, u8 time) LIBOPENCM3_DEPRECATED("change to adc_set_sample_time_on_all_channels"); -void adc_enable_jeoc_interrupt(u32 adc) LIBOPENCM3_DEPRECATED("change to adc_enable_eoc_interrupt_injected"); -void adc_disable_jeoc_interrupt(u32 adc) LIBOPENCM3_DEPRECATED("change to adc_disable_eoc_interrupt_injected"); +void adc_set_continous_conversion_mode(u32 adc) + LIBOPENCM3_DEPRECATED("change to adc_set_continuous_conversion_mode"); +void adc_set_conversion_time(u32 adc, u8 channel, u8 time) + LIBOPENCM3_DEPRECATED("change to adc_set_sample_time"); +void adc_set_conversion_time_on_all_channels(u32 adc, u8 time) + LIBOPENCM3_DEPRECATED("change to adc_set_sample_time_on_all_channels"); +void adc_enable_jeoc_interrupt(u32 adc) + LIBOPENCM3_DEPRECATED("change to adc_enable_eoc_interrupt_injected"); +void adc_disable_jeoc_interrupt(u32 adc) + LIBOPENCM3_DEPRECATED("change to adc_disable_eoc_interrupt_injected"); END_DECLS #endif diff --git a/include/libopencm3/stm32/f1/crc.h b/include/libopencm3/stm32/f1/crc.h index f31d4dec..aed01280 100644 --- a/include/libopencm3/stm32/f1/crc.h +++ b/include/libopencm3/stm32/f1/crc.h @@ -1,6 +1,7 @@ /** @defgroup crc_defines CRC Defines -@brief libopencm3 Defined Constants and Types for the STM32F1xx CRC Generator +@brief libopencm3 Defined Constants and Types for the STM32F1xx CRC +Generator @ingroup STM32F1xx_defines diff --git a/include/libopencm3/stm32/f1/flash.h b/include/libopencm3/stm32/f1/flash.h index caa0268c..9c3de061 100644 --- a/include/libopencm3/stm32/f1/flash.h +++ b/include/libopencm3/stm32/f1/flash.h @@ -22,7 +22,7 @@ * For details see: * PM0075 programming manual: STM32F10xxx Flash programming * August 2010, Doc ID 17863 Rev 1 - * http://www.st.com/st-web-ui/static/active/en/resource/technical/document/programming_manual/CD00283419.pdf + * http://goo.gl/MuTiU */ #ifndef LIBOPENCM3_FLASH_H diff --git a/include/libopencm3/stm32/f1/gpio.h b/include/libopencm3/stm32/f1/gpio.h index fb6690c2..5211d631 100644 --- a/include/libopencm3/stm32/f1/gpio.h +++ b/include/libopencm3/stm32/f1/gpio.h @@ -497,26 +497,26 @@ LGPL License Terms @ref lgpl_license /* ETH GPIO */ #define GPIO_ETH_RX_DV_CRS_DV GPIO7 /* PA7 */ -#define GPIO_ETH_RXD0 GPIO4 /* PC4 */ +#define GPIO_ETH_RXD0 GPIO4 /* PC4 */ #define GPIO_ETH_RXD1 GPIO5 /* PC5 */ #define GPIO_ETH_RXD2 GPIO0 /* PB0 */ #define GPIO_ETH_RXD3 GPIO1 /* PB1 */ #define GPIO_ETH_RE_RX_DV_CRS_DV GPIO8 /* PD8 */ -#define GPIO_ETH_RE_RXD0 GPIO9 /* PD9 */ +#define GPIO_ETH_RE_RXD0 GPIO9 /* PD9 */ #define GPIO_ETH_RE_RXD1 GPIO10 /* PD10 */ #define GPIO_ETH_RE_RXD2 GPIO11 /* PD11 */ #define GPIO_ETH_RE_RXD3 GPIO12 /* PD12 */ /* ETH BANK */ #define GPIO_BANK_ETH_RX_DV_CRS_DV GPIOA /* PA7 */ -#define GPIO_BANK_ETH_RXD0 GPIOC /* PC4 */ +#define GPIO_BANK_ETH_RXD0 GPIOC /* PC4 */ #define GPIO_BANK_ETH_RXD1 GPIOC /* PC5 */ #define GPIO_BANK_ETH_RXD2 GPIOB /* PB0 */ #define GPIO_BANK_ETH_RXD3 GPIOB /* PB1 */ #define GPIO_BANK_ETH_RE_RX_DV_CRS_DV GPIOD /* PD8 */ -#define GPIO_BANK_ETH_RE_RXD0 GPIOD /* PD9 */ +#define GPIO_BANK_ETH_RE_RXD0 GPIOD /* PD9 */ #define GPIO_BANK_ETH_RE_RXD1 GPIOD /* PD10 */ #define GPIO_BANK_ETH_RE_RXD2 GPIOD /* PD11 */ #define GPIO_BANK_ETH_RE_RXD3 GPIOD /* PD12 */ @@ -729,28 +729,28 @@ Line Devices only @ingroup gpio_defines @{*/ -/* PTP_PPS_REMAP: *//** Ethernet PTP PPS remapping - * (only connectivity line devices) */ +/* PTP_PPS_REMAP: */ +/** Ethernet PTP PPS remapping (only connectivity line devices) */ #define AFIO_MAPR_PTP_PPS_REMAP (1 << 30) -/* TIM2ITR1_IREMAP: *//** TIM2 internal trigger 1 remapping - * (only connectivity line devices) */ +/* TIM2ITR1_IREMAP: */ +/** TIM2 internal trigger 1 remapping (only connectivity line devices) */ #define AFIO_MAPR_TIM2ITR1_IREMAP (1 << 29) -/* SPI3_REMAP: *//** SPI3/I2S3 remapping - * (only connectivity line devices) */ +/* SPI3_REMAP: */ +/** SPI3/I2S3 remapping (only connectivity line devices) */ #define AFIO_MAPR_SPI3_REMAP (1 << 28) -/* MII_REMAP: */ /** MII or RMII selection - * (only connectivity line devices) */ +/* MII_REMAP: */ +/** MII or RMII selection (only connectivity line devices) */ #define AFIO_MAPR_MII_RMII_SEL (1 << 23) -/* CAN2_REMAP: */ /** CAN2 I/O remapping - * (only connectivity line devices) */ +/* CAN2_REMAP: */ +/** CAN2 I/O remapping (only connectivity line devices) */ #define AFIO_MAPR_CAN2_REMAP (1 << 22) -/* ETH_REMAP: */ /** Ethernet MAC I/O remapping - * (only connectivity line devices) */ +/* ETH_REMAP: */ +/** Ethernet MAC I/O remapping (only connectivity line devices) */ #define AFIO_MAPR_ETH_REMAP (1 << 21) /**@}*/ @@ -763,9 +763,9 @@ Line Devices only @{*/ #define AFIO_MAPR_SWJ_MASK (0x7 << 24) -/** Full Serial Wire JTAG capability */ +/** Full Serial Wire JTAG capability */ #define AFIO_MAPR_SWJ_CFG_FULL_SWJ (0x0 << 24) -/** Full Serial Wire JTAG capability without JNTRST */ +/** Full Serial Wire JTAG capability without JNTRST */ #define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST (0x1 << 24) /** JTAG-DP disabled with SW-DP enabled */ #define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON (0x2 << 24) @@ -777,41 +777,60 @@ Line Devices only @ingroup gpio_defines @{*/ -/* ADC2_ETRGREG_REMAP: */ /** ADC2 external trigger regulator conversion remapping - * (only low-, medium-, high- and XL-densitiy devices) */ +/* ADC2_ETRGREG_REMAP: */ +/** + * ADC2 external trigger regulator conversion remapping + * (only low-, medium-, high- and XL-densitiy devices) + */ #define AFIO_MAPR_ADC2_ETRGREG_REMAP (1 << 20) -/* ADC2_ETRGINJ_REMAP: */ /** ADC2 external trigger injected conversion remapping - * (only low-, medium-, high- and XL-densitiy devices) */ +/* ADC2_ETRGINJ_REMAP: */ +/** + * ADC2 external trigger injected conversion remapping + * (only low-, medium-, high- and XL-densitiy devices) + */ #define AFIO_MAPR_ADC2_ETRGINJ_REMAP (1 << 19) -/* ADC1_ETRGREG_REMAP: */ /** ADC1 external trigger regulator conversion remapping - * (only low-, medium-, high- and XL-densitiy devices) */ +/* ADC1_ETRGREG_REMAP: */ +/** + * ADC1 external trigger regulator conversion remapping + * (only low-, medium-, high- and XL-densitiy devices) + */ #define AFIO_MAPR_ADC1_ETRGREG_REMAP (1 << 18) -/* ADC1_ETRGINJ_REMAP: */ /** ADC1 external trigger injected conversion remapping - * (only low-, medium-, high- and XL-densitiy devices) */ +/* ADC1_ETRGINJ_REMAP: */ +/** + * ADC1 external trigger injected conversion remapping + * (only low-, medium-, high- and XL-densitiy devices) + */ #define AFIO_MAPR_ADC1_ETRGINJ_REMAP (1 << 17) -/* TIM5CH4_IREMAP: */ /** TIM5 channel4 internal remap */ +/* TIM5CH4_IREMAP: */ +/** TIM5 channel4 internal remap */ #define AFIO_MAPR_TIM5CH4_IREMAP (1 << 16) -/* PD01_REMAP: */ /** Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +/* PD01_REMAP: */ +/** Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ #define AFIO_MAPR_PD01_REMAP (1 << 15) -/* TIM4_REMAP: */ /** TIM4 remapping */ +/* TIM4_REMAP: */ +/** TIM4 remapping */ #define AFIO_MAPR_TIM4_REMAP (1 << 12) -/* USART2_REMAP[1:0]: */ /** USART2 remapping */ +/* USART2_REMAP[1:0]: */ +/** USART2 remapping */ #define AFIO_MAPR_USART2_REMAP (1 << 3) -/* USART1_REMAP[1:0]: */ /** USART1 remapping */ +/* USART1_REMAP[1:0]: */ +/** USART1 remapping */ #define AFIO_MAPR_USART1_REMAP (1 << 2) -/* I2C1_REMAP[1:0]: */ /** I2C1 remapping */ +/* I2C1_REMAP[1:0]: */ +/** I2C1 remapping */ #define AFIO_MAPR_I2C1_REMAP (1 << 1) -/* SPI1_REMAP[1:0]: */ /** SPI1 remapping */ +/* SPI1_REMAP[1:0]: */ +/** SPI1 remapping */ #define AFIO_MAPR_SPI1_REMAP (1 << 0) /**@}*/ @@ -821,7 +840,7 @@ Line Devices only @{*/ #define AFIO_MAPR_CAN1_REMAP_PORTA (0x0 << 13) -#define AFIO_MAPR_CAN1_REMAP_PORTB (0x2 << 13) /* Not on 36pin pkg */ +#define AFIO_MAPR_CAN1_REMAP_PORTB (0x2 << 13) /* Not 36pin pkg */ #define AFIO_MAPR_CAN1_REMAP_PORTD (0x3 << 13) /**@}*/ @@ -870,22 +889,28 @@ Line Devices only @ingroup gpio_defines @{*/ -/* FSMC_NADV_DISCONNECT: */ /** The NADV is disconnected from its allocated pin */ +/* FSMC_NADV_DISCONNECT: */ +/** The NADV is disconnected from its allocated pin */ #define AFIO_MAPR2_FSMC_NADV_DISCONNECT (1 << 10) -/* TIM14_REMAP: */ /** TIM14 remapping */ +/* TIM14_REMAP: */ +/** TIM14 remapping */ #define AFIO_MAPR2_TIM14_REMAP (1 << 9) -/* TIM13_REMAP: */ /** TIM13 remapping */ +/* TIM13_REMAP: */ +/** TIM13 remapping */ #define AFIO_MAPR2_TIM13_REMAP (1 << 8) -/* TIM11_REMAP: */ /** TIM11 remapping */ +/* TIM11_REMAP: */ +/** TIM11 remapping */ #define AFIO_MAPR2_TIM11_REMAP (1 << 7) -/* TIM10_REMAP: */ /** TIM10 remapping */ +/* TIM10_REMAP: */ +/** TIM10 remapping */ #define AFIO_MAPR2_TIM10_REMAP (1 << 6) -/* TIM9_REMAP: */ /** TIM9 remapping */ +/* TIM9_REMAP: */ +/** TIM9 remapping */ #define AFIO_MAPR2_TIM9_REMAP (1 << 5) /**@}*/ diff --git a/include/libopencm3/stm32/f1/iwdg.h b/include/libopencm3/stm32/f1/iwdg.h index 5a42f08b..8c5c0654 100644 --- a/include/libopencm3/stm32/f1/iwdg.h +++ b/include/libopencm3/stm32/f1/iwdg.h @@ -1,6 +1,7 @@ /** @defgroup iwdg_defines IWDG Defines -@brief Defined Constants and Types for the STM32F1xx Independent Watchdog Timer +@brief Defined Constants and Types for the STM32F1xx Independent Watchdog +Timer @ingroup STM32F1xx_defines diff --git a/include/libopencm3/stm32/f1/rcc.h b/include/libopencm3/stm32/f1/rcc.h index 01c9346e..edfecfd6 100644 --- a/include/libopencm3/stm32/f1/rcc.h +++ b/include/libopencm3/stm32/f1/rcc.h @@ -6,8 +6,10 @@ @version 1.0.0 -@author @htmlonly © @endhtmlonly 2009 Federico Ruiz-Ugalde \ -@author @htmlonly © @endhtmlonly 2009 Uwe Hermann +@author @htmlonly © @endhtmlonly 2009 +Federico Ruiz-Ugalde \ +@author @htmlonly © @endhtmlonly 2009 +Uwe Hermann @date 18 August 2012 @@ -55,8 +57,8 @@ LGPL License Terms @ref lgpl_license #define RCC_APB1ENR MMIO32(RCC_BASE + 0x1c) #define RCC_BDCR MMIO32(RCC_BASE + 0x20) #define RCC_CSR MMIO32(RCC_BASE + 0x24) -#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) /* (**) */ -#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) /* (**) */ +#define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) /*(**)*/ +#define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) /*(**)*/ /* --- RCC_CR values ------------------------------------------------------- */ @@ -125,9 +127,10 @@ LGPL License Terms @ref lgpl_license #define RCC_CFGR_PLLMUL_PLL_CLK_MUL13 0xb /* (XX) */ #define RCC_CFGR_PLLMUL_PLL_CLK_MUL14 0xc /* (XX) */ #define RCC_CFGR_PLLMUL_PLL_CLK_MUL15 0xd /* 0xd: PLL x 15 */ -#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5 0xd /* 0xd: PLL x 6.5 for conn. line */ +#define RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5 0xd /* 0xd: PLL x 6.5 for conn. + line */ #define RCC_CFGR_PLLMUL_PLL_CLK_MUL16 0xe /* (XX) */ -// #define PLLMUL_PLL_CLK_MUL16 0xf /* (XX) */ /* Errata? 17? */ +/* #define PLLMUL_PLL_CLK_MUL16 0xf */ /* (XX) */ /* Errata? 17? */ /**@}*/ /* TODO: conn. line differs. */ @@ -286,7 +289,8 @@ LGPL License Terms @ref lgpl_license #define RCC_APB1RSTR_BKPRST (1 << 27) #define RCC_APB1RSTR_CAN2RST (1 << 26) /* (**) */ #define RCC_APB1RSTR_CAN1RST (1 << 25) /* (**) */ -#define RCC_APB1RSTR_CANRST (1 << 25) /* (XX) Alias for CAN1RST */ +#define RCC_APB1RSTR_CANRST (1 << 25) /* (XX) Alias for + CAN1RST */ #define RCC_APB1RSTR_USBRST (1 << 23) /* (XX) */ #define RCC_APB1RSTR_I2C2RST (1 << 22) #define RCC_APB1RSTR_I2C1RST (1 << 21) @@ -358,7 +362,8 @@ LGPL License Terms @ref lgpl_license #define RCC_APB1ENR_BKPEN (1 << 27) #define RCC_APB1ENR_CAN2EN (1 << 26) /* (**) */ #define RCC_APB1ENR_CAN1EN (1 << 25) /* (**) */ -#define RCC_APB1ENR_CANEN (1 << 25) /* (XX) Alias for CAN1EN */ +#define RCC_APB1ENR_CANEN (1 << 25) /* (XX) Alias for + CAN1EN */ #define RCC_APB1ENR_USBEN (1 << 23) /* (XX) */ #define RCC_APB1ENR_I2C2EN (1 << 22) #define RCC_APB1ENR_I2C1EN (1 << 21) diff --git a/include/libopencm3/stm32/f1/usb.h b/include/libopencm3/stm32/f1/usb.h index 6b9d4f43..88d65638 100644 --- a/include/libopencm3/stm32/f1/usb.h +++ b/include/libopencm3/stm32/f1/usb.h @@ -6,7 +6,8 @@ @version 1.0.0 -@author @htmlonly © @endhtmlonly 2009 Piotr Esden-Tempski +@author @htmlonly © @endhtmlonly 2009 +Piotr Esden-Tempski @date 11 March 2013 @@ -131,9 +132,9 @@ LGPL License Terms @ref lgpl_license #define USB_EP_SETUP 0x0800 /* Setup transaction completed */ #define USB_EP_TYPE 0x0600 /* Endpoint type */ #define USB_EP_KIND 0x0100 /* Endpoint kind. - * When set and type=bulk -> double buffer - * When set and type=control -> status out - */ + * When set and type=bulk -> double buffer + * When set and type=control -> status out + */ #define USB_EP_TX_CTR 0x0080 /* Correct transfer TX */ #define USB_EP_TX_DTOG 0x0040 /* Data toggle TX */ diff --git a/include/libopencm3/stm32/f2/crc.h b/include/libopencm3/stm32/f2/crc.h index 425eb615..e9e5eae0 100644 --- a/include/libopencm3/stm32/f2/crc.h +++ b/include/libopencm3/stm32/f2/crc.h @@ -1,6 +1,7 @@ /** @defgroup crc_defines CRC Defines -@brief libopencm3 Defined Constants and Types for the STM32F2xx CRC Generator +@brief libopencm3 Defined Constants and Types for the STM32F2xx CRC +Generator @ingroup STM32F2xx_defines diff --git a/include/libopencm3/stm32/f2/iwdg.h b/include/libopencm3/stm32/f2/iwdg.h index d25398fc..fff3fbd6 100644 --- a/include/libopencm3/stm32/f2/iwdg.h +++ b/include/libopencm3/stm32/f2/iwdg.h @@ -1,6 +1,7 @@ /** @defgroup iwdg_defines IWDG Defines -@brief Defined Constants and Types for the STM32F2xx Independent Watchdog Timer +@brief Defined Constants and Types for the STM32F2xx Independent Watchdog +Timer @ingroup STM32F2xx_defines diff --git a/include/libopencm3/stm32/f2/memorymap.h b/include/libopencm3/stm32/f2/memorymap.h index f888443b..c6d7f814 100644 --- a/include/libopencm3/stm32/f2/memorymap.h +++ b/include/libopencm3/stm32/f2/memorymap.h @@ -22,7 +22,7 @@ #include -/* --- STM32F20x specific peripheral definitions ------------------------------- */ +/* --- STM32F20x specific peripheral definitions --------------------------- */ /* Memory map for all busses */ #define PERIPH_BASE 0x40000000 diff --git a/include/libopencm3/stm32/f2/rcc.h b/include/libopencm3/stm32/f2/rcc.h index 964197c0..fb2dc263 100644 --- a/include/libopencm3/stm32/f2/rcc.h +++ b/include/libopencm3/stm32/f2/rcc.h @@ -77,7 +77,7 @@ #define RCC_CR_HSIRDY (1 << 1) #define RCC_CR_HSION (1 << 0) -/* --- RCC_PLLCFGR values ------------------------------------------------------- */ +/* --- RCC_PLLCFGR values -------------------------------------------------- */ /* PLLQ: [27:24] */ #define RCC_PLLCFGR_PLLQ_SHIFT 24 @@ -342,8 +342,8 @@ #define RCC_AHB1LPENR_DMA1LPEN (1 << 21) #define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18) #define RCC_AHB1LPENR_SRAM2LPEN (1 << 17) -#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16) -#define RCC_AHB1LPENR_FLITFLPEN (1 << 15) +#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16) +#define RCC_AHB1LPENR_FLITFLPEN (1 << 15) #define RCC_AHB1LPENR_CRCLPEN (1 << 12) #define RCC_AHB1LPENR_IOPILPEN (1 << 8) #define RCC_AHB1LPENR_IOPHLPEN (1 << 7) diff --git a/include/libopencm3/stm32/f4/adc.h b/include/libopencm3/stm32/f4/adc.h index d2121e88..fb70b7a1 100644 --- a/include/libopencm3/stm32/f4/adc.h +++ b/include/libopencm3/stm32/f4/adc.h @@ -1,13 +1,16 @@ /** @defgroup STM32F4xx_adc_defines ADC Defines -@brief Defined Constants and Types for the STM32F4xx Analog to Digital Converters +@brief Defined Constants and Types for the STM32F4xx Analog to Digital +Converters @ingroup STM32F4xx_defines @version 1.0.0 -@author @htmlonly © @endhtmlonly 2012 Matthew Lai -@author @htmlonly © @endhtmlonly 2009 Edward Cheeseman +@author @htmlonly © @endhtmlonly 2012 +Matthew Lai +@author @htmlonly © @endhtmlonly 2009 +Edward Cheeseman @date 31 August 2012 @@ -164,9 +167,9 @@ LGPL License Terms @ref lgpl_license /* ADC common (shared) registers */ #define ADC_COMMON_REGISTERS_BASE (ADC1_BASE+0x300) -#define ADC_CSR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x0) -#define ADC_CCR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x4) -#define ADC_CDR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x8) +#define ADC_CSR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x0) +#define ADC_CCR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x4) +#define ADC_CDR MMIO32(ADC_COMMON_REGISTERS_BASE + 0x8) /* --- ADC Channels ------------------------------------------------------- */ @@ -207,7 +210,7 @@ LGPL License Terms @ref lgpl_license #define ADC_SR_EOC (1 << 1) #define ADC_SR_AWD (1 << 0) -/* --- ADC_CR1 values specific to STM32F2,4------------------------------------ */ +/* --- ADC_CR1 values specific to STM32F2,4--------------------------------- */ /* OVRIE: Overrun interrupt enable */ #define ADC_CR1_OVRIE (1 << 26) @@ -281,7 +284,7 @@ LGPL License Terms @ref lgpl_license /* AWDCH[4:0]: Analog watchdog channel bits. (Up to 17 other values reserved) */ /* Notes: * ADC1: Analog channel 16 and 17 are internally connected to the temperature - * sensor and V_REFINT, respectively. + * sensor and V_REFINT, respectively. * ADC2: Analog channel 16 and 17 are internally connected to V_SS. * ADC3: Analog channel 9, 14, 15, 16 and 17 are internally connected to V_SS. */ @@ -567,7 +570,8 @@ LGPL License Terms @ref lgpl_license /* JL[2:0]: Discontinous mode channel count injected channels. */ /****************************************************************************/ -/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode fro injected channels. +/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode fro +injected channels. @ingroup STM32F4xx_adc_defines @{*/ @@ -733,33 +737,45 @@ LGPL License Terms @ref lgpl_license /** All ADCs independent */ #define ADC_CCR_MULTI_INDEPENDENT (0x00 << 0) -/* dual modes (ADC1 + ADC2) */ -/** Dual modes (ADC1 + ADC2) Combined regular simultaneous + injected simultaneous mode */ +/* Dual modes (ADC1 + ADC2) */ +/** + * Dual modes (ADC1 + ADC2) Combined regular simultaneous + + * injected simultaneous mode. + */ #define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_INJECTED_SIMUL (0x01 << 0) -/** Dual modes (ADC1 + ADC2) Combined regular simultaneous + alternate trigger mode. */ +/** + * Dual modes (ADC1 + ADC2) Combined regular simultaneous + + * alternate trigger mode. + */ #define ADC_CCR_MULTI_DUAL_REG_SIMUL_AND_ALTERNATE_TRIG (0x02 << 0) /** Dual modes (ADC1 + ADC2) Injected simultaneous mode only. */ -#define ADC_CCR_MULTI_DUAL_INJECTED_SIMUL (0x05 << 0) +#define ADC_CCR_MULTI_DUAL_INJECTED_SIMUL (0x05 << 0) /** Dual modes (ADC1 + ADC2) Regular simultaneous mode only. */ -#define ADC_CCR_MULTI_DUAL_REGULAR_SIMUL (0x06 << 0) +#define ADC_CCR_MULTI_DUAL_REGULAR_SIMUL (0x06 << 0) /** Dual modes (ADC1 + ADC2) Interleaved mode only. */ -#define ADC_CCR_MULTI_DUAL_INTERLEAVED (0x07 << 0) +#define ADC_CCR_MULTI_DUAL_INTERLEAVED (0x07 << 0) /** Dual modes (ADC1 + ADC2) Alternate trigger mode only. */ -#define ADC_CCR_MULTI_DUAL_ALTERNATE_TRIG (0x09 << 0) +#define ADC_CCR_MULTI_DUAL_ALTERNATE_TRIG (0x09 << 0) /* Triple modes (ADC1 + ADC2 + ADC3) */ -/** Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + injected simultaneous mode */ -#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_INJECTED_SIMUL (0x11 << 0) -/** Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + alternate trigger mode. */ -#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_ALTERNATE_TRIG (0x12 << 0) +/** + * Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + + * injected simultaneous mode. + */ +#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_INJECTED_SIMUL (0x11 << 0) +/** + * Triple modes (ADC1 + ADC2 + ADC3) Combined regular simultaneous + + * alternate trigger mode. + */ +#define ADC_CCR_MULTI_TRIPLE_REG_SIMUL_AND_ALTERNATE_TRIG (0x12 << 0) /** Triple modes (ADC1 + ADC2 + ADC3) Injected simultaneous mode only. */ -#define ADC_CCR_MULTI_TRIPLE_INJECTED_SIMUL (0x15 << 0) +#define ADC_CCR_MULTI_TRIPLE_INJECTED_SIMUL (0x15 << 0) /** Triple modes (ADC1 + ADC2 + ADC3) Regular simultaneous mode only. */ -#define ADC_CCR_MULTI_TRIPLE_REGULAR_SIMUL (0x16 << 0) +#define ADC_CCR_MULTI_TRIPLE_REGULAR_SIMUL (0x16 << 0) /** Triple modes (ADC1 + ADC2 + ADC3) Interleaved mode only. */ -#define ADC_CCR_MULTI_TRIPLE_INTERLEAVED (0x17 << 0) +#define ADC_CCR_MULTI_TRIPLE_INTERLEAVED (0x17 << 0) /** Triple modes (ADC1 + ADC2 + ADC3) Alternate trigger mode only. */ -#define ADC_CCR_MULTI_TRIPLE_ALTERNATE_TRIG (0x19 << 0) +#define ADC_CCR_MULTI_TRIPLE_ALTERNATE_TRIG (0x19 << 0) /**@}*/ #define ADC_CCR_MULTI_MASK (0x1f << 0) diff --git a/include/libopencm3/stm32/f4/crc.h b/include/libopencm3/stm32/f4/crc.h index bab8a23b..7aa1b293 100644 --- a/include/libopencm3/stm32/f4/crc.h +++ b/include/libopencm3/stm32/f4/crc.h @@ -1,6 +1,7 @@ /** @defgroup crc_defines CRC Defines -@brief libopencm3 Defined Constants and Types for the STM32F4xx CRC Generator +@brief libopencm3 Defined Constants and Types for the STM32F4xx CRC +Generator @ingroup STM32F4xx_defines diff --git a/include/libopencm3/stm32/f4/iwdg.h b/include/libopencm3/stm32/f4/iwdg.h index d708fb52..f2280302 100644 --- a/include/libopencm3/stm32/f4/iwdg.h +++ b/include/libopencm3/stm32/f4/iwdg.h @@ -1,6 +1,7 @@ /** @defgroup iwdg_defines IWDG Defines -@brief Defined Constants and Types for the STM32F4xx Independent Watchdog Timer +@brief Defined Constants and Types for the STM32F4xx Independent Watchdog +Timer @ingroup STM32F4xx_defines diff --git a/include/libopencm3/stm32/f4/rcc.h b/include/libopencm3/stm32/f4/rcc.h index 01ca21ab..eb41016d 100644 --- a/include/libopencm3/stm32/f4/rcc.h +++ b/include/libopencm3/stm32/f4/rcc.h @@ -78,7 +78,7 @@ #define RCC_CR_HSIRDY (1 << 1) #define RCC_CR_HSION (1 << 0) -/* --- RCC_PLLCFGR values ------------------------------------------------------- */ +/* --- RCC_PLLCFGR values -------------------------------------------------- */ /* PLLQ: [27:24] */ #define RCC_PLLCFGR_PLLQ_SHIFT 24 @@ -343,8 +343,8 @@ #define RCC_AHB1LPENR_DMA1LPEN (1 << 21) #define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18) #define RCC_AHB1LPENR_SRAM2LPEN (1 << 17) -#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16) -#define RCC_AHB1LPENR_FLITFLPEN (1 << 15) +#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16) +#define RCC_AHB1LPENR_FLITFLPEN (1 << 15) #define RCC_AHB1LPENR_CRCLPEN (1 << 12) #define RCC_AHB1LPENR_IOPILPEN (1 << 8) #define RCC_AHB1LPENR_IOPHLPEN (1 << 7) diff --git a/include/libopencm3/stm32/hash.h b/include/libopencm3/stm32/hash.h index 7b2c5044..35a64b82 100644 --- a/include/libopencm3/stm32/hash.h +++ b/include/libopencm3/stm32/hash.h @@ -22,5 +22,6 @@ #elif defined(STM32F4) # include #else -# error "hash processor is supported only in stm32f21, stm32f41 and stm32f43 families." +# error "hash processor is supported only" \ + "in stm32f21, stm32f41 and stm32f43 families." #endif diff --git a/include/libopencm3/stm32/l1/crc.h b/include/libopencm3/stm32/l1/crc.h index 80194538..1100be91 100644 --- a/include/libopencm3/stm32/l1/crc.h +++ b/include/libopencm3/stm32/l1/crc.h @@ -1,6 +1,7 @@ /** @defgroup crc_defines CRC Defines -@brief libopencm3 Defined Constants and Types for the STM32L1xx CRC Generator +@brief libopencm3 Defined Constants and Types for the STM32L1xx CRC +Generator @ingroup STM32L1xx_defines diff --git a/include/libopencm3/stm32/l1/dma.h b/include/libopencm3/stm32/l1/dma.h index f9b80cbb..2258f5b3 100644 --- a/include/libopencm3/stm32/l1/dma.h +++ b/include/libopencm3/stm32/l1/dma.h @@ -6,8 +6,10 @@ @version 1.0.0 -@author @htmlonly © @endhtmlonly 2011 Fergus Noble -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies +@author @htmlonly © @endhtmlonly 2011 +Fergus Noble +@author @htmlonly © @endhtmlonly 2012 +Ken Sarkies @date 18 October 2012 diff --git a/include/libopencm3/stm32/l1/flash.h b/include/libopencm3/stm32/l1/flash.h index 724fec9d..4dc26216 100644 --- a/include/libopencm3/stm32/l1/flash.h +++ b/include/libopencm3/stm32/l1/flash.h @@ -20,7 +20,8 @@ */ /* - * All extracted from PM0062 rev2, L15xx and L16xx Flash/EEPROM programming manual + * All extracted from PM0062 rev2, L15xx and L16xx Flash/EEPROM programming + * manual. */ #ifndef LIBOPENCM3_FLASH_H diff --git a/include/libopencm3/stm32/l1/gpio.h b/include/libopencm3/stm32/l1/gpio.h index c4ab65fd..5666fc56 100644 --- a/include/libopencm3/stm32/l1/gpio.h +++ b/include/libopencm3/stm32/l1/gpio.h @@ -171,7 +171,7 @@ LGPL License Terms @ref lgpl_license #define GPIO_OTYPE_OD 0x1 /**@}*/ -/* Output speed values */ +/* Output speed values */ #define GPIO_OSPEED(n, speed) (speed << (2 * (n))) #define GPIO_OSPEED_MASK(n) (0x3 << (2 * (n))) /** @defgroup gpio_speed GPIO Output Pin Speed diff --git a/include/libopencm3/stm32/l1/iwdg.h b/include/libopencm3/stm32/l1/iwdg.h index 54c11ebd..50e24acf 100644 --- a/include/libopencm3/stm32/l1/iwdg.h +++ b/include/libopencm3/stm32/l1/iwdg.h @@ -1,6 +1,7 @@ /** @defgroup iwdg_defines IWDG Defines -@brief Defined Constants and Types for the STM32L1xx Independent Watchdog Timer +@brief Defined Constants and Types for the STM32L1xx Independent Watchdog +Timer @ingroup STM32L1xx_defines diff --git a/include/libopencm3/stm32/l1/rcc.h b/include/libopencm3/stm32/l1/rcc.h index b89f20f8..b267c3a4 100644 --- a/include/libopencm3/stm32/l1/rcc.h +++ b/include/libopencm3/stm32/l1/rcc.h @@ -6,9 +6,12 @@ @version 1.0.0 -@author @htmlonly © @endhtmlonly 2009 Federico Ruiz-Ugalde \ -@author @htmlonly © @endhtmlonly 2009 Uwe Hermann -@author @htmlonly © @endhtmlonly 2012 Karl Palsson +@author @htmlonly © @endhtmlonly 2009 +Federico Ruiz-Ugalde \ +@author @htmlonly © @endhtmlonly 2009 +Uwe Hermann +@author @htmlonly © @endhtmlonly 2012 +Karl Palsson @date 11 November 2012 diff --git a/include/libopencm3/stm32/l1/timer.h b/include/libopencm3/stm32/l1/timer.h index dedcfd60..5323ff6c 100644 --- a/include/libopencm3/stm32/l1/timer.h +++ b/include/libopencm3/stm32/l1/timer.h @@ -51,7 +51,8 @@ LGPL License Terms @ref lgpl_license /* ITR1_RMP */ /****************************************************************************/ -/** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Option Register Internal Trigger 1 Remap +/** @defgroup tim2_opt_trigger_remap TIM2_OR Timer 2 Option Register Internal +Trigger 1 Remap @ingroup timer_defines @{*/ diff --git a/include/libopencm3/stm32/otg_fs.h b/include/libopencm3/stm32/otg_fs.h index d8ee3938..182480e0 100644 --- a/include/libopencm3/stm32/otg_fs.h +++ b/include/libopencm3/stm32/otg_fs.h @@ -39,7 +39,8 @@ #define OTG_FS_GCCFG MMIO32(USB_OTG_FS_BASE + 0x038) #define OTG_FS_CID MMIO32(USB_OTG_FS_BASE + 0x03C) #define OTG_FS_HPTXFSIZ MMIO32(USB_OTG_FS_BASE + 0x100) -#define OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + 0x104 + 4*(x-1)) +#define OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + 0x104 + \ + 4*(x-1)) /* Host-mode Control and Status Registers */ #define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + 0x400) @@ -66,28 +67,36 @@ #define OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + 0x82C) #define OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + 0x834) #define OTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + 0x900) -#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0x900 + 0x20*(x)) +#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0x900 + \ + 0x20*(x)) #define OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + 0xB00) -#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0xB00 + 0x20*(x)) -#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + 0x908 + 0x20*(x)) -#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + 0xB08 + 0x20*(x)) +#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + 0xB00 + \ + 0x20*(x)) +#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + 0x908 + \ + 0x20*(x)) +#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + 0xB08 + \ + 0x20*(x)) #define OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0x910) #define OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + 0xB10) -#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0x910 + 0x20*(x)) -#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + 0x918 + 0x20*(x)) -#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0xB10 + 0x20*(x)) +#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0x910 + \ + 0x20*(x)) +#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + 0x918 + \ + 0x20*(x)) +#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + 0xB10 + \ + 0x20*(x)) /* Power and clock gating control and status register */ #define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + 0xE00) /* Data FIFO */ -#define OTG_FS_FIFO(x) ((volatile u32*)(USB_OTG_FS_BASE + (((x) + 1) << 12))) +#define OTG_FS_FIFO(x) ((volatile u32*)(USB_OTG_FS_BASE + \ + (((x) + 1) << 12))) /* Global CSRs */ /* OTG_FS USB control registers (OTG_HS_GOTGCTL) */ #define OTG_FS_GOTGCTL_BSVLD (1 << 19) #define OTG_FS_GOTGCTL_ASVLD (1 << 18) -#define OTG_FS_GOTGCTL_DBCT (1 << 17) +#define OTG_FS_GOTGCTL_DBCT (1 << 17) #define OTG_FS_GOTGCTL_CIDSTS (1 << 16) #define OTG_FS_GOTGCTL_DHNPEN (1 << 11) #define OTG_FS_GOTGCTL_HSHNPEN (1 << 10) diff --git a/include/libopencm3/stm32/otg_hs.h b/include/libopencm3/stm32/otg_hs.h index 2f59ddd9..abb5fa02 100644 --- a/include/libopencm3/stm32/otg_hs.h +++ b/include/libopencm3/stm32/otg_hs.h @@ -135,21 +135,24 @@ #define OTG_HS_DOEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPINT(x)) #define OTG_HS_DIEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPTSIZ0) #define OTG_HS_DOEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPTSIZ0) -#define OTG_HS_DIEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPTSIZ(x))) +#define OTG_HS_DIEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + \ + OTG_DIEPTSIZ(x)) #define OTG_HS_DTXFSTS(x) MMIO32(USB_OTG_HS_BASE + OTG_DTXFSTS(x)) -#define OTG_HS_DOEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPTSIZ(x)) +#define OTG_HS_DOEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + \ + OTG_DOEPTSIZ(x)) /* Power and clock gating control and status register */ #define OTG_HS_PCGCCTL MMIO32(USB_OTG_HS_BASE + OTG_PCGCCTL) /* Data FIFO */ -#define OTG_HS_FIFO(x) ((volatile u32*)(USB_OTG_HS_BASE + OTG_FIFO(x))) +#define OTG_HS_FIFO(x) ((volatile u32*)(USB_OTG_HS_BASE + \ + OTG_FIFO(x))) /* Global CSRs */ /* OTG_HS USB control registers (OTG_FS_GOTGCTL) */ #define OTG_HS_GOTGCTL_BSVLD (1 << 19) #define OTG_HS_GOTGCTL_ASVLD (1 << 18) -#define OTG_HS_GOTGCTL_DBCT (1 << 17) +#define OTG_HS_GOTGCTL_DBCT (1 << 17) #define OTG_HS_GOTGCTL_CIDSTS (1 << 16) #define OTG_HS_GOTGCTL_DHNPEN (1 << 11) #define OTG_HS_GOTGCTL_HSHNPEN (1 << 10) diff --git a/include/libopencm3/stm32/syscfg.h b/include/libopencm3/stm32/syscfg.h index 7426f16c..ceba5a61 100644 --- a/include/libopencm3/stm32/syscfg.h +++ b/include/libopencm3/stm32/syscfg.h @@ -22,7 +22,7 @@ #include -/* --- SYSCFG registers ------------------------------------------------------ */ +/* --- SYSCFG registers ---------------------------------------------------- */ #define SYSCFG_MEMRM MMIO32(SYSCFG_BASE + 0x00) diff --git a/include/libopencm3/stm32/tools.h b/include/libopencm3/stm32/tools.h index 74bbea89..288ad091 100644 --- a/include/libopencm3/stm32/tools.h +++ b/include/libopencm3/stm32/tools.h @@ -59,6 +59,6 @@ do { \ toggle_mask ^= bit_selector; \ } \ SET_REG(REG, toggle_mask); \ -} while(0) +} while (0) #endif diff --git a/include/libopencm3/usb/cdc.h b/include/libopencm3/usb/cdc.h index 1efb36e9..9af8c943 100644 --- a/include/libopencm3/usb/cdc.h +++ b/include/libopencm3/usb/cdc.h @@ -6,7 +6,8 @@ @version 1.0.0 -@author @htmlonly © @endhtmlonly 2010 Gareth McMullin +@author @htmlonly © @endhtmlonly 2010 +Gareth McMullin @date 10 March 2013 @@ -87,7 +88,7 @@ struct usb_cdc_union_descriptor { u8 bControlInterface; u8 bSubordinateInterface0; /* ... */ -} __attribute__((packed)); +} __packed; /* Definitions for Abstract Control Model devices from: @@ -102,7 +103,7 @@ struct usb_cdc_call_management_descriptor { u8 bDescriptorSubtype; u8 bmCapabilities; u8 bDataInterface; -} __attribute__((packed)); +} __packed; /* Table 4: Abstract Control Management Functional Descriptor */ struct usb_cdc_acm_descriptor { @@ -110,7 +111,7 @@ struct usb_cdc_acm_descriptor { u8 bDescriptorType; u8 bDescriptorSubtype; u8 bmCapabilities; -} __attribute__((packed)); +} __packed; /* Table 13: Class-Specific Request Codes for PSTN subclasses */ /* ... */ @@ -125,7 +126,7 @@ struct usb_cdc_line_coding { u8 bCharFormat; u8 bParityType; u8 bDataBits; -} __attribute__((packed)); +} __packed; /* Table 30: Class-Specific Notification Codes for PSTN subclasses */ /* ... */ @@ -139,7 +140,7 @@ struct usb_cdc_notification { u16 wValue; u16 wIndex; u16 wLength; -} __attribute__((packed)); +} __packed; #endif diff --git a/include/libopencm3/usb/dfu.h b/include/libopencm3/usb/dfu.h index 7c8099f1..c216e39c 100644 --- a/include/libopencm3/usb/dfu.h +++ b/include/libopencm3/usb/dfu.h @@ -6,7 +6,8 @@ @version 1.0.0 -@author @htmlonly © @endhtmlonly 2010 Gareth McMullin +@author @htmlonly © @endhtmlonly 2010 +Gareth McMullin @date 10 March 2013 @@ -93,7 +94,7 @@ struct usb_dfu_descriptor { u16 wDetachTimeout; u16 wTransferSize; u16 bcdDFUVersion; -} __attribute__((packed)); +} __packed; #endif diff --git a/include/libopencm3/usb/hid.h b/include/libopencm3/usb/hid.h index 31973ec5..f424f38d 100644 --- a/include/libopencm3/usb/hid.h +++ b/include/libopencm3/usb/hid.h @@ -6,7 +6,8 @@ @version 1.0.0 -@author @htmlonly © @endhtmlonly 2010 Gareth McMullin +@author @htmlonly © @endhtmlonly 2010 +Gareth McMullin @date 10 March 2013 @@ -50,7 +51,7 @@ struct usb_hid_descriptor { u16 bcdHID; u8 bCountryCode; u8 bNumDescriptors; -} __attribute__((packed)); +} __packed; #endif diff --git a/include/libopencm3/usb/usbd.h b/include/libopencm3/usb/usbd.h index 337ed00e..f6f96061 100644 --- a/include/libopencm3/usb/usbd.h +++ b/include/libopencm3/usb/usbd.h @@ -6,7 +6,8 @@ @version 1.0.0 -@author @htmlonly © @endhtmlonly 2010 Gareth McMullin +@author @htmlonly © @endhtmlonly 2010 +Gareth McMullin @date 10 March 2013 @@ -58,11 +59,11 @@ extern const usbd_driver stm32f207_usb_driver; #define otghs_usb_driver stm32f207_usb_driver /* */ -extern usbd_device *usbd_init(const usbd_driver *driver, - const struct usb_device_descriptor *dev, - const struct usb_config_descriptor *conf, - const char **strings, int num_strings, - u8 *control_buffer, u16 control_buffer_size); +extern usbd_device * usbd_init(const usbd_driver *driver, + const struct usb_device_descriptor *dev, + const struct usb_config_descriptor *conf, + const char **strings, int num_strings, + u8 *control_buffer, u16 control_buffer_size); extern void usbd_register_reset_callback(usbd_device *usbd_dev, void (*callback)(void)); diff --git a/include/libopencm3/usb/usbstd.h b/include/libopencm3/usb/usbstd.h index 9d0006f0..fc65aa08 100644 --- a/include/libopencm3/usb/usbstd.h +++ b/include/libopencm3/usb/usbstd.h @@ -1,12 +1,14 @@ /** @defgroup usb_type_defines USB Standard Structure Definitions -@brief Defined Constants and Types for the USB Standard Structure Definitions +@brief Defined Constants and Types for the USB Standard Structure +Definitions @ingroup USB_defines @version 1.0.0 -@author @htmlonly © @endhtmlonly 2010 Gareth McMullin +@author @htmlonly © @endhtmlonly 2010 +Gareth McMullin @date 10 March 2013 @@ -57,10 +59,10 @@ struct usb_setup_data { u16 wValue; u16 wIndex; u16 wLength; -} __attribute__((packed)); +} __packed; /* Class Definition */ -#define USB_CLASS_VENDOR 0xFF +#define USB_CLASS_VENDOR 0xFF /* bmRequestType bit definitions */ #define USB_REQ_TYPE_IN 0x80 @@ -129,7 +131,7 @@ struct usb_device_descriptor { u8 iProduct; u8 iSerialNumber; u8 bNumConfigurations; -} __attribute__((packed)); +} __packed; #define USB_DT_DEVICE_SIZE sizeof(struct usb_device_descriptor) @@ -146,7 +148,7 @@ struct usb_device_qualifier_descriptor { u8 bMaxPacketSize0; u8 bNumConfigurations; u8 bReserved; -} __attribute__((packed)); +} __packed; /* USB Standard Configuration Descriptor - Table 9-10 */ struct usb_config_descriptor { @@ -165,7 +167,7 @@ struct usb_config_descriptor { const struct usb_iface_assoc_descriptor *iface_assoc; const struct usb_interface_descriptor *altsetting; } *interface; -} __attribute__((packed)); +} __packed; #define USB_DT_CONFIGURATION_SIZE 9 /* USB Configuration Descriptor bmAttributes bit definitions */ @@ -192,7 +194,7 @@ struct usb_interface_descriptor { const struct usb_endpoint_descriptor *endpoint; const void *extra; int extralen; -} __attribute__((packed)); +} __packed; #define USB_DT_INTERFACE_SIZE 9 /* USB Standard Endpoint Descriptor - Table 9-13 */ @@ -203,7 +205,7 @@ struct usb_endpoint_descriptor { u8 bmAttributes; u16 wMaxPacketSize; u8 bInterval; -} __attribute__((packed)); +} __packed; #define USB_DT_ENDPOINT_SIZE sizeof(struct usb_endpoint_descriptor) /* USB Endpoint Descriptor bmAttributes bit definitions */ @@ -228,7 +230,7 @@ struct usb_string_descriptor { u8 bLength; u8 bDescriptorType; u16 wData[]; -} __attribute__((packed)); +} __packed; /* From ECN: Interface Association Descriptors, Table 9-Z */ struct usb_iface_assoc_descriptor { @@ -240,7 +242,7 @@ struct usb_iface_assoc_descriptor { u8 bFunctionSubClass; u8 bFunctionProtocol; u8 iFunction; -} __attribute__((packed)); +} __packed; #define USB_DT_INTERFACE_ASSOCIATION_SIZE \ sizeof(struct usb_iface_assoc_descriptor) diff --git a/include/libopencmsis/core_cm3.h b/include/libopencmsis/core_cm3.h index 0a89381d..4425a089 100644 --- a/include/libopencmsis/core_cm3.h +++ b/include/libopencmsis/core_cm3.h @@ -4,7 +4,8 @@ * particularly unimplemented features are FIXME'd extra * */ -/* the original core_cm3.h is nonfree by arm; this provides libopencm3 variant of the symbols efm32lib needs of CMSIS. */ +/* the original core_cm3.h is nonfree by arm; this provides libopencm3 variant + * of the symbols efm32lib needs of CMSIS. */ #ifndef OPENCMSIS_CORECM3_H #define OPENCMSIS_CORECM3_H @@ -35,8 +36,7 @@ /* structure as in, for example, * DeviceSupport/EnergyMicro/EFM32/efm32tg840f32.h, data from * libopencm3/cm3/scb.h. FIXME incomplete. */ -typedef struct -{ +typedef struct { __IO uint32_t CPUID; __IO uint32_t ICSR; __IO uint32_t VTOR; @@ -55,12 +55,13 @@ typedef struct /* needed by efm32_cmu.h, probably it's just what gcc provides anyway */ #define __CLZ(div) __builtin_clz(div) -/* needed by efm32_aes.c. __builtin_bswap32 does the same thing as the rev instruction according to https://bugzilla.mozilla.org/show_bug.cgi?id=600106 */ +/* needed by efm32_aes.c. __builtin_bswap32 does the same thing as the rev + * instruction according to https://bugzilla.mozilla.org/show_bug.cgi?id=600106 + */ #define __REV(x) __builtin_bswap32(x) /* stubs for efm32_dbg.h */ -typedef struct -{ +typedef struct { uint32_t DHCSR; uint32_t DEMCR; /* needed by efm32tg stk trace.c */ } CoreDebug_TypeDef; @@ -94,8 +95,7 @@ static inline void NVIC_DisableIRQ(uint8_t irqn) #define SCB_SHCSR_MEMFAULTENA_Msk 0 -typedef struct -{ +typedef struct { uint32_t CTRL; uint32_t RNR; uint32_t RBAR; @@ -133,8 +133,7 @@ typedef struct * */ /* from d0002_efm32_cortex-m3_reference_manual.pdf section 4.4 */ -typedef struct -{ +typedef struct { uint32_t CTRL; uint32_t LOAD; uint32_t VAL; @@ -146,7 +145,9 @@ static inline uint32_t SysTick_Config(uint32_t n_ticks) { /* constant from systick_set_reload -- as this returns something that's * not void, this is the only possible error condition */ - if (n_ticks & ~0x00FFFFFF) return 1; + if (n_ticks & ~0x00FFFFFF) { + return 1; + } systick_set_reload(n_ticks); systick_set_clocksource(true); @@ -157,8 +158,7 @@ static inline uint32_t SysTick_Config(uint32_t n_ticks) } /* stubs for efm32tg stk trace.c */ -typedef struct -{ +typedef struct { uint32_t LAR; uint32_t TCR; } ITM_TypeDef; diff --git a/lib/cm3/assert.c b/lib/cm3/assert.c index d76c578c..82def0d1 100644 --- a/lib/cm3/assert.c +++ b/lib/cm3/assert.c @@ -21,7 +21,7 @@ void __attribute__((weak)) cm3_assert_failed(void) { - while(1); + while (1); } void __attribute__((weak)) cm3_assert_failed_verbose( diff --git a/lib/cm3/nvic.c b/lib/cm3/nvic.c index db187b36..9a6e08c0 100644 --- a/lib/cm3/nvic.c +++ b/lib/cm3/nvic.c @@ -45,7 +45,7 @@ LGPL License Terms @ref lgpl_license #include #include -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief NVIC Enable Interrupt Enables a user interrupt. @@ -58,7 +58,7 @@ void nvic_enable_irq(u8 irqn) NVIC_ISER(irqn / 32) = (1 << (irqn % 32)); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief NVIC Disable Interrupt Disables a user interrupt. @@ -71,7 +71,7 @@ void nvic_disable_irq(u8 irqn) NVIC_ICER(irqn / 32) = (1 << (irqn % 32)); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief NVIC Return Pending Interrupt True if the interrupt has occurred and is waiting for service. @@ -85,7 +85,7 @@ u8 nvic_get_pending_irq(u8 irqn) return NVIC_ISPR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief NVIC Set Pending Interrupt Force a user interrupt to a pending state. This has no effect if the interrupt @@ -99,7 +99,7 @@ void nvic_set_pending_irq(u8 irqn) NVIC_ISPR(irqn / 32) = (1 << (irqn % 32)); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief NVIC Clear Pending Interrupt Force remove a user interrupt from a pending state. This has no effect if the @@ -113,7 +113,7 @@ void nvic_clear_pending_irq(u8 irqn) NVIC_ICPR(irqn / 32) = (1 << (irqn % 32)); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief NVIC Return Active Interrupt Interrupt has occurred and is currently being serviced. @@ -127,7 +127,7 @@ u8 nvic_get_active_irq(u8 irqn) return NVIC_IABR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief NVIC Return Enabled Interrupt @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint @@ -139,13 +139,14 @@ u8 nvic_get_irq_enabled(u8 irqn) return NVIC_ISER(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief NVIC Set Interrupt Priority There are 16 priority levels only, given by the upper four bits of the priority -byte, as required by ARM standards. The priority levels are interpreted according -to the pre-emptive priority grouping set in the SCB Application Interrupt and Reset -Control Register (SCB_AIRCR), as done in @ref scb_set_priority_grouping. +byte, as required by ARM standards. The priority levels are interpreted +according to the pre-emptive priority grouping set in the SCB Application +Interrupt and Reset Control Register (SCB_AIRCR), as done in @ref +scb_set_priority_grouping. @param[in] irqn Unsigned int8. Interrupt number @ref nvic_stm32f1_userint @param[in] priority Unsigned int8. Interrupt priority (0 ... 255 in steps of 16) @@ -156,29 +157,29 @@ void nvic_set_priority(u8 irqn, u8 priority) /* code from lpc43xx/nvic.c -- this is quite a hack and alludes to the * negative interrupt numbers assigned to the system interrupts. better * handling would mean signed integers. */ - if(irqn>=NVIC_IRQ_COUNT) - { + if (irqn >= NVIC_IRQ_COUNT) { /* Cortex-M system interrupts */ - SCS_SHPR( (irqn&0xF)-4 ) = priority; - }else - { + SCS_SHPR((irqn & 0xF) - 4) = priority; + } else { /* Device specific interrupts */ NVIC_IPR(irqn) = priority; } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief NVIC Software Trigger Interrupt Generate an interrupt from software. This has no effect for unprivileged access -unless the privilege level has been elevated through the System Control Registers. +unless the privilege level has been elevated through the System Control +Registers. @param[in] irqn Unsigned int16. Interrupt number (0 ... 239) */ void nvic_generate_software_interrupt(u16 irqn) { - if (irqn <= 239) + if (irqn <= 239) { NVIC_STIR |= irqn; + } } /**@}*/ diff --git a/lib/cm3/scb.c b/lib/cm3/scb.c index 07684fee..b0260e64 100644 --- a/lib/cm3/scb.c +++ b/lib/cm3/scb.c @@ -25,14 +25,14 @@ void scb_reset_core(void) { SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET; - while(1); + while (1); } void scb_reset_system(void) { SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ; - while(1); + while (1); } void scb_set_priority_grouping(u32 prigroup) diff --git a/lib/cm3/sync.c b/lib/cm3/sync.c index b7bf604f..cc23e0f9 100644 --- a/lib/cm3/sync.c +++ b/lib/cm3/sync.c @@ -19,18 +19,18 @@ #include -u32 __ldrex(volatile u32* addr) +u32 __ldrex(volatile u32 *addr) { u32 res; __asm__ volatile ("ldrex %0, [%1]" : "=r" (res) : "r" (addr)); return res; } -u32 __strex(u32 val, volatile u32* addr) +u32 __strex(u32 val, volatile u32 *addr) { u32 res; - __asm__ volatile ("strex %0, %2, [%1]" : - "=&r" (res) : "r" (addr), "r" (val)); + __asm__ volatile ("strex %0, %2, [%1]" + : "=&r" (res) : "r" (addr), "r" (val)); return res; } @@ -39,7 +39,7 @@ void __dmb() __asm__ volatile ("dmb"); } -void mutex_lock(mutex_t* m) +void mutex_lock(mutex_t *m) { u32 status = 0; @@ -57,7 +57,7 @@ void mutex_lock(mutex_t* m) __dmb(); } -void mutex_unlock(mutex_t* m) +void mutex_unlock(mutex_t *m) { __dmb(); diff --git a/lib/cm3/systick.c b/lib/cm3/systick.c index 874261b5..bcfa80e7 100644 --- a/lib/cm3/systick.c +++ b/lib/cm3/systick.c @@ -40,7 +40,7 @@ LGPL License Terms @ref lgpl_license /**@{*/ #include -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SysTick Set the Automatic Reload Value. The counter is set to the reload value when the counter starts and after it @@ -54,7 +54,7 @@ void systick_set_reload(u32 value) STK_LOAD = (value & 0x00FFFFFF); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SysTick Read the Automatic Reload Value. @returns 24 bit reload value as u32. @@ -62,10 +62,10 @@ void systick_set_reload(u32 value) u32 systick_get_reload(void) { - return (STK_LOAD & 0x00FFFFFF); + return STK_LOAD & 0x00FFFFFF; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Get the current SysTick counter value. @returns 24 bit current value as u32. @@ -73,10 +73,10 @@ u32 systick_get_reload(void) u32 systick_get_value(void) { - return (STK_VAL & 0x00FFFFFF); + return STK_VAL & 0x00FFFFFF; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Set the SysTick Clock Source. The clock source can be either the AHB clock or the same clock divided by 8. @@ -86,11 +86,12 @@ The clock source can be either the AHB clock or the same clock divided by 8. void systick_set_clocksource(u8 clocksource) { - if (clocksource < 2) + if (clocksource < 2) { STK_CTRL |= (clocksource << STK_CTRL_CLKSOURCE_LSB); + } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Enable SysTick Interrupt. */ @@ -100,7 +101,7 @@ void systick_interrupt_enable(void) STK_CTRL |= STK_CTRL_TICKINT; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Disable SysTick Interrupt. */ @@ -110,7 +111,7 @@ void systick_interrupt_disable(void) STK_CTRL &= ~STK_CTRL_TICKINT; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Enable SysTick Counter. */ @@ -120,7 +121,7 @@ void systick_counter_enable(void) STK_CTRL |= STK_CTRL_ENABLE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Disable SysTick Counter. */ @@ -130,31 +131,32 @@ void systick_counter_disable(void) STK_CTRL &= ~STK_CTRL_ENABLE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SysTick Read the Counter Flag. -The count flag is set when the timer count becomes zero, and is cleared when the -flag is read. +The count flag is set when the timer count becomes zero, and is cleared when +the flag is read. @returns Boolean if flag set. */ u8 systick_get_countflag(void) { - if (STK_CTRL & STK_CTRL_COUNTFLAG) + if (STK_CTRL & STK_CTRL_COUNTFLAG) { return 1; - else + } else { return 0; + } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SysTick Get Calibration Value @returns Current calibration value */ u32 systick_get_calib(void) { - return (STK_CALIB&0x00FFFFFF); + return STK_CALIB & 0x00FFFFFF; } /**@}*/ diff --git a/lib/cm3/vector.c b/lib/cm3/vector.c index 43e8917b..3bc7f66b 100644 --- a/lib/cm3/vector.c +++ b/lib/cm3/vector.c @@ -25,8 +25,6 @@ /* load the weak symbols for IRQ_HANDLERS */ #include "../dispatch/vector_nvic.c" -#define WEAK __attribute__ ((weak)) - /* Symbols exported by the linker script(s): */ extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack; typedef void (*funcp_t) (void); @@ -61,17 +59,23 @@ void WEAK __attribute__ ((naked)) reset_handler(void) volatile unsigned *src, *dest; funcp_t *fp; - for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++) + for (src = &_data_loadaddr, dest = &_data; + dest < &_edata; + src++, dest++) { *dest = *src; + } - while (dest < &_ebss) + while (dest < &_ebss) { *dest++ = 0; + } /* Constructors. */ - for (fp = &__preinit_array_start; fp < &__preinit_array_end; fp++) - (*fp)(); - for (fp = &__init_array_start; fp < &__init_array_end; fp++) - (*fp)(); + for (fp = &__preinit_array_start; fp < &__preinit_array_end; fp++) { + (*fp)(); + } + for (fp = &__init_array_start; fp < &__init_array_end; fp++) { + (*fp)(); + } /* might be provided by platform specific vector.c */ pre_main(); @@ -80,13 +84,15 @@ void WEAK __attribute__ ((naked)) reset_handler(void) main(); /* Destructors. */ - for (fp = &__fini_array_start; fp < &__fini_array_end; fp++) - (*fp)(); + for (fp = &__fini_array_start; fp < &__fini_array_end; fp++) { + (*fp)(); + } + } void blocking_handler(void) { - while (1) ; + while (1); } void null_handler(void) diff --git a/lib/dispatch/vector_nvic.c b/lib/dispatch/vector_nvic.c index 7505ce63..6d3dbb03 100644 --- a/lib/dispatch/vector_nvic.c +++ b/lib/dispatch/vector_nvic.c @@ -33,7 +33,8 @@ # include "../lm3s/vector_nvic.c" #else -# warning"no interrupts defined for chipset; not allocating space in the vector table" +# warning "no interrupts defined for chipset;"\ + "not allocating space in the vector table" #define IRQ_HANDLERS diff --git a/lib/lm3s/gpio.c b/lib/lm3s/gpio.c index 3d91c443..1c26de3b 100644 --- a/lib/lm3s/gpio.c +++ b/lib/lm3s/gpio.c @@ -6,7 +6,8 @@ @version 1.0.0 -@author @htmlonly © @endhtmlonly 2011 Gareth McMullin +@author @htmlonly © @endhtmlonly 2011 +Gareth McMullin @date 10 March 2013 diff --git a/lib/lm4f/gpio.c b/lib/lm4f/gpio.c index 4e8e4be1..621c961c 100644 --- a/lib/lm4f/gpio.c +++ b/lib/lm4f/gpio.c @@ -25,8 +25,10 @@ * * @version 1.0.0 * - * @author @htmlonly © @endhtmlonly 2011 Gareth McMullin - * @author @htmlonly © @endhtmlonly 2013 Alexandru Gagniuc + * @author @htmlonly © @endhtmlonly 2011 + * Gareth McMullin + * @author @htmlonly © @endhtmlonly 2013 + * Alexandru Gagniuc * * @date 16 March 2013 * @@ -268,17 +270,17 @@ void gpio_mode_setup(u32 gpioport, enum gpio_mode mode, enum gpio_pullup pullup, void gpio_set_output_config(u32 gpioport, enum gpio_output_type otype, enum gpio_drive_strength drive, u8 gpios) { - if (otype == GPIO_OTYPE_OD) + if (otype == GPIO_OTYPE_OD) { GPIO_ODR(gpioport) |= gpios; - else + } else { GPIO_ODR(gpioport) &= ~gpios; + } /* * Setting a bit in the GPIO_DRxR register clears the corresponding bit * in the other GPIO_DRyR registers, and vice-versa. */ - switch (drive) - { + switch (drive) { case GPIO_DRIVE_8MA_SLEW_CTL: GPIO_DR8R(gpioport) |= gpios; GPIO_SLR(gpioport) |= gpios; @@ -312,7 +314,7 @@ void gpio_set_output_config(u32 gpioport, enum gpio_output_type otype, * * @param[in] gpioport GPIO block register address base @ref gpio_reg_base * @param[in] alt_func_num Pin alternate function number or 0 to disable the - * alternate function multiplexing. + * alternate function multiplexing. * @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified * by OR'ing then together */ @@ -327,7 +329,7 @@ void gpio_set_af(u32 gpioport, u8 alt_func_num, u8 gpios) GPIO_AFSEL(gpioport) &= ~gpios; return; } - + /* Enable the alternate function */ GPIO_AFSEL(gpioport) |= gpios; /* Alternate functions are digital */ @@ -338,11 +340,12 @@ void gpio_set_af(u32 gpioport, u8 alt_func_num, u8 gpios) for (i = 0; i < 8; i++) { pin_mask = (1 << i); - if (!(gpios & pin_mask)) + if (!(gpios & pin_mask)) { continue; + } pctl32 &= ~PCTL_MASK(i); - pctl32 |= PCTL_AF( i, (alt_func_num & 0xf) ); + pctl32 |= PCTL_AF(i, (alt_func_num & 0xf)); } GPIO_PCTL(gpioport) = pctl32; diff --git a/lib/lm4f/rcc.c b/lib/lm4f/rcc.c index 426aa80b..f640dcdb 100644 --- a/lib/lm4f/rcc.c +++ b/lib/lm4f/rcc.c @@ -23,7 +23,8 @@ * * @ingroup LM4Fxx * -@author @htmlonly © @endhtmlonly 2012 Alexandru Gagniuc +@author @htmlonly © @endhtmlonly 2012 +Alexandru Gagniuc * \brief libopencm3 LM4F Clock control API * @@ -93,13 +94,13 @@ * High-level routines update the system clock automatically. * For read access, it is recommended to acces this variable via * @code - * rcc_get_system_clock_frequency(); + * rcc_get_system_clock_frequency(); * @endcode * * If write access is desired (i.e. when changing the system clock via the * fine-grained mechanisms), then include the following line in your code: * @code - * extern u32 lm4f_rcc_sysclk_freq; + * extern u32 lm4f_rcc_sysclk_freq; * @endcode */ u32 lm4f_rcc_sysclk_freq = 16000000; @@ -266,8 +267,8 @@ void rcc_pll_bypass_enable(void) * function. * * @param[in] div clock divisor to apply to the 400MHz PLL clock. It is the - * caller's responsibility to ensure that the divisor will not create - * a system clock that is out of spec. + * caller's responsibility to ensure that the divisor will not create + * a system clock that is out of spec. */ void rcc_set_pll_divisor(u8 div400) { @@ -334,7 +335,7 @@ void rcc_usb_pll_on(void) */ void rcc_wait_for_pll_ready(void) { - while(!(SYSCTL_PLLSTAT & SYSCTL_PLLSTAT_LOCK)); + while (!(SYSCTL_PLLSTAT & SYSCTL_PLLSTAT_LOCK)); } /** @@ -434,8 +435,8 @@ static u32 xtal_to_freq(xtal_t xtal) * @param [in] osc_src Oscillator from where to derive the system clock. * @param [in] xtal Type of crystal connected to the OSCO/OSCI pins * @param [in] pll_div400 The clock divisor to apply to the 400MHz PLL clock. - * If 0, then the PLL is disabled, and the system runs - * off a "raw" clock. + * If 0, then the PLL is disabled, and the system runs + * off a "raw" clock. * * @return System clock frequency in Hz */ @@ -448,8 +449,9 @@ void rcc_sysclk_config(osc_src_t osc_src, xtal_t xtal, u8 pll_div400) rcc_pll_bypass_enable(); /* Enable the main oscillator, if needed */ - if (osc_src == OSCSRC_MOSC) + if (osc_src == OSCSRC_MOSC) { rcc_enable_main_osc(); + } /* Make RCC2 override RCC */ rcc_enable_rcc2(); diff --git a/lib/lm4f/uart.c b/lib/lm4f/uart.c index d0ab71bc..d5833956 100644 --- a/lib/lm4f/uart.c +++ b/lib/lm4f/uart.c @@ -116,10 +116,11 @@ void uart_set_baudrate(u32 uart, u32 baud) u32 clock; /* Are we running off the internal clock or system clock? */ - if (UART_CC(uart) == UART_CC_CS_PIOSC) + if (UART_CC(uart) == UART_CC_CS_PIOSC) { clock = 16000000; - else + } else { clock = rcc_get_system_clock_frequency(); + } /* Find the baudrate divisor */ u32 div = (((clock * 8) / baud) + 1) / 2; @@ -143,7 +144,7 @@ void uart_set_databits(u32 uart, u8 databits) bits32 = (databits - 5) << 5; /* TODO: What about 9 data bits? */ - + reg32 = UART_LCRH(uart); reg32 &= ~UART_LCRH_WLEN_MASK; reg32 |= bits32; @@ -158,10 +159,11 @@ void uart_set_databits(u32 uart, u8 databits) */ void uart_set_stopbits(u32 uart, u8 stopbits) { - if (stopbits == 2) + if (stopbits == 2) { UART_LCRH(uart) |= UART_LCRH_STP2; - else + } else { UART_LCRH(uart) &= ~UART_LCRH_STP2; + } } /** @@ -178,8 +180,7 @@ void uart_set_parity(u32 uart, enum uart_parity parity) reg32 |= UART_LCRH_PEN; reg32 &= ~(UART_LCRH_SPS | UART_LCRH_EPS); - switch (parity) - { + switch (parity) { case UART_PARITY_NONE: /* Once we disable parity the other bits are meaningless */ UART_LCRH(uart) &= ~UART_LCRH_PEN; @@ -218,12 +219,13 @@ void uart_set_flow_control(u32 uart, enum uart_flowctl flow) reg32 &= ~(UART_CTL_RTSEN | UART_CTL_CTSEN); - if (flow == UART_FLOWCTL_RTS) - reg32 |= UART_CTL_RTSEN; - else if (flow == UART_FLOWCTL_CTS) + if (flow == UART_FLOWCTL_RTS) { + reg32 |= UART_CTL_RTSEN; + } else if (flow == UART_FLOWCTL_CTS) { reg32 |= UART_CTL_CTSEN; - else if (flow == UART_FLOWCTL_RTS_CTS) + } else if (flow == UART_FLOWCTL_RTS_CTS) { reg32 |= (UART_CTL_RTSEN | UART_CTL_CTSEN); + } UART_CTL(uart) = reg32; } @@ -301,7 +303,7 @@ u16 uart_recv(u32 uart) void uart_wait_send_ready(u32 uart) { /* Wait until the Tx FIFO is no longer full */ - while(UART_FR(uart) & UART_FR_TXFF); + while (UART_FR(uart) & UART_FR_TXFF); } /** @@ -314,7 +316,7 @@ void uart_wait_send_ready(u32 uart) void uart_wait_recv_ready(u32 uart) { /* Wait until the Tx FIFO is no longer empty */ - while(UART_FR(uart) & UART_FR_RXFE); + while (UART_FR(uart) & UART_FR_RXFE); } /** @@ -438,8 +440,8 @@ void uart_enable_interrupts(u32 uart, enum uart_interrupt_flag ints) * interrupts, pass (UART_INT_RX | UART_INT_CTS) * * @param[in] uart UART block register address base @ref uart_reg_base - * @param[in] ints Interrupts which to disable. Any combination of interrupts may - * be specified by OR'ing then together + * @param[in] ints Interrupts which to disable. Any combination of interrupts + * may be specified by OR'ing then together */ void uart_disable_interrupts(u32 uart, enum uart_interrupt_flag ints) { diff --git a/lib/lm4f/usb_lm4f.c b/lib/lm4f/usb_lm4f.c index 36ef58a2..dcf9aae5 100644 --- a/lib/lm4f/usb_lm4f.c +++ b/lib/lm4f/usb_lm4f.c @@ -232,8 +232,9 @@ static void lm4f_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size, if (addr == 0) { USB_EPIDX = 0; - if (reg8 > USB_FIFOSZ_SIZE_64) + if (reg8 > USB_FIFOSZ_SIZE_64) { reg8 = USB_FIFOSZ_SIZE_64; + } /* The RX and TX FIFOs are shared for EP0 */ USB_RXFIFOSZ = reg8; @@ -248,8 +249,9 @@ static void lm4f_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size, } /* Are we out of FIFO space? */ - if (usbd_dev->fifo_mem_top + fifo_size > MAX_FIFO_RAM) + if (usbd_dev->fifo_mem_top + fifo_size > MAX_FIFO_RAM) { return; + } USB_EPIDX = addr & USB_EPIDX_MASK; @@ -262,12 +264,12 @@ static void lm4f_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size, usbd_dev->user_callback_ctr[ep][USB_TRANSACTION_IN] = (void *)callback; } - if (type == USB_ENDPOINT_ATTR_ISOCHRONOUS) + if (type == USB_ENDPOINT_ATTR_ISOCHRONOUS) { USB_TXCSRH(ep) |= USB_TXCSRH_ISO; - else + } else { USB_TXCSRH(ep) &= ~USB_TXCSRH_ISO; - } - else { + } + } else { USB_RXMAXP(ep) = max_size; USB_RXFIFOSZ = reg8; USB_RXFIFOADD = ((usbd_dev->fifo_mem_top) >> 3); @@ -275,10 +277,11 @@ static void lm4f_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size, usbd_dev->user_callback_ctr[ep][USB_TRANSACTION_OUT] = (void *)callback; } - if (type == USB_ENDPOINT_ATTR_ISOCHRONOUS) + if (type == USB_ENDPOINT_ATTR_ISOCHRONOUS) { USB_RXCSRH(ep) |= USB_RXCSRH_ISO; - else + } else { USB_RXCSRH(ep) &= ~USB_RXCSRH_ISO; + } } usbd_dev->fifo_mem_top += fifo_size; @@ -301,24 +304,27 @@ static void lm4f_ep_stall_set(usbd_device *usbd_dev, u8 addr, u8 stall) const bool dir_tx = addr & 0x80; if (ep == 0) { - if (stall) + if (stall) { USB_CSRL0 |= USB_CSRL0_STALL; - else + } else { USB_CSRL0 &= ~USB_CSRL0_STALL; + } return; } if (dir_tx) { - if (stall) + if (stall) { (USB_TXCSRL(ep)) |= USB_TXCSRL_STALL; - else + } else { (USB_TXCSRL(ep)) &= ~USB_TXCSRL_STALL; + } } else { - if (stall) + if (stall) { (USB_RXCSRL(ep)) |= USB_RXCSRL_STALL; - else + } else { (USB_RXCSRL(ep)) &= ~USB_RXCSRL_STALL; + } } } @@ -330,13 +336,14 @@ static u8 lm4f_ep_stall_get(usbd_device *usbd_dev, u8 addr) const bool dir_tx = addr & 0x80; if (ep == 0) { - return (USB_CSRL0 & USB_CSRL0_STALLED); + return USB_CSRL0 & USB_CSRL0_STALLED; } - if (dir_tx) - return (USB_TXCSRL(ep) & USB_TXCSRL_STALLED); - else - return (USB_RXCSRL(ep) & USB_RXCSRL_STALLED); + if (dir_tx) { + return USB_TXCSRL(ep) & USB_TXCSRL_STALLED; + } else { + return USB_RXCSRL(ep) & USB_RXCSRL_STALLED; + } } static void lm4f_ep_nak_set(usbd_device *usbd_dev, u8 addr, u8 nak) @@ -368,14 +375,16 @@ static u16 lm4f_ep_write_packet(usbd_device *usbd_dev, u8 addr, * the reads are downgraded to 8-bit in hardware. We lose a bit of * performance, but we don't crash. */ - for (i = 0; i < (len & ~0x3); i += 4) + for (i = 0; i < (len & ~0x3); i += 4) { USB_FIFO32(ep) = *((u32 *)(buf + i)); + } if (len & 0x2) { USB_FIFO16(ep) = *((u16 *)(buf + i)); i += 2; } - if (len & 0x1) + if (len & 0x1) { USB_FIFO8(ep) = *((u8 *)(buf + i)); + } if (ep == 0) { /* @@ -384,11 +393,11 @@ static u16 lm4f_ep_write_packet(usbd_device *usbd_dev, u8 addr, * that is a multiple of 64 bytes will end with a zero-length * packet, so our check is sane. */ - if (len != 64) + if (len != 64) { USB_CSRL0 |= USB_CSRL0_TXRDY | USB_CSRL0_DATAEND; - else + } else { USB_CSRL0 |= USB_CSRL0_TXRDY; - + } } else { USB_TXCSRL(ep) |= USB_TXCSRL_TXRDY; } @@ -396,7 +405,8 @@ static u16 lm4f_ep_write_packet(usbd_device *usbd_dev, u8 addr, return i; } -static u16 lm4f_ep_read_packet(usbd_device *usbd_dev, u8 addr, void *buf, u16 len) +static u16 lm4f_ep_read_packet(usbd_device *usbd_dev, u8 addr, void *buf, + u16 len) { (void)usbd_dev; @@ -412,14 +422,16 @@ static u16 lm4f_ep_read_packet(usbd_device *usbd_dev, u8 addr, void *buf, u16 le * the writes are downgraded to 8-bit in hardware. We lose a bit of * performance, but we don't crash. */ - for (len = 0; len < (rlen & ~0x3); len += 4) + for (len = 0; len < (rlen & ~0x3); len += 4) { *((u32 *)(buf + len)) = USB_FIFO32(ep); + } if (rlen & 0x2) { *((u16 *)(buf + len)) = USB_FIFO16(ep); len += 2; } - if (rlen & 0x1) + if (rlen & 0x1) { *((u8 *)(buf + len)) = USB_FIFO8(ep); + } if (ep == 0) { /* @@ -456,17 +468,21 @@ static void lm4f_poll(usbd_device *usbd_dev) const u8 usb_txis = USB_TXIS; const u8 usb_csrl0 = USB_CSRL0; - if ((usb_is & USB_IM_SUSPEND) && (usbd_dev->user_callback_suspend)) + if ((usb_is & USB_IM_SUSPEND) && (usbd_dev->user_callback_suspend)) { usbd_dev->user_callback_suspend(); - - if ((usb_is & USB_IM_RESUME) && (usbd_dev->user_callback_resume)) - usbd_dev->user_callback_resume(); + } - if (usb_is & USB_IM_RESET) + if ((usb_is & USB_IM_RESUME) && (usbd_dev->user_callback_resume)) { + usbd_dev->user_callback_resume(); + } + + if (usb_is & USB_IM_RESET) { _usbd_reset(usbd_dev); - - if ((usb_is & USB_IM_SOF) && (usbd_dev->user_callback_sof)) + } + + if ((usb_is & USB_IM_SOF) && (usbd_dev->user_callback_sof)) { usbd_dev->user_callback_sof(); + } if (usb_txis & USB_EP0) { /* @@ -483,14 +499,17 @@ static void lm4f_poll(usbd_device *usbd_dev) type = (usbd_dev->control_state.state != DATA_OUT && usbd_dev->control_state.state != LAST_DATA_OUT) ? USB_TRANSACTION_SETUP : - USB_TRANSACTION_OUT ; + USB_TRANSACTION_OUT; - if (usbd_dev->user_callback_ctr[0][type]) - usbd_dev->user_callback_ctr[0][type] (usbd_dev, 0); + if (usbd_dev->user_callback_ctr[0][type]) { + usbd_dev-> + user_callback_ctr[0][type](usbd_dev, 0); + } } else { - tx_cb = usbd_dev->user_callback_ctr[0][USB_TRANSACTION_IN]; + tx_cb = usbd_dev->user_callback_ctr[0] + [USB_TRANSACTION_IN]; /* * EP0 bit in TXIS is set not only when a packet is @@ -508,11 +527,13 @@ static void lm4f_poll(usbd_device *usbd_dev) */ if ((usbd_dev->control_state.state != DATA_IN) && (usbd_dev->control_state.state != LAST_DATA_IN) && - (usbd_dev->control_state.state != STATUS_IN)) + (usbd_dev->control_state.state != STATUS_IN)) { return; + } - if (tx_cb) - tx_cb (usbd_dev, 0); + if (tx_cb) { + tx_cb(usbd_dev, 0); + } } } @@ -521,11 +542,13 @@ static void lm4f_poll(usbd_device *usbd_dev) tx_cb = usbd_dev->user_callback_ctr[i][USB_TRANSACTION_IN]; rx_cb = usbd_dev->user_callback_ctr[i][USB_TRANSACTION_OUT]; - if ( (usb_txis & (1 << i)) && tx_cb) + if ((usb_txis & (1 << i)) && tx_cb) { tx_cb(usbd_dev, i); + } - if ( (usb_rxis & (1 << i)) && rx_cb) + if ((usb_rxis & (1 << i)) && rx_cb) { rx_cb(usbd_dev, i); + } } @@ -540,10 +563,11 @@ static void lm4f_disconnect(usbd_device *usbd_dev, bool disconnected) * usbd_disconnect(dev, 1) followed by usbd_disconnect(dev, 0) * causes the device to re-enumerate and re-configure properly. */ - if (disconnected) + if (disconnected) { lm4f_usb_soft_disconnect(); - else + } else { lm4f_usb_soft_connect(); + } } /* @@ -568,8 +592,9 @@ static usbd_device *lm4f_usbd_init(void) /* Software reset USB */ SYSCTL_SRUSB = 1; - for (i = 0; i < 1000; i++) + for (i = 0; i < 1000; i++) { __asm__("nop"); + } SYSCTL_SRUSB = 0; /* @@ -579,8 +604,8 @@ static usbd_device *lm4f_usbd_init(void) */ /* Wait for it */ i = 0; - while ( (SYSCTL_RIS & SYSCTL_RIS_USBPLLLRIS) == 0) { - i ++; + while ((SYSCTL_RIS & SYSCTL_RIS_USBPLLLRIS) == 0) { + i++; if (i > 0xffff) { return 0; } diff --git a/lib/lpc17xx/gpio.c b/lib/lpc17xx/gpio.c index 0a56d27e..0236f57a 100644 --- a/lib/lpc17xx/gpio.c +++ b/lib/lpc17xx/gpio.c @@ -41,7 +41,7 @@ void gpio_set(u32 gpioport, u32 gpios) void gpio_clear(u32 gpioport, u32 gpios) { - GPIO_CLR(gpioport) = gpios; + GPIO_CLR(gpioport) = gpios; } /**@}*/ diff --git a/lib/lpc43xx/i2c.c b/lib/lpc43xx/i2c.c index b401afb1..5f1ab307 100644 --- a/lib/lpc43xx/i2c.c +++ b/lib/lpc43xx/i2c.c @@ -81,8 +81,9 @@ void i2c0_tx_start(void) /* transmit data byte */ void i2c0_tx_byte(u8 byte) { - if (I2C0_CONSET & I2C_CONSET_STA) + if (I2C0_CONSET & I2C_CONSET_STA) { I2C0_CONCLR = I2C_CONCLR_STAC; + } I2C0_DAT = byte; I2C0_CONCLR = I2C_CONCLR_SIC; while (!(I2C0_CONSET & I2C_CONSET_SI)); @@ -91,8 +92,9 @@ void i2c0_tx_byte(u8 byte) /* receive data byte */ u8 i2c0_rx_byte(void) { - if (I2C0_CONSET & I2C_CONSET_STA) + if (I2C0_CONSET & I2C_CONSET_STA) { I2C0_CONCLR = I2C_CONCLR_STAC; + } I2C0_CONCLR = I2C_CONCLR_SIC; while (!(I2C0_CONSET & I2C_CONSET_SI)); return I2C0_DAT; @@ -101,8 +103,9 @@ u8 i2c0_rx_byte(void) /* transmit stop bit */ void i2c0_stop(void) { - if (I2C0_CONSET & I2C_CONSET_STA) + if (I2C0_CONSET & I2C_CONSET_STA) { I2C0_CONCLR = I2C_CONCLR_STAC; + } I2C0_CONSET = I2C_CONSET_STO; I2C0_CONCLR = I2C_CONCLR_SIC; } diff --git a/lib/lpc43xx/scu.c b/lib/lpc43xx/scu.c index f3d7dcd1..a8474724 100644 --- a/lib/lpc43xx/scu.c +++ b/lib/lpc43xx/scu.c @@ -34,13 +34,17 @@ LGPL License Terms @ref lgpl_license #include -/* For pin_conf_normal value see scu.h define SCU_CONF_XXX or Configuration for different I/O pins types */ +/* For pin_conf_normal value see scu.h define SCU_CONF_XXX or Configuration for + * different I/O pins types + */ void scu_pinmux(scu_grp_pin_t group_pin, u32 scu_conf) { MMIO32(group_pin) = scu_conf; } -/* For other special SCU register USB1, I2C0, ADC0/1, DAC, EMC clock delay See scu.h */ +/* For other special SCU register USB1, I2C0, ADC0/1, DAC, EMC clock delay See + * scu.h + */ /* For Pin interrupt select register see scu.h SCU_PINTSEL0 & SCU_PINTSEL1 */ diff --git a/lib/lpc43xx/ssp.c b/lib/lpc43xx/ssp.c index 4a1ffb50..640e9917 100644 --- a/lib/lpc43xx/ssp.c +++ b/lib/lpc43xx/ssp.c @@ -61,11 +61,9 @@ void ssp_disable(ssp_num_t ssp_num) { u32 ssp_port; - if(ssp_num == SSP0_NUM) - { + if (ssp_num == SSP0_NUM) { ssp_port = SSP0; - }else - { + } else { ssp_port = SSP1; } /* Disable SSP */ @@ -88,16 +86,15 @@ void ssp_init(ssp_num_t ssp_num, u32 ssp_port; u32 clock; - if(ssp_num == SSP0_NUM) - { + if (ssp_num == SSP0_NUM) { ssp_port = SSP0; - }else - { + } else { ssp_port = SSP1; } /* use PLL1 as clock source for SSP1 */ - CGU_BASE_SSP1_CLK = (CGU_SRC_PLL1< 0 ) - { + if ((&_etext_ram-&_text_ram) > 0) { src = &_etext_rom-(&_etext_ram-&_text_ram); - /* Change Shadow memory to ROM (for Debug Purpose in case Boot has not set correctly the M4MEMMAP because of debug) */ + /* Change Shadow memory to ROM (for Debug Purpose in case Boot + * has not set correctly the M4MEMMAP because of debug) + */ CREG_M4MEMMAP = (unsigned long)src; - for(dest = &_text_ram; dest < &_etext_ram; ) - { + for (dest = &_text_ram; dest < &_etext_ram; ) { *dest++ = *src++; } diff --git a/lib/sam/common/gpio.c b/lib/sam/common/gpio.c index 80d41776..b68e1321 100644 --- a/lib/sam/common/gpio.c +++ b/lib/sam/common/gpio.c @@ -1,4 +1,4 @@ -/* +/* * This file is part of the libopencm3 project. * * Copyright (C) 2012 Gareth McMullin @@ -42,15 +42,17 @@ void gpio_init(u32 port, u32 pins, enum gpio_flags flags) PIO_PDR(port) = pins; } - if (flags & GPIO_FLAG_OPEN_DRAIN) + if (flags & GPIO_FLAG_OPEN_DRAIN) { PIO_MDER(port) = pins; - else + } else { PIO_MDDR(port) = pins; + } - if (flags & GPIO_FLAG_PULL_UP) + if (flags & GPIO_FLAG_PULL_UP) { PIO_PUER(port) = pins; - else + } else { PIO_PUDR(port) = pins; + } } void gpio_toggle(u32 gpioport, u32 gpios) diff --git a/lib/sam/common/pmc.c b/lib/sam/common/pmc.c index 01b4fc4c..0680c243 100644 --- a/lib/sam/common/pmc.c +++ b/lib/sam/common/pmc.c @@ -44,18 +44,20 @@ void pmc_plla_config(u8 mul, u8 div) void pmc_peripheral_clock_enable(u8 pid) { - if (pid < 32) + if (pid < 32) { PMC_PCER0 = 1 << pid; - else + } else { PMC_PCER1 = 1 << (pid & 31); + } } void pmc_peripheral_clock_disable(u8 pid) { - if (pid < 32) + if (pid < 32) { PMC_PCDR0 = 1 << pid; - else + } else { PMC_PCDR1 = 1 << (pid & 31); + } } void pmc_mck_set_source(enum mck_src src) diff --git a/lib/sam/common/usart.c b/lib/sam/common/usart.c index 56937fcc..83c17f98 100644 --- a/lib/sam/common/usart.c +++ b/lib/sam/common/usart.c @@ -28,13 +28,13 @@ void usart_set_baudrate(u32 usart, u32 baud) void usart_set_databits(u32 usart, int bits) { USART_MR(usart) = (USART_MR(usart) & ~USART_MR_CHRL_MASK) | - ((bits - 5) << 6); + ((bits - 5) << 6); } void usart_set_stopbits(u32 usart, enum usart_stopbits sb) { USART_MR(usart) = (USART_MR(usart) & ~USART_MR_NBSTOP_MASK) | - (sb << 12); + (sb << 12); } void usart_set_parity(u32 usart, enum usart_parity par) @@ -46,14 +46,14 @@ void usart_set_mode(u32 usart, enum usart_mode mode) { USART_CR(usart) = (mode & USART_MODE_RX) ? USART_CR_RXEN : USART_CR_RXDIS; - USART_CR(usart) = - (mode & USART_MODE_TX) ? USART_CR_TXEN : USART_CR_TXDIS; + USART_CR(usart) = (mode & USART_MODE_TX) ? USART_CR_TXEN + : USART_CR_TXDIS; } void usart_set_flow_control(u32 usart, enum usart_flowcontrol fc) { USART_MR(usart) = (USART_MR(usart) & ~USART_MR_MODE_MASK) | - (fc ? USART_MR_MODE_HW_HANDSHAKING : 0); + (fc ? USART_MR_MODE_HW_HANDSHAKING : 0); } void usart_enable(u32 usart) diff --git a/lib/stm32/can.c b/lib/stm32/can.c index b479b8ef..9eae3cc9 100644 --- a/lib/stm32/can.c +++ b/lib/stm32/can.c @@ -59,13 +59,15 @@ LGPL License Terms @ref lgpl_license */ #define CAN_MSR_INAK_TIMEOUT 0x0000FFFF -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief CAN Reset -The CAN peripheral and all its associated configuration registers are placed in the -reset condition. The reset is effective via the RCC peripheral reset system. +The CAN peripheral and all its associated configuration registers are placed in +the reset condition. The reset is effective via the RCC peripheral reset +system. -@param[in] canport Unsigned int32. CAN block register address base @ref can_reg_base. +@param[in] canport Unsigned int32. CAN block register address base @ref +can_reg_base. */ void can_reset(u32 canport) { @@ -78,7 +80,7 @@ void can_reset(u32 canport) } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief CAN Init Initialize the selected CAN peripheral block. @@ -112,11 +114,10 @@ int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart, /* Wait for acknowledge. */ wait_ack = CAN_MSR_INAK_TIMEOUT; while ((--wait_ack) && - ((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK)) { - } + ((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK)); /* Check the acknowledge. */ - if ((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK){ + if ((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK) { return 1; } @@ -126,64 +127,55 @@ int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart, /* Set the automatic bus-off management. */ if (ttcm) { CAN_MCR(canport) |= CAN_MCR_TTCM; - } - else { + } else { CAN_MCR(canport) &= ~CAN_MCR_TTCM; } if (abom) { CAN_MCR(canport) |= CAN_MCR_ABOM; - } - else { + } else { CAN_MCR(canport) &= ~CAN_MCR_ABOM; } if (awum) { CAN_MCR(canport) |= CAN_MCR_AWUM; - } - else { + } else { CAN_MCR(canport) &= ~CAN_MCR_AWUM; } if (nart) { CAN_MCR(canport) |= CAN_MCR_NART; - } - else{ + } else { CAN_MCR(canport) &= ~CAN_MCR_NART; } if (rflm) { CAN_MCR(canport) |= CAN_MCR_RFLM; - } - else { + } else { CAN_MCR(canport) &= ~CAN_MCR_RFLM; } if (txfp) { CAN_MCR(canport) |= CAN_MCR_TXFP; - } - else { + } else { CAN_MCR(canport) &= ~CAN_MCR_TXFP; } if (silent) { CAN_BTR(canport) |= CAN_BTR_SILM; - } - else { + } else { CAN_BTR(canport) &= ~CAN_BTR_SILM; } if (loopback) { CAN_BTR(canport) |= CAN_BTR_LBKM; - } - else { + } else { CAN_BTR(canport) &= ~CAN_BTR_LBKM; } - /* Set bit timings. */ CAN_BTR(canport) |= sjw | ts2 | ts1 | - ((brp - 1ul) & CAN_BTR_BRP_MASK); + ((brp - 1ul) & CAN_BTR_BRP_MASK); /* Request initialization "leave". */ CAN_MCR(canport) &= ~CAN_MCR_INRQ; @@ -191,8 +183,7 @@ int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart, /* Wait for acknowledge. */ wait_ack = CAN_MSR_INAK_TIMEOUT; while ((--wait_ack) && - ((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK)) { - } + ((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK)); if ((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK) { ret = 1; @@ -201,7 +192,7 @@ int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart, return ret; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief CAN Filter Init Initialize incoming message filter and assign to FIFO. @@ -251,10 +242,10 @@ void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode, /* Select FIFO0 or FIFO1 as filter assignement. */ if (fifo) { CAN_FFA1R(canport) |= filter_select_bit; /* FIFO1 */ - } - else { + } else { CAN_FFA1R(canport) &= ~filter_select_bit; /* FIFO0 */ } + if (enable) { CAN_FA1R(canport) |= filter_select_bit; /* Activate filter. */ } @@ -263,7 +254,7 @@ void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode, CAN_FMR(canport) &= ~CAN_FMR_FINIT; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief CAN Initialize a 16bit Message ID Mask Filter @param[in] canport Unsigned int32. CAN block register base @ref can_reg_base. @@ -283,7 +274,7 @@ void can_filter_id_mask_16bit_init(u32 canport, u32 nr, u16 id1, u16 mask1, ((u32)id2 << 16) | (u32)mask2, fifo, enable); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief CAN Initialize a 32bit Message ID Mask Filter @param[in] canport Unsigned int32. CAN block register base @ref can_reg_base. @@ -299,7 +290,7 @@ void can_filter_id_mask_32bit_init(u32 canport, u32 nr, u32 id, u32 mask, can_filter_init(canport, nr, true, false, id, mask, fifo, enable); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief CAN Initialize a 16bit Message ID List Filter @param[in] canport Unsigned int32. CAN block register base @ref can_reg_base. @@ -319,7 +310,7 @@ void can_filter_id_list_16bit_init(u32 canport, u32 nr, u16 id1, u16 id2, ((u32)id3 << 16) | (u32)id4, fifo, enable); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief CAN Initialize a 32bit Message ID List Filter @param[in] canport Unsigned int32. CAN block register base @ref can_reg_base. @@ -335,7 +326,7 @@ void can_filter_id_list_32bit_init(u32 canport, u32 nr, u32 id1, u32 id2, can_filter_init(canport, nr, true, true, id1, id2, fifo, enable); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief CAN Enable IRQ @param[in] canport Unsigned int32. CAN block register base @ref can_reg_base. @@ -346,7 +337,7 @@ void can_enable_irq(u32 canport, u32 irq) CAN_IER(canport) |= irq; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief CAN Disable IRQ @param[in] canport Unsigned int32. CAN block register base @ref can_reg_base. @@ -357,7 +348,7 @@ void can_disable_irq(u32 canport, u32 irq) CAN_IER(canport) &= ~irq; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief CAN Transmit Message @param[in] canport Unsigned int32. CAN block register base @ref can_reg_base. @@ -376,7 +367,7 @@ int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data) union { u8 data8[4]; u32 data32; - }tdlxr,tdhxr; + } tdlxr, tdhxr; /* Check which transmit mailbox is empty if any. */ if ((CAN_TSR(canport) & CAN_TSR_TME0) == CAN_TSR_TME0) { @@ -394,53 +385,54 @@ int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data) /* If we have no empty mailbox return with an error. */ if (ret == -1) { - return ret; } if (ext) { /* Set extended ID. */ - CAN_TIxR(canport, mailbox) = (id << CAN_TIxR_EXID_SHIFT) | CAN_TIxR_IDE; + CAN_TIxR(canport, mailbox) = (id << CAN_TIxR_EXID_SHIFT) | + CAN_TIxR_IDE; } else { /* Set standard ID. */ CAN_TIxR(canport, mailbox) = id << CAN_TIxR_STID_SHIFT; } /* Set/clear remote transmission request bit. */ - if (rtr){ + if (rtr) { CAN_TIxR(canport, mailbox) |= CAN_TIxR_RTR; /* Set */ } + /* Set the DLC. */ CAN_TDTxR(canport, mailbox) &= ~CAN_TDTxR_DLC_MASK; CAN_TDTxR(canport, mailbox) |= (length & CAN_TDTxR_DLC_MASK); - switch(length) { - case 8: - tdhxr.data8[3] = data[7]; - /* no break */ - case 7: - tdhxr.data8[2] = data[6]; - /* no break */ - case 6: - tdhxr.data8[1] = data[5]; - /* no break */ - case 5: - tdhxr.data8[0] = data[4]; - /* no break */ - case 4: - tdlxr.data8[3] = data[3]; - /* no break */ - case 3: - tdlxr.data8[2] = data[2]; - /* no break */ - case 2: - tdlxr.data8[1] = data[1]; - /* no break */ - case 1: - tdlxr.data8[0] = data[0]; - /* no break */ - default: - break; + switch (length) { + case 8: + tdhxr.data8[3] = data[7]; + /* no break */ + case 7: + tdhxr.data8[2] = data[6]; + /* no break */ + case 6: + tdhxr.data8[1] = data[5]; + /* no break */ + case 5: + tdhxr.data8[0] = data[4]; + /* no break */ + case 4: + tdlxr.data8[3] = data[3]; + /* no break */ + case 3: + tdlxr.data8[2] = data[2]; + /* no break */ + case 2: + tdlxr.data8[1] = data[1]; + /* no break */ + case 1: + tdlxr.data8[0] = data[0]; + /* no break */ + default: + break; } /* Set the data. */ @@ -453,7 +445,7 @@ int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data) return ret; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief CAN Release FIFO @param[in] canport Unsigned int32. CAN block register base @ref can_reg_base. @@ -463,13 +455,12 @@ void can_fifo_release(u32 canport, u8 fifo) { if (fifo == 0) { CAN_RF0R(canport) |= CAN_RF1R_RFOM1; - } - else { + } else { CAN_RF1R(canport) |= CAN_RF1R_RFOM1; } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief CAN Receive Message @param[in] canport Unsigned int32. CAN block register base @ref can_reg_base. @@ -489,8 +480,8 @@ void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext, union { u8 data8[4]; u32 data32; - }rdlxr,rdhxr; - const u32 fifoid_array[2] = {CAN_FIFO0,CAN_FIFO1}; + } rdlxr, rdhxr; + const u32 fifoid_array[2] = {CAN_FIFO0, CAN_FIFO1}; fifo_id = fifoid_array[fifo]; @@ -498,18 +489,19 @@ void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext, if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_IDE) { *ext = true; /* Get extended CAN ID. */ - *id = (CAN_RIxR(canport, fifo_id) >> CAN_RIxR_EXID_SHIFT) & CAN_RIxR_EXID_MASK; + *id = (CAN_RIxR(canport, fifo_id) >> CAN_RIxR_EXID_SHIFT) & + CAN_RIxR_EXID_MASK; } else { *ext = false; /* Get standard CAN ID. */ - *id = (CAN_RIxR(canport, fifo_id) >> CAN_RIxR_STID_SHIFT) & CAN_RIxR_STID_MASK; + *id = (CAN_RIxR(canport, fifo_id) >> CAN_RIxR_STID_SHIFT) & + CAN_RIxR_STID_MASK; } /* Get remote transmit flag. */ - if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_RTR) { + if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_RTR) { *rtr = true; - } - else { + } else { *rtr = false; } @@ -519,8 +511,9 @@ void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext, /* Get data length. */ *length = CAN_RDTxR(canport, fifo_id) & CAN_RDTxR_DLC_MASK; - /* accelerate reception by copying the CAN data from the controller memory to - * the fast internal RAM */ + /* accelerate reception by copying the CAN data from the controller + * memory to the fast internal RAM + */ rdlxr.data32 = CAN_RDLxR(canport, fifo_id); rdhxr.data32 = CAN_RDHxR(canport, fifo_id); @@ -546,7 +539,7 @@ void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext, data[7] = rdhxr.data8[3]; /* Release the FIFO. */ - if (release){ + if (release) { can_fifo_release(canport, fifo); } } diff --git a/lib/stm32/common/crc_common_all.c b/lib/stm32/common/crc_common_all.c index 92eb1e4b..ac5df995 100644 --- a/lib/stm32/common/crc_common_all.c +++ b/lib/stm32/common/crc_common_all.c @@ -27,7 +27,7 @@ /**@{*/ -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief CRC Reset. Reset the CRC unit and forces the data register to all 1s. @@ -39,7 +39,7 @@ void crc_reset(void) CRC_CR |= CRC_CR_RESET; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief CRC Calculate. Writes a data word to the register, the write operation stalling until the @@ -52,11 +52,11 @@ computation is complete. u32 crc_calculate(u32 data) { CRC_DR = data; - // Data sheet says this blocks until it's ready.... + /* Data sheet says this blocks until it's ready.... */ return CRC_DR; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief CRC Calculate of a Block of Data. Writes data words consecutively to the register, the write operation stalling @@ -70,9 +70,11 @@ until the computation of each word is complete. u32 crc_calculate_block(u32 *datap, int size) { int i; + for (i = 0; i < size; i++) { CRC_DR = datap[i]; } + return CRC_DR; } /**@}*/ diff --git a/lib/stm32/common/dac_common_all.c b/lib/stm32/common/dac_common_all.c index 3a6a8ca3..fa1a3a5a 100644 --- a/lib/stm32/common/dac_common_all.c +++ b/lib/stm32/common/dac_common_all.c @@ -120,12 +120,12 @@ LGPL License Terms @ref lgpl_license #define MASK8 0xFF #define MASK12 0xFFF -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DAC Channel Enable. -Enable a digital to analog converter channel. After setting this enable, the DAC -requires a twakeup time typically around 10 microseconds before it -actually wakes up. +Enable a digital to analog converter channel. After setting this enable, the +DAC requires a twakeup time typically around 10 microseconds before +it actually wakes up. @param[in] dac_channel enum ::data_channel. */ @@ -145,7 +145,7 @@ void dac_enable(data_channel dac_channel) } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DAC Channel Disable. Disable a digital to analog converter channel. @@ -168,13 +168,13 @@ void dac_disable(data_channel dac_channel) } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DAC Channel Output Buffer Enable. -Enable a digital to analog converter channel output drive buffer. This is an optional -amplifying buffer that provides additional drive for the output signal. The -buffer is enabled by default after a reset and needs to be explicitly disabled -if required. +Enable a digital to analog converter channel output drive buffer. This is an +optional amplifying buffer that provides additional drive for the output +signal. The buffer is enabled by default after a reset and needs to be +explicitly disabled if required. @param[in] dac_channel enum ::data_channel. */ @@ -193,12 +193,12 @@ void dac_buffer_enable(data_channel dac_channel) break; } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DAC Channel Output Buffer Disable. -Disable a digital to analog converter channel output drive buffer. Disabling this will -reduce power consumption slightly and will increase the output impedance of the DAC. -The buffers are enabled by default after a reset. +Disable a digital to analog converter channel output drive buffer. Disabling +this will reduce power consumption slightly and will increase the output +impedance of the DAC. The buffers are enabled by default after a reset. @param[in] dac_channel enum ::data_channel. */ @@ -217,7 +217,7 @@ void dac_buffer_disable(data_channel dac_channel) break; } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DAC Channel DMA Enable. Enable a digital to analog converter channel DMA mode (connected to DMA2 channel @@ -242,7 +242,7 @@ void dac_dma_enable(data_channel dac_channel) } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DAC Channel DMA Disable. Disable a digital to analog converter channel DMA mode. @@ -265,13 +265,13 @@ void dac_dma_disable(data_channel dac_channel) } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DAC Channel Trigger Enable. -Enable a digital to analog converter channel external trigger mode. This allows an -external trigger to initiate register transfers from the buffer register to the DAC -output register, followed by a DMA transfer to the buffer register if DMA is enabled. -The trigger source must also be selected. +Enable a digital to analog converter channel external trigger mode. This allows +an external trigger to initiate register transfers from the buffer register to +the DAC output register, followed by a DMA transfer to the buffer register if +DMA is enabled. The trigger source must also be selected. @param[in] dac_channel enum ::data_channel. */ @@ -291,7 +291,7 @@ void dac_trigger_enable(data_channel dac_channel) } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DAC Channel Trigger Disable. Disable a digital to analog converter channel external trigger. @@ -314,14 +314,15 @@ void dac_trigger_disable(data_channel dac_channel) } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Set DAC Channel Trigger Source. -Sets the digital to analog converter trigger source, which can be taken from various -timers, an external trigger or a software trigger. +Sets the digital to analog converter trigger source, which can be taken from +various timers, an external trigger or a software trigger. -@param[in] dac_trig_src u32. Taken from @ref dac_trig2_sel or @ref dac_trig1_sel or -a logical OR of one of each of these to set both channels simultaneously. +@param[in] dac_trig_src u32. Taken from @ref dac_trig2_sel or @ref +dac_trig1_sel or a logical OR of one of each of these to set both channels +simultaneously. */ void dac_set_trigger_source(u32 dac_trig_src) @@ -329,17 +330,17 @@ void dac_set_trigger_source(u32 dac_trig_src) DAC_CR |= dac_trig_src; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Enable and Set DAC Channel Waveform Generation. -Enable the digital to analog converter waveform generation as either pseudo-random -noise or triangular wave. These signals are superimposed on existing output values -in the DAC output registers. +Enable the digital to analog converter waveform generation as either +pseudo-random noise or triangular wave. These signals are superimposed on +existing output values in the DAC output registers. @note The DAC trigger must be enabled for this to work. -@param[in] dac_wave_ens u32. Taken from @ref dac_wave1_en or @ref dac_wave2_en or -a logical OR of one of each of these to set both channels simultaneously. +@param[in] dac_wave_ens u32. Taken from @ref dac_wave1_en or @ref dac_wave2_en +or a logical OR of one of each of these to set both channels simultaneously. */ void dac_set_waveform_generation(u32 dac_wave_ens) @@ -347,7 +348,7 @@ void dac_set_waveform_generation(u32 dac_wave_ens) DAC_CR |= dac_wave_ens; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Disable DAC Channel Waveform Generation. Disable a digital to analog converter channel superimposed waveform generation. @@ -370,22 +371,24 @@ void dac_disable_waveform_generation(data_channel dac_channel) } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Set DAC Channel LFSR Mask or Triangle Wave Amplitude. -Sets the digital to analog converter superimposed waveform generation characteristics. -@li If the noise generation mode is set, this sets the length of the PRBS sequence and -hence the amplitude of the output noise signal. Default setting is length 1. -@li If the triangle wave generation mode is set, this sets the amplitude of the -output signal as 2^(n)-1 where n is the parameter value. Default setting is 1. +Sets the digital to analog converter superimposed waveform generation +characteristics. @li If the noise generation mode is set, this sets the length +of the PRBS sequence and hence the amplitude of the output noise signal. +Default setting is length 1. @li If the triangle wave generation mode is set, +this sets the amplitude of the output signal as 2^(n)-1 where n is the +parameter value. Default setting is 1. -@note High amplitude levels of these waveforms can overload the DAC and distort the -signal output. -@note This must be called before enabling the DAC as the settings will then become read-only. +@note High amplitude levels of these waveforms can overload the DAC and distort +the signal output. +@note This must be called before enabling the DAC as the settings will then +become read-only. @note The DAC trigger must be enabled for this to work. -@param[in] dac_mamp u32. Taken from @ref dac_mamp2 or @ref dac_mamp1 or a logical OR -of one of each of these to set both channels simultaneously. +@param[in] dac_mamp u32. Taken from @ref dac_mamp2 or @ref dac_mamp1 or a +logical OR of one of each of these to set both channels simultaneously. */ void dac_set_waveform_characteristics(u32 dac_mamp) @@ -393,7 +396,7 @@ void dac_set_waveform_characteristics(u32 dac_mamp) DAC_CR |= dac_mamp; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Load DAC Data Register. Loads the appropriate digital to analog converter data register with 12 or 8 bit @@ -407,10 +410,10 @@ data to be converted on a channel. The data can be aligned as follows: @param[in] dac_channel enum ::data_channel. */ -void dac_load_data_buffer_single(u16 dac_data, data_align dac_data_format, data_channel dac_channel) +void dac_load_data_buffer_single(u16 dac_data, data_align dac_data_format, + data_channel dac_channel) { - if (dac_channel == CHANNEL_1) - { + if (dac_channel == CHANNEL_1) { switch (dac_data_format) { case RIGHT8: DAC_DHR8R1 = dac_data; @@ -422,9 +425,7 @@ void dac_load_data_buffer_single(u16 dac_data, data_align dac_data_format, data_ DAC_DHR12L1 = dac_data; break; } - } - else if (dac_channel == CHANNEL_2) - { + } else if (dac_channel == CHANNEL_2) { switch (dac_data_format) { case RIGHT8: DAC_DHR8R2 = dac_data; @@ -439,7 +440,7 @@ void dac_load_data_buffer_single(u16 dac_data, data_align dac_data_format, data_ } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Load DAC Dual Data Register. Loads the appropriate digital to analog converter dual data register with 12 or @@ -449,25 +450,29 @@ identically. @param[in] dac_data1 u16 for channel 1 with appropriate alignment. @param[in] dac_data2 u16 for channel 2 with appropriate alignment. -@param[in] dac_data_format enum ::data_align. Right or left aligned, and 8 or 12 bit. +@param[in] dac_data_format enum ::data_align. Right or left aligned, and 8 or +12 bit. */ -void dac_load_data_buffer_dual(u16 dac_data1, u16 dac_data2, data_align dac_data_format) +void dac_load_data_buffer_dual(u16 dac_data1, u16 dac_data2, + data_align dac_data_format) { switch (dac_data_format) { case RIGHT8: DAC_DHR8RD = ((dac_data1 & MASK8) | ((dac_data2 & MASK8) << 8)); break; case RIGHT12: - DAC_DHR12RD = ((dac_data1 & MASK12) | ((dac_data2 & MASK12) << 16)); + DAC_DHR12RD = ((dac_data1 & MASK12) | + ((dac_data2 & MASK12) << 16)); break; case LEFT12: - DAC_DHR12LD = ((dac_data1 & MASK12) | ((dac_data2 & MASK12) << 16)); + DAC_DHR12LD = ((dac_data1 & MASK12) | + ((dac_data2 & MASK12) << 16)); break; } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Trigger the DAC by a Software Trigger. If the trigger source is set to be a software trigger, cause a trigger to occur. diff --git a/lib/stm32/common/dma_common_f13.c b/lib/stm32/common/dma_common_f13.c index b3e31ced..8bd54f5b 100644 --- a/lib/stm32/common/dma_common_f13.c +++ b/lib/stm32/common/dma_common_f13.c @@ -40,7 +40,7 @@ LGPL License Terms @ref lgpl_license #include -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Reset The channel is disabled and configuration registers are cleared. @@ -63,7 +63,7 @@ void dma_channel_reset(u32 dma, u8 channel) DMA_IFCR(dma) |= DMA_IFCR_CIF(channel); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Clear Interrupt Flag The interrupt flag for the channel is cleared. More than one interrupt for the @@ -71,7 +71,8 @@ same channel may be cleared by using the logical OR of the interrupt flags. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: @ref dma_ch -@param[in] interrupts unsigned int32. Logical OR of interrupt numbers: @ref dma_if_offset +@param[in] interrupts unsigned int32. Logical OR of interrupt numbers: @ref +dma_if_offset */ void dma_clear_interrupt_flags(u32 dma, u8 channel, u32 interrupts) @@ -81,7 +82,7 @@ void dma_clear_interrupt_flags(u32 dma, u8 channel, u32 interrupts) DMA_IFCR(dma) = flags; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Read Interrupt Flag The interrupt flag for the channel is returned. @@ -99,7 +100,7 @@ bool dma_get_interrupt_flag(u32 dma, u8 channel, u32 interrupt) return ((DMA_ISR(dma) & flag) > 0); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Enable Memory to Memory Transfers Memory to memory transfers do not require a trigger to activate each transfer. @@ -116,7 +117,7 @@ void dma_enable_mem2mem_mode(u32 dma, u8 channel) DMA_CCR(dma, channel) &= ~DMA_CCR_CIRC; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Set Priority Channel Priority has four levels: low to very high. This has precedence over the @@ -133,7 +134,7 @@ void dma_set_priority(u32 dma, u8 channel, u32 prio) DMA_CCR(dma, channel) |= prio; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Set Memory Word Width Set the memory word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for @@ -151,16 +152,17 @@ void dma_set_memory_size(u32 dma, u8 channel, u32 mem_size) DMA_CCR(dma, channel) |= mem_size; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Set Peripheral Word Width -Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for -alignment information if the source and destination widths do not match, or +Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet +for alignment information if the source and destination widths do not match, or if the peripheral does not support byte or half-word writes. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 -@param[in] peripheral_size unsigned int32. Peripheral word width @ref dma_ch_perwidth. +@param[in] peripheral_size unsigned int32. Peripheral word width @ref +dma_ch_perwidth. */ void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size) @@ -169,7 +171,7 @@ void dma_set_peripheral_size(u32 dma, u8 channel, u32 peripheral_size) DMA_CCR(dma, channel) |= peripheral_size; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Enable Memory Increment after Transfer Following each transfer the current memory address is incremented by @@ -185,7 +187,7 @@ void dma_enable_memory_increment_mode(u32 dma, u8 channel) DMA_CCR(dma, channel) |= DMA_CCR_MINC; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Disable Memory Increment after Transfer @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @@ -197,7 +199,7 @@ void dma_disable_memory_increment_mode(u32 dma, u8 channel) DMA_CCR(dma, channel) &= ~DMA_CCR_MINC; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Enable Peripheral Increment after Transfer Following each transfer the current peripheral address is incremented by @@ -213,7 +215,7 @@ void dma_enable_peripheral_increment_mode(u32 dma, u8 channel) DMA_CCR(dma, channel) |= DMA_CCR_PINC; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Disable Peripheral Increment after Transfer @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @@ -225,7 +227,7 @@ void dma_disable_peripheral_increment_mode(u32 dma, u8 channel) DMA_CCR(dma, channel) &= ~DMA_CCR_PINC; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Enable Memory Circular Mode After the number of bytes/words to be transferred has been completed, the @@ -245,7 +247,7 @@ void dma_enable_circular_mode(u32 dma, u8 channel) DMA_CCR(dma, channel) &= ~DMA_CCR_MEM2MEM; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Enable Transfers from a Peripheral The data direction is set to read from a peripheral. @@ -259,7 +261,7 @@ void dma_set_read_from_peripheral(u32 dma, u8 channel) DMA_CCR(dma, channel) &= ~DMA_CCR_DIR; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Enable Transfers from Memory The data direction is set to read from memory. @@ -273,7 +275,7 @@ void dma_set_read_from_memory(u32 dma, u8 channel) DMA_CCR(dma, channel) |= DMA_CCR_DIR; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Enable Interrupt on Transfer Error @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @@ -285,7 +287,7 @@ void dma_enable_transfer_error_interrupt(u32 dma, u8 channel) DMA_CCR(dma, channel) |= DMA_CCR_TEIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Disable Interrupt on Transfer Error @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @@ -297,7 +299,7 @@ void dma_disable_transfer_error_interrupt(u32 dma, u8 channel) DMA_CCR(dma, channel) &= ~DMA_CCR_TEIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Enable Interrupt on Transfer Half Complete @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @@ -309,7 +311,7 @@ void dma_enable_half_transfer_interrupt(u32 dma, u8 channel) DMA_CCR(dma, channel) |= DMA_CCR_HTIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Disable Interrupt on Transfer Half Complete @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @@ -321,7 +323,7 @@ void dma_disable_half_transfer_interrupt(u32 dma, u8 channel) DMA_CCR(dma, channel) &= ~DMA_CCR_HTIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Enable Interrupt on Transfer Complete @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @@ -333,7 +335,7 @@ void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel) DMA_CCR(dma, channel) |= DMA_CCR_TCIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Disable Interrupt on Transfer Complete @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @@ -345,7 +347,7 @@ void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel) DMA_CCR(dma, channel) &= ~DMA_CCR_TCIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Enable @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @@ -357,10 +359,11 @@ void dma_enable_channel(u32 dma, u8 channel) DMA_CCR(dma, channel) |= DMA_CCR_EN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Disable -@note The DMA channel registers retain their values when the channel is disabled. +@note The DMA channel registers retain their values when the channel is +disabled. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 @@ -371,14 +374,14 @@ void dma_disable_channel(u32 dma, u8 channel) DMA_CCR(dma, channel) &= ~DMA_CCR_EN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Set the Peripheral Address -Set the address of the peripheral register to or from which data is to be transferred. -Refer to the documentation for the specific peripheral. +Set the address of the peripheral register to or from which data is to be +transferred. Refer to the documentation for the specific peripheral. -@note The DMA channel must be disabled before setting this address. This function -has no effect if the channel is enabled. +@note The DMA channel must be disabled before setting this address. This +function has no effect if the channel is enabled. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 @@ -387,15 +390,16 @@ has no effect if the channel is enabled. void dma_set_peripheral_address(u32 dma, u8 channel, u32 address) { - if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) + if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) { DMA_CPAR(dma, channel) = (u32) address; + } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Set the Base Memory Address -@note The DMA channel must be disabled before setting this address. This function -has no effect if the channel is enabled. +@note The DMA channel must be disabled before setting this address. This +function has no effect if the channel is enabled. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 @@ -404,19 +408,21 @@ has no effect if the channel is enabled. void dma_set_memory_address(u32 dma, u8 channel, u32 address) { - if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) + if (!(DMA_CCR(dma, channel) & DMA_CCR_EN)) { DMA_CMAR(dma, channel) = (u32) address; + } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Set the Transfer Block Size -@note The DMA channel must be disabled before setting this count value. The count -is not changed if the channel is enabled. +@note The DMA channel must be disabled before setting this count value. The +count is not changed if the channel is enabled. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2 -@param[in] number unsigned int16. Number of data words to transfer (65535 maximum). +@param[in] number unsigned int16. Number of data words to transfer (65535 +maximum). */ void dma_set_number_of_data(u32 dma, u8 channel, u16 number) diff --git a/lib/stm32/common/dma_common_f24.c b/lib/stm32/common/dma_common_f24.c index 6f341a7a..921ebf06 100644 --- a/lib/stm32/common/dma_common_f24.c +++ b/lib/stm32/common/dma_common_f24.c @@ -1,6 +1,7 @@ /** @addtogroup dma_file -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies +@author @htmlonly © @endhtmlonly 2012 +Ken Sarkies This library supports the DMA Control System in the STM32F2 and STM32F4 series of ARM Cortex Microcontrollers by ST Microelectronics. @@ -47,7 +48,7 @@ LGPL License Terms @ref lgpl_license #include -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Reset The specified stream is disabled and configuration registers are cleared. @@ -72,17 +73,14 @@ void dma_stream_reset(u32 dma, u8 stream) DMA_SFCR(dma, stream) = 0x21; /* Reset all stream interrupt flags using the interrupt flag clear register. */ u32 mask = DMA_ISR_MASK(stream); - if (stream < 4) - { + if (stream < 4) { DMA_LIFCR(dma) |= mask; - } - else - { + } else { DMA_HIFCR(dma) |= mask; - } + } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Clear Interrupt Flag The interrupt flag for the stream is cleared. More than one interrupt for the @@ -90,25 +88,25 @@ same stream may be cleared by using the bitwise OR of the interrupt flags. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number -@param[in] interrupts unsigned int32. Bitwise OR of interrupt numbers: @ref dma_if_offset +@param[in] interrupts unsigned int32. Bitwise OR of interrupt numbers: @ref +dma_if_offset */ void dma_clear_interrupt_flags(u32 dma, u8 stream, u32 interrupts) { -/* Get offset to interrupt flag location in stream field */ + /* Get offset to interrupt flag location in stream field */ u32 flags = (interrupts << DMA_ISR_OFFSET(stream)); -/* First four streams are in low register. Flag clear must be set then reset. */ - if (stream < 4) - { + /* First four streams are in low register. Flag clear must be set then + * reset. + */ + if (stream < 4) { DMA_LIFCR(dma) = flags; - } - else - { + } else { DMA_HIFCR(dma) = flags; } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Read Interrupt Flag The interrupt flag for the stream is returned. @@ -121,15 +119,19 @@ The interrupt flag for the stream is returned. bool dma_get_interrupt_flag(u32 dma, u8 stream, u32 interrupt) { -/* get offset to interrupt flag location in stream field. -Assumes stream and interrupt parameters are integers */ + /* get offset to interrupt flag location in stream field. Assumes + * stream and interrupt parameters are integers. + */ u32 flag = (interrupt << DMA_ISR_OFFSET(stream)); -/* First four streams are in low register */ - if (stream < 4) return ((DMA_LISR(dma) & flag) > 0); - else return ((DMA_HISR(dma) & flag) > 0); + /* First four streams are in low register */ + if (stream < 4) { + return ((DMA_LISR(dma) & flag) > 0); + } else { + return ((DMA_HISR(dma) & flag) > 0); + } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Enable Transfer Direction Set peripheral to memory, memory to peripheral or memory to memory. If memory @@ -146,16 +148,18 @@ Ensure that the stream is disabled otherwise the setting will not be changed. void dma_set_transfer_mode(u32 dma, u8 stream, u32 direction) { u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_DIR_MASK); -/* Disable circular and double buffer modes if memory to memory transfers -are in effect (Direct Mode is automatically disabled by hardware) */ - if (direction == DMA_SxCR_DIR_MEM_TO_MEM) - { + /* Disable circular and double buffer modes if memory to memory + * transfers are in effect. (Direct Mode is automatically disabled by + * hardware) + */ + if (direction == DMA_SxCR_DIR_MEM_TO_MEM) { reg32 &= ~(DMA_SxCR_CIRC | DMA_SxCR_DBM); } + DMA_SCR(dma, stream) = (reg32 | direction); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Set Priority Stream Priority has four levels: low to very high. This has precedence over the @@ -175,7 +179,7 @@ void dma_set_priority(u32 dma, u8 stream, u32 prio) DMA_SCR(dma, stream) |= prio; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Set Memory Word Width Set the memory word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for @@ -190,23 +194,23 @@ Ensure that the stream is disabled otherwise the setting will not be changed. void dma_set_memory_size(u32 dma, u8 stream, u32 mem_size) { - DMA_SCR(dma, stream) &= ~(DMA_SxCR_MSIZE_MASK); DMA_SCR(dma, stream) |= mem_size; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Set Peripheral Word Width -Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet for -alignment information if the source and destination widths do not match, or +Set the peripheral word width 8 bits, 16 bits, or 32 bits. Refer to datasheet +for alignment information if the source and destination widths do not match, or if the peripheral does not support byte or half-word writes. Ensure that the stream is disabled otherwise the setting will not be changed. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number -@param[in] peripheral_size unsigned int32. Peripheral word width @ref dma_st_perwidth. +@param[in] peripheral_size unsigned int32. Peripheral word width @ref +dma_st_perwidth. */ void dma_set_peripheral_size(u32 dma, u8 stream, u32 peripheral_size) @@ -215,7 +219,7 @@ void dma_set_peripheral_size(u32 dma, u8 stream, u32 peripheral_size) DMA_SCR(dma, stream) |= peripheral_size; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Enable Memory Increment after Transfer Following each transfer the current memory address is incremented by @@ -233,7 +237,7 @@ void dma_enable_memory_increment_mode(u32 dma, u8 stream) DMA_SCR(dma, stream) |= DMA_SxCR_MINC; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Disable Memory Increment after Transfer Ensure that the stream is disabled otherwise the setting will not be changed. @@ -247,7 +251,7 @@ void dma_disable_memory_increment_mode(u32 dma, u8 stream) DMA_SCR(dma, stream) &= ~DMA_SxCR_MINC; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Enable Variable Sized Peripheral Increment after Transfer Following each transfer the current peripheral address is incremented by @@ -266,7 +270,7 @@ void dma_enable_peripheral_increment_mode(u32 dma, u8 stream) DMA_SCR(dma, stream) = (reg32 & ~DMA_SxCR_PINCOS); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Disable Peripheral Increment after Transfer Ensure that the stream is disabled otherwise the setting will not be changed. @@ -280,7 +284,7 @@ void dma_disable_peripheral_increment_mode(u32 dma, u8 stream) DMA_SCR(dma, stream) &= ~DMA_SxCR_PINC; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Channel Enable Fixed Sized Peripheral Increment after Transfer Following each transfer the current peripheral address is incremented by @@ -298,7 +302,7 @@ void dma_enable_fixed_peripheral_increment_mode(u32 dma, u8 stream) DMA_SCR(dma, stream) |= (DMA_SxCR_PINC | DMA_SxCR_PINCOS); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Enable Memory Circular Mode After the number of bytes/words to be transferred has been completed, the @@ -320,7 +324,7 @@ void dma_enable_circular_mode(u32 dma, u8 stream) DMA_SCR(dma, stream) |= DMA_SxCR_CIRC; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Channel Select Associate an input channel to the stream. Not every channel is allocated to a @@ -339,7 +343,7 @@ void dma_channel_select(u32 dma, u8 stream, u32 channel) DMA_SCR(dma, stream) |= channel; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Set Memory Burst Configuration Set the memory burst type to none, 4 8 or 16 word length. This is forced to none @@ -358,7 +362,7 @@ void dma_set_memory_burst(u32 dma, u8 stream, u32 burst) DMA_SCR(dma, stream) = (reg32 | burst); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Set Peripheral Burst Configuration Set the memory burst type to none, 4 8 or 16 word length. This is forced to none @@ -377,11 +381,11 @@ void dma_set_peripheral_burst(u32 dma, u8 stream, u32 burst) DMA_SCR(dma, stream) = (reg32 | burst); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Set Initial Target Memory -In double buffered mode, set the target memory (M0 or M1) to be used for the first -transfer. +In double buffered mode, set the target memory (M0 or M1) to be used for the +first transfer. Ensure that the stream is disabled otherwise the setting will not be changed. @@ -393,17 +397,20 @@ Ensure that the stream is disabled otherwise the setting will not be changed. void dma_set_initial_target(u32 dma, u8 stream, u8 memory) { u32 reg32 = (DMA_SCR(dma, stream) & ~DMA_SxCR_CT); - if (memory == 1) reg32 |= DMA_SxCR_CT; + if (memory == 1) { + reg32 |= DMA_SxCR_CT; + } + DMA_SCR(dma, stream) = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Read Current Memory Target -In double buffer mode, return the current memory target (M0 or M1). It is possible -to update the memory pointer in the register that is not currently in -use. An attempt to change the register currently in use will cause the stream -to be disabled and the transfer error flag to be set. +In double buffer mode, return the current memory target (M0 or M1). It is +possible to update the memory pointer in the register that is not +currently in use. An attempt to change the register currently in use will cause +the stream to be disabled and the transfer error flag to be set. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number @@ -412,11 +419,14 @@ to be disabled and the transfer error flag to be set. u8 dma_get_target(u32 dma, u8 stream) { - if (DMA_SCR(dma, stream) & DMA_SxCR_CT) return 1; + if (DMA_SCR(dma, stream) & DMA_SxCR_CT) { + return 1; + } + return 0; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Enable Double Buffer Mode Double buffer mode is used for memory to/from peripheral transfers only, and in @@ -436,7 +446,7 @@ void dma_enable_double_buffer_mode(u32 dma, u8 stream) DMA_SCR(dma, stream) |= DMA_SxCR_DBM; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Disable Double Buffer Mode @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @@ -448,7 +458,7 @@ void dma_disable_double_buffer_mode(u32 dma, u8 stream) DMA_SCR(dma, stream) &= ~DMA_SxCR_DBM; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Set Peripheral Flow Control Set the peripheral to control DMA flow. Useful when the number of transfers is @@ -465,7 +475,7 @@ void dma_set_peripheral_flow_control(u32 dma, u8 stream) DMA_SCR(dma, stream) |= DMA_SxCR_PFCTRL; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Set DMA Flow Control Set the DMA controller to control DMA flow. This is the default. @@ -481,7 +491,7 @@ void dma_set_dma_flow_control(u32 dma, u8 stream) DMA_SCR(dma, stream) &= ~DMA_SxCR_PFCTRL; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Enable Interrupt on Transfer Error @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @@ -494,7 +504,7 @@ void dma_enable_transfer_error_interrupt(u32 dma, u8 stream) DMA_SCR(dma, stream) |= DMA_SxCR_TEIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Disable Interrupt on Transfer Error @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @@ -506,7 +516,7 @@ void dma_disable_transfer_error_interrupt(u32 dma, u8 stream) DMA_SCR(dma, stream) &= ~DMA_SxCR_TEIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Enable Interrupt on Transfer Half Complete @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @@ -519,7 +529,7 @@ void dma_enable_half_transfer_interrupt(u32 dma, u8 stream) DMA_SCR(dma, stream) |= DMA_SxCR_HTIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Disable Interrupt on Transfer Half Complete @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @@ -531,7 +541,7 @@ void dma_disable_half_transfer_interrupt(u32 dma, u8 stream) DMA_SCR(dma, stream) &= ~DMA_SxCR_HTIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Enable Interrupt on Transfer Complete @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @@ -544,7 +554,7 @@ void dma_enable_transfer_complete_interrupt(u32 dma, u8 stream) DMA_SCR(dma, stream) |= DMA_SxCR_TCIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Disable Interrupt on Transfer Complete @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @@ -556,7 +566,7 @@ void dma_disable_transfer_complete_interrupt(u32 dma, u8 stream) DMA_SCR(dma, stream) &= ~DMA_SxCR_TCIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Enable Interrupt on Direct Mode Error @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @@ -569,7 +579,7 @@ void dma_enable_direct_mode_error_interrupt(u32 dma, u8 stream) DMA_SCR(dma, stream) |= DMA_SxCR_DMEIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Disable Interrupt on Direct Mode Error @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @@ -581,7 +591,7 @@ void dma_disable_direct_mode_error_interrupt(u32 dma, u8 stream) DMA_SCR(dma, stream) &= ~DMA_SxCR_DMEIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Enable Interrupt on FIFO Error @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @@ -594,7 +604,7 @@ void dma_enable_fifo_error_interrupt(u32 dma, u8 stream) DMA_SFCR(dma, stream) |= DMA_SxFCR_FEIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Disable Interrupt on FIFO Error @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @@ -606,7 +616,7 @@ void dma_disable_fifo_error_interrupt(u32 dma, u8 stream) DMA_SFCR(dma, stream) &= ~DMA_SxFCR_FEIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Get FIFO Status Status of FIFO (empty. full or partial filled states) is returned. This has no @@ -619,10 +629,10 @@ meaning if direct mode is enabled (as the FIFO is not used). u32 dma_fifo_status(u32 dma, u8 stream) { - return (DMA_SFCR(dma, stream) & DMA_SxFCR_FS_MASK); + return DMA_SFCR(dma, stream) & DMA_SxFCR_FS_MASK; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Enable Direct Mode Direct mode is the default. Data is transferred as soon as a DMA request is @@ -638,7 +648,7 @@ void dma_enable_direct_mode(u32 dma, u8 stream) DMA_SFCR(dma, stream) &= ~DMA_SxFCR_DMDIS; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Enable FIFO Mode Data is transferred via a FIFO. @@ -652,7 +662,7 @@ void dma_enable_fifo_mode(u32 dma, u8 stream) DMA_SFCR(dma, stream) |= DMA_SxFCR_DMDIS; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Set FIFO Threshold This is the filled level at which data is transferred out of the FIFO to the @@ -669,7 +679,7 @@ void dma_set_fifo_threshold(u32 dma, u8 stream, u32 threshold) DMA_SFCR(dma, stream) = (reg32 | threshold); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Enable @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @@ -681,7 +691,7 @@ void dma_enable_stream(u32 dma, u8 stream) DMA_SCR(dma, stream) |= DMA_SxCR_EN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Disable @note The DMA stream registers retain their values when the stream is disabled. @@ -695,11 +705,11 @@ void dma_disable_stream(u32 dma, u8 stream) DMA_SCR(dma, stream) &= ~DMA_SxCR_EN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Set the Peripheral Address -Set the address of the peripheral register to or from which data is to be transferred. -Refer to the documentation for the specific peripheral. +Set the address of the peripheral register to or from which data is to be +transferred. Refer to the documentation for the specific peripheral. @note The DMA stream must be disabled before setting this address. This function has no effect if the stream is enabled. @@ -711,11 +721,12 @@ has no effect if the stream is enabled. void dma_set_peripheral_address(u32 dma, u8 stream, u32 address) { - if (!(DMA_SCR(dma, stream) & DMA_SxCR_EN)) + if (!(DMA_SCR(dma, stream) & DMA_SxCR_EN)) { DMA_SPAR(dma, stream) = (u32 *) address; + } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Set the Base Memory Address 0 Set the address pointer to the memory location for DMA transfers. The DMA stream @@ -733,11 +744,13 @@ This is the default base memory address used in direct mode. void dma_set_memory_address(u32 dma, u8 stream, u32 address) { u32 reg32 = DMA_SCR(dma, stream); - if ( !(reg32 & DMA_SxCR_EN) || ((reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM)) ) + if (!(reg32 & DMA_SxCR_EN) || + ((reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM))) { DMA_SM0AR(dma, stream) = (u32 *) address; + } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Set the Base Memory Address 1 Set the address pointer to the memory location for DMA transfers. The DMA stream @@ -753,11 +766,13 @@ to change this in double buffer mode when the current target is memory area 0 void dma_set_memory_address_1(u32 dma, u8 stream, u32 address) { u32 reg32 = DMA_SCR(dma, stream); - if ( !(reg32 & DMA_SxCR_EN) || (!(reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM)) ) + if (!(reg32 & DMA_SxCR_EN) || + (!(reg32 & DMA_SxCR_CT) && (reg32 & DMA_SxCR_DBM))) { DMA_SM1AR(dma, stream) = (u32 *) address; + } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief DMA Stream Set the Transfer Block Size @note The DMA stream must be disabled before setting this count value. The count @@ -765,7 +780,8 @@ is not changed if the stream is enabled. @param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2 @param[in] stream unsigned int8. Stream number: @ref dma_st_number -@param[in] number unsigned int16. Number of data words to transfer (65535 maximum). +@param[in] number unsigned int16. Number of data words to transfer (65535 +maximum). */ void dma_set_number_of_data(u32 dma, u8 stream, u16 number) diff --git a/lib/stm32/common/flash_common_f24.c b/lib/stm32/common/flash_common_f24.c index 17cc561d..ab5a1099 100644 --- a/lib/stm32/common/flash_common_f24.c +++ b/lib/stm32/common/flash_common_f24.c @@ -148,8 +148,7 @@ void flash_lock_option_bytes(void) void flash_wait_for_last_operation(void) { - while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY) - ; + while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY); } void flash_program_double_word(u32 address, u64 data) @@ -218,13 +217,15 @@ void flash_program_byte(u32 address, u8 data) FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */ } -void flash_program(u32 address, u8* data, u32 len) +void flash_program(u32 address, u8 *data, u32 len) { - /* TODO: Use dword and word size program operations where possible for turbo - * speed. */ - u32 i; - for (i=0; i. */ -#define WEAK __attribute__ ((weak)) +#define WEAK __attribute__((weak)) #include /**@{*/ -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Set a Group of Pins Atomic Set one or more pins of the given GPIO port to 1 in an atomic operation. @param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id @param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id - If multiple pins are to be changed, use logical OR '|' to separate them. + If multiple pins are to be changed, use logical OR '|' to separate + them. */ void gpio_set(u32 gpioport, u16 gpios) { GPIO_BSRR(gpioport) = gpios; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Clear a Group of Pins Atomic Clear one or more pins of the given GPIO port to 0 in an atomic operation. @param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id @param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id - If multiple pins are to be changed, use logical OR '|' to separate them. + If multiple pins are to be changed, use logical OR '|' to separate + them. */ void gpio_clear(u32 gpioport, u16 gpios) { GPIO_BSRR(gpioport) = (gpios << 16); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Read a Group of Pins. @param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id @param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id - If multiple pins are to be read, use logical OR '|' to separate them. -@return Unsigned int16 value of the pin values. The bit position of the pin value - returned corresponds to the pin number. + If multiple pins are to be read, use logical OR '|' to separate + them. +@return Unsigned int16 value of the pin values. The bit position of the pin + value returned corresponds to the pin number. */ u16 gpio_get(u32 gpioport, u16 gpios) { return gpio_port_read(gpioport) & gpios; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Toggle a Group of Pins Toggle one or more pins of the given GPIO port. This is not an atomic operation. @param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id @param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id - If multiple pins are to be changed, use logical OR '|' to separate them. + If multiple pins are to be changed, use logical OR '|' to separate + them. */ void gpio_toggle(u32 gpioport, u16 gpios) { GPIO_ODR(gpioport) ^= gpios; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Read from a Port Read the current value of the given GPIO port. Only the lower 16 bits contain @@ -99,7 +103,7 @@ u16 gpio_port_read(u32 gpioport) return (u16)GPIO_IDR(gpioport); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Write to a Port Write a value to the given GPIO port. @@ -112,15 +116,17 @@ void gpio_port_write(u32 gpioport, u16 data) GPIO_ODR(gpioport) = data; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Lock the Configuration of a Group of Pins -The configuration of one or more pins of the given GPIO port is locked. There is -no mechanism to unlock these via software. Unlocking occurs at the next reset. +The configuration of one or more pins of the given GPIO port is locked. There +is no mechanism to unlock these via software. Unlocking occurs at the next +reset. @param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id @param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id - If multiple pins are to be locked, use logical OR '|' to separate them. + If multiple pins are to be locked, use logical OR '|' to separate + them. */ void gpio_port_config_lock(u32 gpioport, u16 gpios) { @@ -133,8 +139,10 @@ void gpio_port_config_lock(u32 gpioport, u16 gpios) reg32 = GPIO_LCKR(gpioport); /* Read LCKK. */ reg32 = GPIO_LCKR(gpioport); /* Read LCKK again. */ - /* Tell the compiler the variable is actually used. It will get optimized out anyways. */ - reg32 = reg32; + /* Tell the compiler the variable is actually used. It will get + * optimized out anyways. + */ + reg32 = reg32; /* If (reg32 & GPIO_LCKK) is true, the lock is now active. */ } diff --git a/lib/stm32/common/gpio_common_f24.c b/lib/stm32/common/gpio_common_f24.c index dfa2bacd..b8bd2747 100644 --- a/lib/stm32/common/gpio_common_f24.c +++ b/lib/stm32/common/gpio_common_f24.c @@ -1,20 +1,22 @@ /** @addtogroup gpio_file -@author @htmlonly © @endhtmlonly 2009 Uwe Hermann -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies +@author @htmlonly © @endhtmlonly 2009 +Uwe Hermann +@author @htmlonly © @endhtmlonly 2012 +Ken Sarkies Each I/O port has 16 individually configurable bits. Many I/O pins share GPIO -functionality with a number of alternate functions and must be configured to the -alternate function mode if these are to be accessed. A feature is available to -remap alternative functions to a limited set of alternative pins in the event -of a clash of requirements. +functionality with a number of alternate functions and must be configured to +the alternate function mode if these are to be accessed. A feature is available +to remap alternative functions to a limited set of alternative pins in the +event of a clash of requirements. -The data registers associated with each port for input and output are 32 bit with -the upper 16 bits unused. The output buffer must be written as a 32 bit word, but -individual bits may be set or reset separately in atomic operations to avoid race -conditions during interrupts. Bits may also be individually locked to prevent -accidental configuration changes. Once locked the configuration cannot be changed -until after the next reset. +The data registers associated with each port for input and output are 32 bit +with the upper 16 bits unused. The output buffer must be written as a 32 bit +word, but individual bits may be set or reset separately in atomic operations +to avoid race conditions during interrupts. Bits may also be individually +locked to prevent accidental configuration changes. Once locked the +configuration cannot be changed until after the next reset. Each port bit can be configured as analog or digital input, the latter can be floating or pulled up or down. As outputs they can be configured as either @@ -29,9 +31,9 @@ Example 1: Push-pull digital output actions with pullup on ports C2 and C9 @code gpio_mode_setup(GPIOC, GPIO_MODE_OUTPUT, - GPIO_PUPD_PULLUP, GPIO2 | GPIO9); + GPIO_PUPD_PULLUP, GPIO2 | GPIO9); gpio_output_options(GPIOC, GPIO_OTYPE_PP, - GPIO_OSPEED_25MHZ, GPIO2 | GPIO9); + GPIO_OSPEED_25MHZ, GPIO2 | GPIO9); gpio_set(GPIOC, GPIO2 | GPIO9); gpio_clear(GPIOC, GPIO2); gpio_toggle(GPIOC, GPIO2 | GPIO9); @@ -42,7 +44,7 @@ Example 2: Digital input on port C12 with pullup @code gpio_mode_setup(GPIOC, GPIO_MODE_INPUT, - GPIO_PUPD_PULLUP, GPIO12); + GPIO_PUPD_PULLUP, GPIO12); reg16 = gpio_port_read(GPIOC); @endcode @@ -70,7 +72,7 @@ Example 2: Digital input on port C12 with pullup #include -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Set GPIO Pin Mode Sets the Pin Direction and Analog/Digital Mode, and Output Pin Pullup, @@ -78,9 +80,11 @@ for a set of GPIO pins on a given GPIO port. @param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id @param[in] mode Unsigned int8. Pin mode @ref gpio_mode -@param[in] pull_up_down Unsigned int8. Pin pullup/pulldown configuration @ref gpio_pup +@param[in] pull_up_down Unsigned int8. Pin pullup/pulldown configuration @ref +gpio_pup @param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id - If multiple pins are to be set, use bitwise OR '|' to separate them. + If multiple pins are to be set, use bitwise OR '|' to separate + them. */ void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios) { @@ -95,8 +99,9 @@ void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios) pupd = GPIO_PUPDR(gpioport); for (i = 0; i < 16; i++) { - if (!((1 << i) & gpios)) + if (!((1 << i) & gpios)) { continue; + } moder &= ~GPIO_MODE_MASK(i); moder |= GPIO_MODE(i, mode); @@ -109,33 +114,37 @@ void gpio_mode_setup(u32 gpioport, u8 mode, u8 pull_up_down, u16 gpios) GPIO_PUPDR(gpioport) = pupd; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Set GPIO Output Options -When the pin is set to output mode, this sets the configuration (analog/digital and -open drain/push pull) and speed, for a set of GPIO pins on a given GPIO port. +When the pin is set to output mode, this sets the configuration (analog/digital +and open drain/push pull) and speed, for a set of GPIO pins on a given GPIO +port. @param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id @param[in] otype Unsigned int8. Pin output type @ref gpio_output_type @param[in] speed Unsigned int8. Pin speed @ref gpio_speed @param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id - If multiple pins are to be set, use bitwise OR '|' to separate them. + If multiple pins are to be set, use bitwise OR '|' to separate + them. */ void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios) { u16 i; u32 ospeedr; - if (otype == 0x1) + if (otype == 0x1) { GPIO_OTYPER(gpioport) |= gpios; + } else GPIO_OTYPER(gpioport) &= ~gpios; ospeedr = GPIO_OSPEEDR(gpioport); for (i = 0; i < 16; i++) { - if (!((1 << i) & gpios)) + if (!((1 << i) & gpios)) { continue; + } ospeedr &= ~GPIO_OSPEED_MASK(i); ospeedr |= GPIO_OSPEED(i, speed); } @@ -143,22 +152,26 @@ void gpio_set_output_options(u32 gpioport, u8 otype, u8 speed, u16 gpios) GPIO_OSPEEDR(gpioport) = ospeedr; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Set GPIO Alternate Function Selection -Set the alternate function mapping number for each pin. Most pins have alternate -functions associated with them. When set to AF mode, a pin may be used for one of -its allocated alternate functions selected by the number given here. To determine -the number to be used for the desired function refer to the individual datasheet -for the particular device. A table is given under the Pin Selection chapter. +Set the alternate function mapping number for each pin. Most pins have +alternate functions associated with them. When set to AF mode, a pin may be +used for one of its allocated alternate functions selected by the number given +here. To determine the number to be used for the desired function refer to the +individual datasheet for the particular device. A table is given under the Pin +Selection chapter. -Note that a number of pins may be set but only with a single AF number. In practice -this would rarely be useful as each pin is likely to require a different number. +Note that a number of pins may be set but only with a single AF number. In +practice this would rarely be useful as each pin is likely to require a +different number. @param[in] gpioport Unsigned int32. Port identifier @ref gpio_port_id -@param[in] alt_func_num Unsigned int8. Pin alternate function number @ref gpio_af_num +@param[in] alt_func_num Unsigned int8. Pin alternate function number @ref +gpio_af_num @param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id - If multiple pins are to be set, use bitwise OR '|' to separate them. + If multiple pins are to be set, use bitwise OR '|' to separate + them. */ void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios) { @@ -169,15 +182,17 @@ void gpio_set_af(u32 gpioport, u8 alt_func_num, u16 gpios) afrh = GPIO_AFRH(gpioport); for (i = 0; i < 8; i++) { - if (!((1 << i) & gpios)) + if (!((1 << i) & gpios)) { continue; + } afrl &= ~GPIO_AFR_MASK(i); afrl |= GPIO_AFR(i, alt_func_num); } for (i = 8; i < 16; i++) { - if (!((1 << i) & gpios)) + if (!((1 << i) & gpios)) { continue; + } afrh &= ~GPIO_AFR_MASK(i - 8); afrh |= GPIO_AFR(i - 8, alt_func_num); } diff --git a/lib/stm32/common/hash_common_f24.c b/lib/stm32/common/hash_common_f24.c index d77a28ab..40f1b718 100644 --- a/lib/stm32/common/hash_common_f24.c +++ b/lib/stm32/common/hash_common_f24.c @@ -1,6 +1,7 @@ /** @addtogroup hash_file -@author @htmlonly © @endhtmlonly 2013 Mikhail Avkhimenia +@author @htmlonly © @endhtmlonly 2013 +Mikhail Avkhimenia This library supports the HASH processor in the STM32F2 and STM32F4 series of ARM Cortex Microcontrollers by ST Microelectronics. @@ -31,7 +32,7 @@ LGPL License Terms @ref lgpl_license #include -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief HASH Set Mode Sets up the specified mode - either HASH or HMAC. @@ -45,7 +46,7 @@ void hash_set_mode(u8 mode) HASH_CR |= mode; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief HASH Set Algorithm Sets up the specified algorithm - either MD5 or SHA1. @@ -59,7 +60,7 @@ void hash_set_algorithm(u8 algorithm) HASH_CR |= algorithm; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief HASH Set Data Type Sets up the specified data type: 32Bit, 16Bit, 8Bit, Bitstring. @@ -70,10 +71,10 @@ Sets up the specified data type: 32Bit, 16Bit, 8Bit, Bitstring. void hash_set_data_type(u8 datatype) { HASH_CR &= ~HASH_CR_DATATYPE; - HASH_CR |= datatype; + HASH_CR |= datatype; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief HASH Set Key Length Sets up the specified key length: Long, Short. @@ -84,10 +85,10 @@ Sets up the specified key length: Long, Short. void hash_set_key_length(u8 keylength) { HASH_CR &= ~HASH_CR_LKEY; - HASH_CR |= keylength; + HASH_CR |= keylength; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief HASH Set Last Word Valid Bits Specifies the number of valid bits in the last word. @@ -101,7 +102,7 @@ void hash_set_last_word_valid_bits(u8 validbits) HASH_STR |= 32 - validbits; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief HASH Init Initializes the HASH processor. @@ -113,7 +114,7 @@ void hash_init() HASH_CR |= HASH_CR_INIT; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief HASH Add data Puts data into the HASH processor's queue. @@ -126,7 +127,7 @@ void hash_add_data(u32 data) HASH_DIN = data; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief HASH Digest Starts the processing of the last data block. @@ -138,7 +139,7 @@ void hash_digest() HASH_STR |= HASH_STR_DCAL; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief HASH Get Hash Result Makes a copy of the resulting hash. @@ -154,6 +155,7 @@ void hash_get_result(u32 *data) data[2] = HASH_HR[2]; data[3] = HASH_HR[3]; - if ((HASH_CR & HASH_CR_ALGO) == HASH_ALGO_SHA1) + if ((HASH_CR & HASH_CR_ALGO) == HASH_ALGO_SHA1) { data[4] = HASH_HR[4]; + } } diff --git a/lib/stm32/common/i2c_common_all.c b/lib/stm32/common/i2c_common_all.c index 337fe9d1..3d20d3bb 100644 --- a/lib/stm32/common/i2c_common_all.c +++ b/lib/stm32/common/i2c_common_all.c @@ -1,7 +1,9 @@ /** @addtogroup i2c_file -@author @htmlonly © @endhtmlonly 2010 Thomas Otto -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies +@author @htmlonly © @endhtmlonly 2010 +Thomas Otto +@author @htmlonly © @endhtmlonly 2012 +Ken Sarkies Devices can have up to two I2C peripherals. The peripherals support SMBus and PMBus variants. @@ -38,11 +40,11 @@ register access, Error conditions /**@{*/ -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C Reset. -The I2C peripheral and all its associated configuration registers are placed in the -reset condition. The reset is effected via the RCC peripheral reset system. +The I2C peripheral and all its associated configuration registers are placed in +the reset condition. The reset is effected via the RCC peripheral reset system. @param[in] i2c Unsigned int32. I2C peripheral identifier @ref i2c_reg_base. */ @@ -61,7 +63,7 @@ void i2c_reset(u32 i2c) } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C Peripheral Enable. @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. @@ -72,7 +74,7 @@ void i2c_peripheral_enable(u32 i2c) I2C_CR1(i2c) |= I2C_CR1_PE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C Peripheral Disable. This must not be reset while in Master mode until a communication has finished. @@ -86,7 +88,7 @@ void i2c_peripheral_disable(u32 i2c) I2C_CR1(i2c) &= ~I2C_CR1_PE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C Send Start Condition. If in Master mode this will cause a restart condition to occur at the end of the @@ -101,7 +103,7 @@ void i2c_send_start(u32 i2c) I2C_CR1(i2c) |= I2C_CR1_START; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C Send Stop Condition. After the current byte transfer this will initiate a stop condition if in Master @@ -115,7 +117,7 @@ void i2c_send_stop(u32 i2c) I2C_CR1(i2c) |= I2C_CR1_STOP; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C Clear Stop Flag. Clear the "Send Stop" flag in the I2C config register @@ -127,7 +129,7 @@ void i2c_clear_stop(u32 i2c) I2C_CR1(i2c) &= ~I2C_CR1_STOP; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C Set the 7 bit Slave Address for the Peripheral. This sets an address for Slave mode operation, in 7 bit form. @@ -143,7 +145,7 @@ void i2c_set_own_7bit_slave_address(u32 i2c, u8 slave) I2C_OAR1(i2c) |= (1 << 14); /* Datasheet: always keep 1 by software. */ } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C Set the 10 bit Slave Address for the Peripheral. This sets an address for Slave mode operation, in 10 bit form. @@ -159,7 +161,7 @@ void i2c_set_own_10bit_slave_address(u32 i2c, u16 slave) I2C_OAR1(i2c) = (u16)(I2C_OAR1_ADDMODE | slave); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C Set Fast Mode. Set the clock frequency to the high clock rate mode (up to 400kHz). The actual @@ -173,11 +175,11 @@ void i2c_set_fast_mode(u32 i2c) I2C_CCR(i2c) |= I2C_CCR_FS; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C Set Standard Mode. -Set the clock frequency to the standard clock rate mode (up to 100kHz). The actual -clock frequency must be set with @ref i2c_set_clock_frequency +Set the clock frequency to the standard clock rate mode (up to 100kHz). The +actual clock frequency must be set with @ref i2c_set_clock_frequency @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. */ @@ -187,12 +189,13 @@ void i2c_set_standard_mode(u32 i2c) I2C_CCR(i2c) &= ~I2C_CCR_FS; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C Set Peripheral Clock Frequency. -Set the peripheral clock frequency: 2MHz to 36MHz (the APB frequency). Note that -this is not the I2C bus clock. This is set in conjunction with the Clock -Control register to generate the Master bus clock, see @ref i2c_set_ccr +Set the peripheral clock frequency: 2MHz to 36MHz (the APB frequency). Note +that this is not the I2C bus clock. This is set in conjunction with +the Clock Control register to generate the Master bus clock, see @ref +i2c_set_ccr @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. @param[in] freq Unsigned int8. Clock Frequency Setting @ref i2c_clock. @@ -206,7 +209,7 @@ void i2c_set_clock_frequency(u32 i2c, u8 freq) I2C_CR2(i2c) = reg16; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C Set Bus Clock Frequency. Set the bus clock frequency. This is a 12 bit number (0...4095) calculated @@ -229,7 +232,7 @@ void i2c_set_ccr(u32 i2c, u16 freq) I2C_CCR(i2c) = reg16; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C Set the Rise Time. Set the maximum rise time on the bus according to the I2C specification, as 1 @@ -247,12 +250,13 @@ void i2c_set_trise(u32 i2c, u16 trise) I2C_TRISE(i2c) = trise; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C Send the 7-bit Slave Address. @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. @param[in] slave Unsigned int16. Slave address 0...1023. -@param[in] readwrite Unsigned int8. Single bit to instruct slave to receive or send @ref i2c_rw. +@param[in] readwrite Unsigned int8. Single bit to instruct slave to receive or +send @ref i2c_rw. */ void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite) @@ -260,7 +264,7 @@ void i2c_send_7bit_address(u32 i2c, u8 slave, u8 readwrite) I2C_DR(i2c) = (u8)((slave << 1) | readwrite); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C Send Data. @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. @@ -272,7 +276,7 @@ void i2c_send_data(u32 i2c, u8 data) I2C_DR(i2c) = data; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C Get Data. @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. @@ -282,7 +286,7 @@ uint8_t i2c_get_data(u32 i2c) return I2C_DR(i2c) & 0xff; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C Enable Interrupt @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. @@ -293,7 +297,7 @@ void i2c_enable_interrupt(u32 i2c, u32 interrupt) I2C_CR2(i2c) |= interrupt; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C Disable Interrupt @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. @@ -304,7 +308,7 @@ void i2c_disable_interrupt(u32 i2c, u32 interrupt) I2C_CR2(i2c) &= ~interrupt; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C Enable ACK Enables acking of own 7/10 bit address @@ -315,7 +319,7 @@ void i2c_enable_ack(u32 i2c) I2C_CR1(i2c) |= I2C_CR1_ACK; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C Disable ACK Disables acking of own 7/10 bit address @@ -326,7 +330,7 @@ void i2c_disable_ack(u32 i2c) I2C_CR1(i2c) &= ~I2C_CR1_ACK; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C NACK Next Byte Causes the I2C controller to NACK the reception of the next byte @@ -337,7 +341,7 @@ void i2c_nack_next(u32 i2c) I2C_CR1(i2c) |= I2C_CR1_POS; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C NACK Next Byte Causes the I2C controller to NACK the reception of the current byte @@ -349,7 +353,7 @@ void i2c_nack_current(u32 i2c) I2C_CR1(i2c) &= ~I2C_CR1_POS; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C Set clock duty cycle @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. @@ -357,13 +361,14 @@ void i2c_nack_current(u32 i2c) */ void i2c_set_dutycycle(u32 i2c, u32 dutycycle) { - if (dutycycle == I2C_CCR_DUTY_DIV2) + if (dutycycle == I2C_CCR_DUTY_DIV2) { I2C_CCR(i2c) &= ~I2C_CCR_DUTY; - else + } else { I2C_CCR(i2c) |= I2C_CCR_DUTY; + } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C Enable DMA @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. @@ -373,7 +378,7 @@ void i2c_enable_dma(u32 i2c) I2C_CR2(i2c) |= I2C_CR2_DMAEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C Disable DMA @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. @@ -383,7 +388,7 @@ void i2c_disable_dma(u32 i2c) I2C_CR2(i2c) &= ~I2C_CR2_DMAEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C Set DMA last transfer @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. @@ -393,7 +398,7 @@ void i2c_set_dma_last_transfer(u32 i2c) I2C_CR2(i2c) |= I2C_CR2_LAST; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief I2C Clear DMA last transfer @param[in] i2c Unsigned int32. I2C register base address @ref i2c_reg_base. diff --git a/lib/stm32/common/iwdg_common_all.c b/lib/stm32/common/iwdg_common_all.c index 792adfe4..acf455c2 100644 --- a/lib/stm32/common/iwdg_common_all.c +++ b/lib/stm32/common/iwdg_common_all.c @@ -42,7 +42,7 @@ relevant bit is not set, the IWDG timer must be enabled by software. #define COUNT_LENGTH 12 #define COUNT_MASK ((1 << COUNT_LENGTH)-1) -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief IWDG Enable Watchdog Timer The watchdog timer is started. The timeout period defaults to 512 milliseconds @@ -55,7 +55,7 @@ void iwdg_start(void) IWDG_KR = IWDG_KR_START; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief IWDG Set Period in Milliseconds The countdown period is converted into count and prescale values. The maximum @@ -66,27 +66,41 @@ A delay of up to 5 clock cycles of the LSI clock (about 156 microseconds) can occasionally occur if the prescale or preload registers are currently busy loading a previous value. -@param[in] period u32 Period in milliseconds (< 32760) from a watchdog reset until -a system reset is issued. +@param[in] period u32 Period in milliseconds (< 32760) from a watchdog reset +until a system reset is issued. */ void iwdg_set_period_ms(u32 period) { -u32 count, prescale, reload, exponent; -/* Set the count to represent ticks of the 32kHz LSI clock */ + u32 count, prescale, reload, exponent; + + /* Set the count to represent ticks of the 32kHz LSI clock */ count = (period << 5); -/* Strip off the first 12 bits to get the prescale value required */ + + /* Strip off the first 12 bits to get the prescale value required */ prescale = (count >> 12); - if (prescale > 256) {exponent = IWDG_PR_DIV256; reload = COUNT_MASK;} - else if (prescale > 128) {exponent = IWDG_PR_DIV256; reload = (count >> 8);} - else if (prescale > 64) {exponent = IWDG_PR_DIV128; reload = (count >> 7);} - else if (prescale > 32) {exponent = IWDG_PR_DIV64; reload = (count >> 6);} - else if (prescale > 16) {exponent = IWDG_PR_DIV32; reload = (count >> 5);} - else if (prescale > 8) {exponent = IWDG_PR_DIV16; reload = (count >> 4);} - else if (prescale > 4) {exponent = IWDG_PR_DIV8; reload = (count >> 3);} - else {exponent = IWDG_PR_DIV4; reload = (count >> 2);} -/* Avoid the undefined situation of a zero count */ - if (count == 0) count = 1; + if (prescale > 256) { + exponent = IWDG_PR_DIV256; reload = COUNT_MASK; + } else if (prescale > 128) { + exponent = IWDG_PR_DIV256; reload = (count >> 8); + } else if (prescale > 64) { + exponent = IWDG_PR_DIV128; reload = (count >> 7); + } else if (prescale > 32) { + exponent = IWDG_PR_DIV64; reload = (count >> 6); + } else if (prescale > 16) { + exponent = IWDG_PR_DIV32; reload = (count >> 5); + } else if (prescale > 8) { + exponent = IWDG_PR_DIV16; reload = (count >> 4); + } else if (prescale > 4) { + exponent = IWDG_PR_DIV8; reload = (count >> 3); + } else { + exponent = IWDG_PR_DIV4; reload = (count >> 2); + } + + /* Avoid the undefined situation of a zero count */ + if (count == 0) { + count = 1; + } while (iwdg_prescaler_busy()); IWDG_KR = IWDG_KR_UNLOCK; @@ -96,31 +110,31 @@ u32 count, prescale, reload, exponent; IWDG_RLR = (reload & COUNT_MASK); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief IWDG Get Reload Register Status -@returns boolean: TRUE if the reload register is busy and unavailable for loading -a new count value. +@returns boolean: TRUE if the reload register is busy and unavailable for +loading a new count value. */ bool iwdg_reload_busy(void) { - return (IWDG_SR & IWDG_SR_RVU); + return IWDG_SR & IWDG_SR_RVU; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief IWDG Get Prescaler Register Status -@returns boolean: TRUE if the prescaler register is busy and unavailable for loading -a new period value. +@returns boolean: TRUE if the prescaler register is busy and unavailable for +loading a new period value. */ bool iwdg_prescaler_busy(void) { - return (IWDG_SR & IWDG_SR_PVU); + return IWDG_SR & IWDG_SR_PVU; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief IWDG reset Watchdog Timer The watchdog timer is reset. The counter restarts from the value in the reload diff --git a/lib/stm32/common/pwr_common_all.c b/lib/stm32/common/pwr_common_all.c index a4556648..2e29ed61 100644 --- a/lib/stm32/common/pwr_common_all.c +++ b/lib/stm32/common/pwr_common_all.c @@ -1,6 +1,7 @@ /** @addtogroup pwr-file PWR -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies +@author @htmlonly © @endhtmlonly 2012 +Ken Sarkies */ /* @@ -199,7 +200,7 @@ cleared by software (see @ref pwr_clear_wakeup_flag). bool pwr_get_wakeup_flag(void) { - return (PWR_CSR & PWR_CSR_WUF); + return PWR_CSR & PWR_CSR_WUF; } /**@}*/ diff --git a/lib/stm32/common/rtc_common_bcd.c b/lib/stm32/common/rtc_common_bcd.c index ff61a481..cfd8407a 100644 --- a/lib/stm32/common/rtc_common_bcd.c +++ b/lib/stm32/common/rtc_common_bcd.c @@ -33,7 +33,8 @@ This sets the RTC synchronous and asynchronous prescalars. */ -void rtc_set_prescaler(u32 sync, u32 async) { +void rtc_set_prescaler(u32 sync, u32 async) +{ /* * Even if only one of the two fields needs to be changed, * 2 separate write accesses must be performed to the RTC_PRER register. @@ -48,16 +49,16 @@ void rtc_set_prescaler(u32 sync, u32 async) { Time and Date are accessed through shadow registers which must be synchronized */ -void rtc_wait_for_synchro(void) { +void rtc_wait_for_synchro(void) +{ /* Unlock RTC registers */ RTC_WPR = 0xca; RTC_WPR = 0x53; RTC_ISR &= ~(RTC_ISR_RSF); - while (!(RTC_ISR & RTC_ISR_RSF)) { - ; - } + while (!(RTC_ISR & RTC_ISR_RSF)); + /* disable write protection again */ RTC_WPR = 0xff; } @@ -66,7 +67,8 @@ void rtc_wait_for_synchro(void) { /** @brief Unlock write access to the RTC registers */ -void rtc_unlock(void) { +void rtc_unlock(void) +{ RTC_WPR = 0xca; RTC_WPR = 0x53; } @@ -75,7 +77,8 @@ void rtc_unlock(void) { /** @brief Lock write access to the RTC registers */ -void rtc_lock(void) { +void rtc_lock(void) +{ RTC_WPR = 0xff; } @@ -83,31 +86,38 @@ void rtc_lock(void) { /** @brief Sets the wakeup time auto-reload value */ -void rtc_set_wakeup_time(u16 wkup_time, u8 rtc_cr_wucksel) { -// FTFM: -// The following sequence is required to configure or change the wakeup timer -// auto-reload value (WUT[15:0] in RTC_WUTR): -// 1. Clear WUTE in RTC_CR to disable the wakeup timer. - RTC_CR &= ~RTC_CR_WUTE; -// 2. Poll WUTWF until it is set in RTC_ISR to make sure the access to wakeup -// auto-reload counter and to WUCKSEL[2:0] bits is allowed. It takes around 2 -// RTCCLK clock cycles (due to clock synchronization). - while (!((RTC_ISR) & (RTC_ISR_WUTWF))) { } -// 3. Program the wakeup auto-reload value WUT[15:0], and the wakeup clock -// selection (WUCKSEL[2:0] bits in RTC_CR).Set WUTE in RTC_CR to enable the -// timer again. The wakeup timer restarts down-counting. - RTC_WUTR = wkup_time; - RTC_CR |= (rtc_cr_wucksel << RTC_CR_WUCLKSEL_SHIFT); - RTC_CR |= RTC_CR_WUTE; +void rtc_set_wakeup_time(u16 wkup_time, u8 rtc_cr_wucksel) +{ + /* FTFM: + * The following sequence is required to configure or change the wakeup + * timer auto-reload value (WUT[15:0] in RTC_WUTR): + * 1. Clear WUTE in RTC_CR to disable the wakeup timer. + */ + RTC_CR &= ~RTC_CR_WUTE; + /* 2. Poll WUTWF until it is set in RTC_ISR to make sure the access to + * wakeup auto-reload counter and to WUCKSEL[2:0] bits is allowed. + * It takes around 2 RTCCLK clock cycles (due to clock + * synchronization). + */ + while (!((RTC_ISR) & (RTC_ISR_WUTWF))); + /* 3. Program the wakeup auto-reload value WUT[15:0], and the wakeup + * clock selection (WUCKSEL[2:0] bits in RTC_CR).Set WUTE in RTC_CR + * to enable the timer again. The wakeup timer restarts + * down-counting. + */ + RTC_WUTR = wkup_time; + RTC_CR |= (rtc_cr_wucksel << RTC_CR_WUCLKSEL_SHIFT); + RTC_CR |= RTC_CR_WUTE; } /*---------------------------------------------------------------------------*/ /** @brief Clears the wakeup flag - @details This function should be called first in the rtc_wkup_isr() +@details This function should be called first in the rtc_wkup_isr() */ -void rtc_clear_wakeup_flag(void) { - RTC_ISR &= ~RTC_ISR_WUTF; +void rtc_clear_wakeup_flag(void) +{ + RTC_ISR &= ~RTC_ISR_WUTF; } /**@}*/ diff --git a/lib/stm32/common/spi_common_all.c b/lib/stm32/common/spi_common_all.c index 2431d443..40fcd959 100644 --- a/lib/stm32/common/spi_common_all.c +++ b/lib/stm32/common/spi_common_all.c @@ -1,7 +1,9 @@ /** @addtogroup spi_file -@author @htmlonly © @endhtmlonly 2009 Uwe Hermann -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies +@author @htmlonly © @endhtmlonly 2009 +Uwe Hermann +@author @htmlonly © @endhtmlonly 2012 +Ken Sarkies Devices can have up to three SPI peripherals. The common 4-wire full-duplex mode of operation is supported, along with 3-wire variants using unidirectional @@ -18,8 +20,8 @@ Example: 1Mbps, positive clock polarity, leading edge trigger, 8-bit words, LSB first. @code spi_init_master(SPI1, 1000000, SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE, - SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, - SPI_CR1_LSBFIRST); + SPI_CR1_CPHA_CLK_TRANSITION_1, SPI_CR1_DFF_8BIT, + SPI_CR1_LSBFIRST); spi_write(SPI1, 0x55); // 8-bit write spi_write(SPI1, 0xaa88); // 16-bit write reg8 = spi_read(SPI1); // 8-bit read @@ -67,13 +69,14 @@ LSB first. /**@{*/ -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Reset. -The SPI peripheral and all its associated configuration registers are placed in the -reset condition. The reset is effected via the RCC peripheral reset system. +The SPI peripheral and all its associated configuration registers are placed in +the reset condition. The reset is effected via the RCC peripheral reset system. -@param[in] spi_peripheral Unsigned int32. SPI peripheral identifier @ref spi_reg_base. +@param[in] spi_peripheral Unsigned int32. SPI peripheral identifier @ref +spi_reg_base. */ void spi_reset(u32 spi_peripheral) @@ -96,7 +99,7 @@ void spi_reset(u32 spi_peripheral) } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Configure the SPI as Master. The SPI peripheral is configured as a master with communication parameters @@ -111,7 +114,8 @@ These must be controlled separately. @param[in] cpol Unsigned int32. Clock polarity @ref spi_cpol. @param[in] cpha Unsigned int32. Clock Phase @ref spi_cpha. @param[in] dff Unsigned int32. Data frame format 8/16 bits @ref spi_dff. -@param[in] lsbfirst Unsigned int32. Frame format lsb/msb first @ref spi_lsbfirst. +@param[in] lsbfirst Unsigned int32. Frame format lsb/msb first @ref +spi_lsbfirst. @returns int. Error code. */ @@ -138,7 +142,7 @@ int spi_init_master(u32 spi, u32 br, u32 cpol, u32 cpha, u32 dff, u32 lsbfirst) } /* TODO: Error handling? */ -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Enable. The SPI peripheral is enabled. @@ -154,7 +158,7 @@ void spi_enable(u32 spi) } /* TODO: Error handling? */ -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Disable. The SPI peripheral is disabled. @@ -171,7 +175,7 @@ void spi_disable(u32 spi) SPI_CR1(spi) = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Clean Disable. Disable the SPI peripheral according to the procedure in section 23.3.8 of the @@ -185,25 +189,22 @@ prevents the BSY flag from becoming unreliable. u16 spi_clean_disable(u32 spi) { /* Wait to receive last data */ - while (!(SPI_SR(spi) & SPI_SR_RXNE)) - ; + while (!(SPI_SR(spi) & SPI_SR_RXNE)); u16 data = SPI_DR(spi); /* Wait to transmit last data */ - while (!(SPI_SR(spi) & SPI_SR_TXE)) - ; + while (!(SPI_SR(spi) & SPI_SR_TXE)); /* Wait until not busy */ - while (SPI_SR(spi) & SPI_SR_BSY) - ; + while (SPI_SR(spi) & SPI_SR_BSY); SPI_CR1(spi) &= ~SPI_CR1_SPE; return data; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Data Write. Data is written to the SPI interface. @@ -218,10 +219,11 @@ void spi_write(u32 spi, u16 data) SPI_DR(spi) = data; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Data Write with Blocking. -Data is written to the SPI interface after the previous write transfer has finished. +Data is written to the SPI interface after the previous write transfer has +finished. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @param[in] data Unsigned int16. 8 or 16 bit data to be written. @@ -230,14 +232,13 @@ Data is written to the SPI interface after the previous write transfer has finis void spi_send(u32 spi, u16 data) { /* Wait for transfer finished. */ - while (!(SPI_SR(spi) & SPI_SR_TXE)) - ; + while (!(SPI_SR(spi) & SPI_SR_TXE)); /* Write data (8 or 16 bits, depending on DFF) into DR. */ SPI_DR(spi) = data; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Data Read. Data is read from the SPI interface after the incoming transfer has finished. @@ -249,18 +250,17 @@ Data is read from the SPI interface after the incoming transfer has finished. u16 spi_read(u32 spi) { /* Wait for transfer finished. */ - while (!(SPI_SR(spi) & SPI_SR_RXNE)) - ; + while (!(SPI_SR(spi) & SPI_SR_RXNE)); /* Read the data (8 or 16 bits, depending on DFF bit) from DR. */ return SPI_DR(spi); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Data Write and Read Exchange. -Data is written to the SPI interface, then a read is done after the incoming transfer -has finished. +Data is written to the SPI interface, then a read is done after the incoming +transfer has finished. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @param[in] data Unsigned int16. 8 or 16 bit data to be written. @@ -272,14 +272,13 @@ u16 spi_xfer(u32 spi, u16 data) spi_write(spi, data); /* Wait for transfer finished. */ - while (!(SPI_SR(spi) & SPI_SR_RXNE)) - ; + while (!(SPI_SR(spi) & SPI_SR_RXNE)); /* Read the data (8 or 16 bits, depending on DFF bit) from DR. */ return SPI_DR(spi); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Set Bidirectional Simplex Mode. The SPI peripheral is set for bidirectional transfers in two-wire simplex mode @@ -293,12 +292,12 @@ void spi_set_bidirectional_mode(u32 spi) SPI_CR1(spi) |= SPI_CR1_BIDIMODE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Set Unidirectional Mode. -The SPI peripheral is set for unidirectional transfers. This is used in full duplex -mode or when the SPI is placed in two-wire simplex mode that uses a clock wire and a -unidirectional data wire. +The SPI peripheral is set for unidirectional transfers. This is used in full +duplex mode or when the SPI is placed in two-wire simplex mode that uses a +clock wire and a unidirectional data wire. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ @@ -308,11 +307,12 @@ void spi_set_unidirectional_mode(u32 spi) SPI_CR1(spi) &= ~SPI_CR1_BIDIMODE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Set Bidirectional Simplex Receive Only Mode. The SPI peripheral is set for bidirectional transfers in two-wire simplex mode -(using a clock wire and a bidirectional data wire), and is placed in a receive state. +(using a clock wire and a bidirectional data wire), and is placed in a receive +state. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ @@ -323,11 +323,12 @@ void spi_set_bidirectional_receive_only_mode(u32 spi) SPI_CR1(spi) &= ~SPI_CR1_BIDIOE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Set Bidirectional Simplex Receive Only Mode. The SPI peripheral is set for bidirectional transfers in two-wire simplex mode -(using a clock wire and a bidirectional data wire), and is placed in a transmit state. +(using a clock wire and a bidirectional data wire), and is placed in a transmit +state. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ @@ -338,7 +339,7 @@ void spi_set_bidirectional_transmit_only_mode(u32 spi) SPI_CR1(spi) |= SPI_CR1_BIDIOE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Enable the CRC. The SPI peripheral is set to use a CRC field for transmit and receive. @@ -351,7 +352,7 @@ void spi_enable_crc(u32 spi) SPI_CR1(spi) |= SPI_CR1_CRCEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Disable the CRC. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @@ -362,7 +363,7 @@ void spi_disable_crc(u32 spi) SPI_CR1(spi) &= ~SPI_CR1_CRCEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Next Transmit is a Data Word The next transmission to take place is a data word from the transmit buffer. @@ -377,7 +378,7 @@ void spi_set_next_tx_from_buffer(u32 spi) SPI_CR1(spi) &= ~SPI_CR1_CRCNEXT; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Next Transmit is a CRC Word The next transmission to take place is a crc word from the hardware crc unit. @@ -392,7 +393,7 @@ void spi_set_next_tx_from_crc(u32 spi) SPI_CR1(spi) |= SPI_CR1_CRCNEXT; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Set Data Frame Format to 8 bits @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @@ -403,7 +404,7 @@ void spi_set_dff_8bit(u32 spi) SPI_CR1(spi) &= ~SPI_CR1_DFF; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Set Data Frame Format to 16 bits @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @@ -414,7 +415,7 @@ void spi_set_dff_16bit(u32 spi) SPI_CR1(spi) |= SPI_CR1_DFF; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Set Full Duplex (3-wire) Mode @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @@ -425,8 +426,9 @@ void spi_set_full_duplex_mode(u32 spi) SPI_CR1(spi) &= ~SPI_CR1_RXONLY; } -/*-----------------------------------------------------------------------------*/ -/** @brief SPI Set Receive Only Mode for Simplex (2-wire) Unidirectional Transfers +/*---------------------------------------------------------------------------*/ +/** @brief SPI Set Receive Only Mode for Simplex (2-wire) Unidirectional +Transfers @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ @@ -436,7 +438,7 @@ void spi_set_receive_only_mode(u32 spi) SPI_CR1(spi) |= SPI_CR1_RXONLY; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Enable Slave Management by Hardware In slave mode the NSS hardware input is used as a select enable for the slave. @@ -449,7 +451,7 @@ void spi_disable_software_slave_management(u32 spi) SPI_CR1(spi) &= ~SPI_CR1_SSM; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Enable Slave Management by Software In slave mode the NSS hardware input is replaced by an internal software @@ -463,13 +465,14 @@ void spi_enable_software_slave_management(u32 spi) SPI_CR1(spi) |= SPI_CR1_SSM; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Set the Software NSS Signal High In slave mode, and only when software slave management is used, this replaces the NSS signal with a slave select enable signal. -@todo these should perhaps be combined with an SSM enable as it is meaningless otherwise +@todo these should perhaps be combined with an SSM enable as it is meaningless +otherwise @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ @@ -479,7 +482,7 @@ void spi_set_nss_high(u32 spi) SPI_CR1(spi) |= SPI_CR1_SSI; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Set the Software NSS Signal Low In slave mode, and only when software slave management is used, this replaces @@ -493,7 +496,7 @@ void spi_set_nss_low(u32 spi) SPI_CR1(spi) &= ~SPI_CR1_SSI; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Set to Send LSB First @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @@ -504,7 +507,7 @@ void spi_send_lsb_first(u32 spi) SPI_CR1(spi) |= SPI_CR1_LSBFIRST; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Set to Send MSB First @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @@ -515,10 +518,11 @@ void spi_send_msb_first(u32 spi) SPI_CR1(spi) &= ~SPI_CR1_LSBFIRST; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Set the Baudrate Prescaler -@todo Why is this specification different to the spi_init_master baudrate values? +@todo Why is this specification different to the spi_init_master baudrate +values? @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @param[in] baudrate Unsigned int8. Baudrate prescale value @ref spi_br_pre. @@ -528,15 +532,16 @@ void spi_set_baudrate_prescaler(u32 spi, u8 baudrate) { u32 reg32; - if (baudrate > 7) + if (baudrate > 7) { return; + } reg32 = (SPI_CR1(spi) & 0xffc7); /* Clear bits [5:3]. */ reg32 |= (baudrate << 3); SPI_CR1(spi) = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Set to Master Mode @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @@ -547,7 +552,7 @@ void spi_set_master_mode(u32 spi) SPI_CR1(spi) |= SPI_CR1_MSTR; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Set to Slave Mode @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @@ -558,7 +563,7 @@ void spi_set_slave_mode(u32 spi) SPI_CR1(spi) &= ~SPI_CR1_MSTR; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Set the Clock Polarity to High when Idle @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @@ -569,7 +574,7 @@ void spi_set_clock_polarity_1(u32 spi) SPI_CR1(spi) |= SPI_CR1_CPOL; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Set the Clock Polarity to Low when Idle @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @@ -580,7 +585,7 @@ void spi_set_clock_polarity_0(u32 spi) SPI_CR1(spi) &= ~SPI_CR1_CPOL; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Set the Clock Phase to Capture on Trailing Edge @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @@ -591,7 +596,7 @@ void spi_set_clock_phase_1(u32 spi) SPI_CR1(spi) |= SPI_CR1_CPHA; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Set the Clock Phase to Capture on Leading Edge @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @@ -602,7 +607,7 @@ void spi_set_clock_phase_0(u32 spi) SPI_CR1(spi) &= ~SPI_CR1_CPHA; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Enable the Transmit Buffer Empty Interrupt @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @@ -613,7 +618,7 @@ void spi_enable_tx_buffer_empty_interrupt(u32 spi) SPI_CR2(spi) |= SPI_CR2_TXEIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Disable the Transmit Buffer Empty Interrupt @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @@ -624,7 +629,7 @@ void spi_disable_tx_buffer_empty_interrupt(u32 spi) SPI_CR2(spi) &= ~SPI_CR2_TXEIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Enable the Receive Buffer Ready Interrupt @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @@ -635,7 +640,7 @@ void spi_enable_rx_buffer_not_empty_interrupt(u32 spi) SPI_CR2(spi) |= SPI_CR2_RXNEIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Disable the Receive Buffer Ready Interrupt @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @@ -646,7 +651,7 @@ void spi_disable_rx_buffer_not_empty_interrupt(u32 spi) SPI_CR2(spi) &= ~SPI_CR2_RXNEIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Enable the Error Interrupt @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @@ -657,7 +662,7 @@ void spi_enable_error_interrupt(u32 spi) SPI_CR2(spi) |= SPI_CR2_ERRIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Disable the Error Interrupt @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @@ -668,7 +673,7 @@ void spi_disable_error_interrupt(u32 spi) SPI_CR2(spi) &= ~SPI_CR2_ERRIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Set the NSS Pin as an Output Normally used in master mode to allows the master to place all devices on the @@ -682,7 +687,7 @@ void spi_enable_ss_output(u32 spi) SPI_CR2(spi) |= SPI_CR2_SSOE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Set the NSS Pin as an Input In master mode this allows the master to sense the presence of other masters. If @@ -697,7 +702,7 @@ void spi_disable_ss_output(u32 spi) SPI_CR2(spi) &= ~SPI_CR2_SSOE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Enable Transmit Transfers via DMA This allows transmissions to proceed unattended using DMA to move data to the @@ -712,7 +717,7 @@ void spi_enable_tx_dma(u32 spi) SPI_CR2(spi) |= SPI_CR2_TXDMAEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Disable Transmit Transfers via DMA @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. @@ -723,12 +728,12 @@ void spi_disable_tx_dma(u32 spi) SPI_CR2(spi) &= ~SPI_CR2_TXDMAEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Enable Receive Transfers via DMA -This allows received data streams to proceed unattended using DMA to move data from -the receive buffer as data becomes available. The DMA channels provided for each -SPI peripheral are given in the Technical Manual DMA section. +This allows received data streams to proceed unattended using DMA to move data +from the receive buffer as data becomes available. The DMA channels provided +for each SPI peripheral are given in the Technical Manual DMA section. @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. */ @@ -738,7 +743,7 @@ void spi_enable_rx_dma(u32 spi) SPI_CR2(spi) |= SPI_CR2_RXDMAEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief SPI Disable Receive Transfers via DMA @param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base. diff --git a/lib/stm32/common/timer_common_all.c b/lib/stm32/common/timer_common_all.c index a5bd5e53..1dd8da60 100644 --- a/lib/stm32/common/timer_common_all.c +++ b/lib/stm32/common/timer_common_all.c @@ -1,7 +1,9 @@ /** @addtogroup timer_file -@author @htmlonly © @endhtmlonly 2010 Edward Cheeseman -@author @htmlonly © @endhtmlonly 2011 Stephen Caudle +@author @htmlonly © @endhtmlonly 2010 +Edward Cheeseman +@author @htmlonly © @endhtmlonly 2011 +Stephen Caudle @section tim_common Notes for All Timers @@ -16,40 +18,44 @@ Some of the larger devices have additional general purpose timers (9-14). @section tim_api_ex Basic TIMER handling API. -Enable the timer clock first. The timer mode sets the clock division ratio, -the count alignment (edge or centred) and count direction. Finally enable the timer. +Enable the timer clock first. The timer mode sets the clock division ratio, the +count alignment (edge or centred) and count direction. Finally enable the +timer. The timer output compare block produces a signal that can be configured for -output to a pin or passed to other peripherals for use as a trigger. In all cases -the output compare mode must be set to define how the output responds to a compare -match, and the output must be enabled. If output to a pin is required, enable the -appropriate GPIO clock and set the pin to alternate output mode. +output to a pin or passed to other peripherals for use as a trigger. In all +cases the output compare mode must be set to define how the output responds to +a compare match, and the output must be enabled. If output to a pin is +required, enable the appropriate GPIO clock and set the pin to alternate output +mode. Example: Timer 2 with 2x clock divide, edge aligned and up counting. @code rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM2EN); timer_reset(TIM2); timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT_MUL_2, - TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); + TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); ... timer_set_period(TIM2, 1000); timer_enable_counter(TIM2); @endcode Example: Timer 1 with PWM output, no clock divide and centre alignment. Set the -Output Compare mode to PWM and enable the output of channel 1. Note that for the -advanced timers the break functionality must be enabled before the signal will -appear at the output, even though break is not being used. This is in addition to -the normal output enable. Enable the alternate function clock (APB2 only) and port A -clock. Set ports A8 and A9 (timer 1 channel 1 compare outputs) to alternate function -push-pull outputs where the PWM output will appear. +Output Compare mode to PWM and enable the output of channel 1. Note that for +the advanced timers the break functionality must be enabled before the signal +will appear at the output, even though break is not being used. This is in +addition to the normal output enable. Enable the alternate function clock (APB2 +only) and port A clock. Set ports A8 and A9 (timer 1 channel 1 compare outputs) +to alternate function push-pull outputs where the PWM output will appear. @code - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN | RCC_APB2ENR_AFIOEN); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_IOPAEN | + RCC_APB2ENR_AFIOEN); gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ, GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO8 | GPIO9); rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_TIM1EN); timer_reset(TIM1); - timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_CENTER_1, TIM_CR1_DIR_UP); + timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_CENTER_1, + TIM_CR1_DIR_UP); timer_set_oc_mode(TIM1, TIM_OC1, TIM_OCM_PWM2); timer_enable_oc_output(TIM1, TIM_OC1); timer_enable_break_main_output(TIM1); @@ -100,12 +106,11 @@ push-pull outputs where the PWM output will appear. /*---------------------------------------------------------------------------*/ /** @brief Reset a Timer. -The counter and all its associated configuration registers -are placed in the reset condition. The reset is effected via the RCC peripheral reset -system. +The counter and all its associated configuration registers are placed in the +reset condition. The reset is effected via the RCC peripheral reset system. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base - (TIM9 .. TIM14 not yet supported here). +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref + tim_reg_base (TIM9 .. TIM14 not yet supported here). */ void timer_reset(u32 timer_peripheral) @@ -157,23 +162,28 @@ void timer_reset(u32 timer_peripheral) break; case TIM10: rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM10RST); - rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM10RST); + rcc_peripheral_clear_reset(&RCC_APB2RSTR, + RCC_APB2RSTR_TIM10RST); break; case TIM11: rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM11RST); - rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM11RST); + rcc_peripheral_clear_reset(&RCC_APB2RSTR, + RCC_APB2RSTR_TIM11RST); break; case TIM12: rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM12RST); - rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM12RST); + rcc_peripheral_clear_reset(&RCC_APB1RSTR, + RCC_APB1RSTR_TIM12RST); break; case TIM13: rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM13RST); - rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM13RST); + rcc_peripheral_clear_reset(&RCC_APB1RSTR, + RCC_APB1RSTR_TIM13RST); break; case TIM14: rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM14RST); - rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM14RST); + rcc_peripheral_clear_reset(&RCC_APB1RSTR, + RCC_APB1RSTR_TIM14RST); break; */ } @@ -182,8 +192,10 @@ void timer_reset(u32 timer_peripheral) /*---------------------------------------------------------------------------*/ /** @brief Enable Interrupts for a Timer -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base -@param[in] irq Unsigned int32. @ref tim_irq_enable. Logical OR of all interrupt enable bits to be set +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base +@param[in] irq Unsigned int32. @ref tim_irq_enable. Logical OR of all interrupt +enable bits to be set */ void timer_enable_irq(u32 timer_peripheral, u32 irq) @@ -194,8 +206,10 @@ void timer_enable_irq(u32 timer_peripheral, u32 irq) /*---------------------------------------------------------------------------*/ /** @brief Disable Interrupts for a Timer. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base -@param[in] irq Unsigned int32. @ref tim_irq_enable. Logical OR of all interrupt enable bits to be cleared +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base +@param[in] irq Unsigned int32. @ref tim_irq_enable. Logical OR of all interrupt +enable bits to be cleared */ void timer_disable_irq(u32 timer_peripheral, u32 irq) @@ -206,13 +220,15 @@ void timer_disable_irq(u32 timer_peripheral, u32 irq) /*---------------------------------------------------------------------------*/ /** @brief Return Interrupt Source. -Returns true if the specified interrupt flag (UIF, TIF or CCxIF, with BIF or COMIF -for advanced timers) was set and the interrupt was enabled. If the specified flag -is not an interrupt flag, the function returns false. +Returns true if the specified interrupt flag (UIF, TIF or CCxIF, with BIF or +COMIF for advanced timers) was set and the interrupt was enabled. If the +specified flag is not an interrupt flag, the function returns false. -@todo Timers 6-7, 9-14 have fewer interrupts, but invalid flags are not caught here. +@todo Timers 6-7, 9-14 have fewer interrupts, but invalid flags are not caught +here. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base @param[in] flag Unsigned int32. Status register flag @ref tim_sr_values. @returns boolean: flag set. */ @@ -220,12 +236,16 @@ is not an interrupt flag, the function returns false. bool timer_interrupt_source(u32 timer_peripheral, u32 flag) { /* flag not set or interrupt disabled or not an interrupt source */ - if (((TIM_SR(timer_peripheral) & TIM_DIER(timer_peripheral) & flag) == 0) || - (flag > TIM_SR_BIF)) return false; + if (((TIM_SR(timer_peripheral) & + TIM_DIER(timer_peripheral) & flag) == 0) || + (flag > TIM_SR_BIF)) { + return false; + } /* Only an interrupt source for advanced timers */ #if (defined(TIM1_BASE) || defined(TIM8_BASE)) - if ((flag == TIM_SR_BIF) || (flag == TIM_SR_COMIF)) - return ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)); + if ((flag == TIM_SR_BIF) || (flag == TIM_SR_COMIF)) { + return (timer_peripheral == TIM1) || (timer_peripheral == TIM8); + } #endif return true; } @@ -233,7 +253,8 @@ bool timer_interrupt_source(u32 timer_peripheral, u32 flag) /*---------------------------------------------------------------------------*/ /** @brief Read a Status Flag. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base @param[in] flag Unsigned int32. Status register flag @ref tim_sr_values. @returns boolean: flag set. */ @@ -250,7 +271,8 @@ bool timer_get_flag(u32 timer_peripheral, u32 flag) /*---------------------------------------------------------------------------*/ /** @brief Clear a Status Flag. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base @param[in] flag Unsigned int32. @ref tim_sr_values. Status register flag. */ @@ -278,10 +300,13 @@ settings. hardware and cannot be written. The count direction setting has no effect in this case. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base (TIM1, TIM2 ... TIM5, TIM8) -@param[in] clock_div Unsigned int32. Clock Divider Ratio in bits 8,9: @ref tim_x_cr1_cdr +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base (TIM1, TIM2 ... TIM5, TIM8) +@param[in] clock_div Unsigned int32. Clock Divider Ratio in bits 8,9: @ref +tim_x_cr1_cdr @param[in] alignment Unsigned int32. Alignment bits in 5,6: @ref tim_x_cr1_cms -@param[in] direction Unsigned int32. Count direction in bit 4,: @ref tim_x_cr1_dir +@param[in] direction Unsigned int32. Count direction in bit 4,: @ref +tim_x_cr1_dir */ void timer_set_mode(u32 timer_peripheral, u32 clock_div, @@ -304,8 +329,10 @@ void timer_set_mode(u32 timer_peripheral, u32 clock_div, This forms the sampling clock for the input filters and the dead-time clock in the advanced timers 1 and 8, by division from the timer clock. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base -@param[in] clock_div Unsigned int32. Clock Divider Ratio in bits 8,9: @ref tim_x_cr1_cdr +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base +@param[in] clock_div Unsigned int32. Clock Divider Ratio in bits 8,9: @ref +tim_x_cr1_cdr */ void timer_set_clock_division(u32 timer_peripheral, u32 clock_div) @@ -321,7 +348,8 @@ void timer_set_clock_division(u32 timer_peripheral, u32 clock_div) During counter operation this causes the counter to be loaded from its auto-reload register only at the next update event. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base */ void timer_enable_preload(u32 timer_peripheral) @@ -336,7 +364,8 @@ This causes the counter to be loaded immediately with a new count value when the auto-reload register is written, so that the new value becomes effective for the current count cycle rather than for the cycle following an update event. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base */ void timer_disable_preload(u32 timer_peripheral) @@ -349,7 +378,8 @@ void timer_disable_preload(u32 timer_peripheral) The mode can be edge aligned or centered. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base @param[in] alignment Unsigned int32. Alignment bits in 5,6: @ref tim_x_cr1_cms */ @@ -365,7 +395,8 @@ void timer_set_alignment(u32 timer_peripheral, u32 alignment) This has no effect if the timer is set to center aligned. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base */ void timer_direction_up(u32 timer_peripheral) @@ -378,7 +409,8 @@ void timer_direction_up(u32 timer_peripheral) This has no effect if the timer is set to center aligned. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base */ void timer_direction_down(u32 timer_peripheral) @@ -389,7 +421,8 @@ void timer_direction_down(u32 timer_peripheral) /*---------------------------------------------------------------------------*/ /** @brief Enable the Timer for One Cycle and Stop. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base */ void timer_one_shot_mode(u32 timer_peripheral) @@ -400,7 +433,8 @@ void timer_one_shot_mode(u32 timer_peripheral) /*---------------------------------------------------------------------------*/ /** @brief Enable the Timer to Run Continuously. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base */ void timer_continuous_mode(u32 timer_peripheral) @@ -416,7 +450,8 @@ The events which will generate an interrupt or DMA request can be @li a forced update, @li an event from the slave mode controller. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base */ void timer_update_on_any(u32 timer_peripheral) @@ -425,9 +460,11 @@ void timer_update_on_any(u32 timer_peripheral) } /*---------------------------------------------------------------------------*/ -/** @brief Set the Timer to Generate Update IRQ or DMA only from Under/Overflow Events. +/** @brief Set the Timer to Generate Update IRQ or DMA only from Under/Overflow +Events. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base */ void timer_update_on_overflow(u32 timer_peripheral) @@ -438,7 +475,8 @@ void timer_update_on_overflow(u32 timer_peripheral) /*---------------------------------------------------------------------------*/ /** @brief Enable Timer Update Events. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base */ void timer_enable_update_event(u32 timer_peripheral) @@ -451,7 +489,8 @@ void timer_enable_update_event(u32 timer_peripheral) Update events are not generated and the shadow registers keep their values. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base */ void timer_disable_update_event(u32 timer_peripheral) @@ -464,7 +503,8 @@ void timer_disable_update_event(u32 timer_peripheral) This should be called after the timer initial configuration has been completed. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base */ void timer_enable_counter(u32 timer_peripheral) @@ -475,7 +515,8 @@ void timer_enable_counter(u32 timer_peripheral) /*---------------------------------------------------------------------------*/ /** @brief Stop the timer from counting. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base */ void timer_disable_counter(u32 timer_peripheral) @@ -492,16 +533,19 @@ This determines the value of the timer output compare when it enters idle state. @note This setting is only valid for the advanced timers. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base -@param[in] outputs Unsigned int32. Timer Output Idle State Controls @ref tim_x_cr2_ois. -If several settings are to be made, use the logical OR of the output control values. +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base +@param[in] outputs Unsigned int32. Timer Output Idle State Controls @ref +tim_x_cr2_ois. If several settings are to be made, use the logical OR of the +output control values. */ void timer_set_output_idle_state(u32 timer_peripheral, u32 outputs) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) - TIM_CR2(timer_peripheral) |= outputs & TIM_CR2_OIS_MASK; + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { + TIM_CR2(timer_peripheral) |= outputs & TIM_CR2_OIS_MASK; + } #else (void)timer_peripheral; (void)outputs; @@ -517,15 +561,18 @@ This determines the value of the timer output compare when it enters idle state. @note This setting is only valid for the advanced timers. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base -@param[in] outputs Unsigned int32. Timer Output Idle State Controls @ref tim_x_cr2_ois +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base +@param[in] outputs Unsigned int32. Timer Output Idle State Controls @ref +tim_x_cr2_ois */ void timer_reset_output_idle_state(u32 timer_peripheral, u32 outputs) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) - TIM_CR2(timer_peripheral) &= ~(outputs & TIM_CR2_OIS_MASK); + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { + TIM_CR2(timer_peripheral) &= ~(outputs & TIM_CR2_OIS_MASK); + } #else (void)timer_peripheral; (void)outputs; @@ -535,10 +582,11 @@ void timer_reset_output_idle_state(u32 timer_peripheral, u32 outputs) /*---------------------------------------------------------------------------*/ /** @brief Set Timer 1 Input to XOR of Three Channels. -The first timer capture input is formed from the XOR of the first three timer input -channels 1, 2, 3. +The first timer capture input is formed from the XOR of the first three timer +input channels 1, 2, 3. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base */ void timer_set_ti1_ch123_xor(u32 timer_peripheral) @@ -551,7 +599,8 @@ void timer_set_ti1_ch123_xor(u32 timer_peripheral) The first timer capture input is taken from the timer input channel 1 only. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base */ void timer_set_ti1_ch1(u32 timer_peripheral) @@ -562,10 +611,11 @@ void timer_set_ti1_ch1(u32 timer_peripheral) /*---------------------------------------------------------------------------*/ /** @brief Set the Master Mode -This sets the Trigger Output TRGO for synchronizing with slave timers or passing as -an internal trigger to the ADC or DAC. +This sets the Trigger Output TRGO for synchronizing with slave timers or +passing as an internal trigger to the ADC or DAC. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base @param[in] mode Unsigned int32. Master Mode @ref tim_mastermode */ @@ -580,7 +630,8 @@ void timer_set_master_mode(u32 timer_peripheral, u32 mode) Capture/compare events will cause DMA requests to be generated. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base */ void timer_set_dma_on_compare_event(u32 timer_peripheral) @@ -593,7 +644,8 @@ void timer_set_dma_on_compare_event(u32 timer_peripheral) Update events will cause DMA requests to be generated. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base */ void timer_set_dma_on_update_event(u32 timer_peripheral) @@ -608,17 +660,19 @@ If the capture/compare control bits CCxE, CCxNE and OCxM are set to be preloaded, they are updated by software generating the COMG event (@ref timer_generate_event) or when a rising edge occurs on the trigger input TRGI. -@note This setting is only valid for the advanced timer channels with complementary -outputs. +@note This setting is only valid for the advanced timer channels with +complementary outputs. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base */ void timer_enable_compare_control_update_on_trigger(u32 timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_CR2(timer_peripheral) |= TIM_CR2_CCUS; + } #else (void)timer_peripheral; #endif @@ -631,17 +685,19 @@ If the capture/compare control bits CCxE, CCxNE and OCxM are set to be preloaded, they are updated by software generating the COMG event (@ref timer_generate_event). -@note This setting is only valid for the advanced timer channels with complementary -outputs. +@note This setting is only valid for the advanced timer channels with +complementary outputs. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base */ void timer_disable_compare_control_update_on_trigger(u32 timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCUS; + } #else (void)timer_peripheral; #endif @@ -653,17 +709,19 @@ void timer_disable_compare_control_update_on_trigger(u32 timer_peripheral) The capture/compare control bits CCxE, CCxNE and OCxM are set to be preloaded when a COM event occurs. -@note This setting is only valid for the advanced timer channels with complementary -outputs. +@note This setting is only valid for the advanced timer channels with +complementary outputs. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base */ void timer_enable_preload_complementry_enable_bits(u32 timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_CR2(timer_peripheral) |= TIM_CR2_CCPC; + } #else (void)timer_peripheral; #endif @@ -674,17 +732,19 @@ void timer_enable_preload_complementry_enable_bits(u32 timer_peripheral) The capture/compare control bits CCxE, CCxNE and OCxM preload is disabled. -@note This setting is only valid for the advanced timer channels with complementary -outputs. +@note This setting is only valid for the advanced timer channels with +complementary outputs. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base */ void timer_disable_preload_complementry_enable_bits(u32 timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCPC; + } #else (void)timer_peripheral; #endif @@ -695,7 +755,8 @@ void timer_disable_preload_complementry_enable_bits(u32 timer_peripheral) The timer clock is prescaled by the 16 bit scale value plus 1. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base @param[in] value Unsigned int32. Prescaler values 0...0xFFFF. */ @@ -712,15 +773,17 @@ count cycles have been completed. @note This setting is only valid for the advanced timers. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base @param[in] value Unsigned int32. Repetition values 0...0xFF. */ void timer_set_repetition_counter(u32 timer_peripheral, u32 value) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_RCR(timer_peripheral) = value; + } #else (void)timer_peripheral; (void)value; @@ -732,7 +795,8 @@ void timer_set_repetition_counter(u32 timer_peripheral, u32 value) Specify the timer period in the auto-reload register. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base @param[in] period Unsigned int32. Period in counter clock ticks. */ @@ -744,12 +808,13 @@ void timer_set_period(u32 timer_peripheral, u32 period) /*---------------------------------------------------------------------------*/ /** @brief Timer Enable the Output Compare Clear Function -When this is enabled, the output compare signal is cleared when a high is detected -on the external trigger input. This works in the output compare and PWM modes only -(not forced mode). +When this is enabled, the output compare signal is cleared when a high is +detected on the external trigger input. This works in the output compare and +PWM modes only (not forced mode). The output compare signal remains off until the next update event. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base @param[in] oc_id enum ::tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken) */ @@ -772,7 +837,9 @@ void timer_enable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id) case TIM_OC1N: case TIM_OC2N: case TIM_OC3N: - /* Ignoring as oc clear enable only applies to the whole channel. */ + /* Ignoring as oc clear enable only applies to the whole + * channel. + */ break; } } @@ -780,7 +847,8 @@ void timer_enable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id) /*---------------------------------------------------------------------------*/ /** @brief Timer Disable the Output Compare Clear Function -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base @param[in] oc_id enum ::tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken) */ @@ -803,7 +871,9 @@ void timer_disable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id) case TIM_OC1N: case TIM_OC2N: case TIM_OC3N: - /* Ignoring as oc clear enable only applies to the whole channel. */ + /* Ignoring as oc clear enable only applies to the whole + * channel. + */ break; } } @@ -816,7 +886,8 @@ by a trigger input, independently of the compare match. This speeds up the setting of the output compare to 3 clock cycles as opposed to at least 5 in the slow mode. This works in the PWM1 and PWM2 modes only. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base @param[in] oc_id enum ::tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken) */ @@ -850,7 +921,8 @@ void timer_set_oc_fast_mode(u32 timer_peripheral, enum tim_oc_id oc_id) This disables the fast compare mode and the output compare depends on the counter and compare register values. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base @param[in] oc_id enum ::tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken) */ @@ -881,24 +953,28 @@ void timer_set_oc_slow_mode(u32 timer_peripheral, enum tim_oc_id oc_id) /*---------------------------------------------------------------------------*/ /** @brief Timer Set Output Compare Mode -Specifies how the comparator output will respond to a compare match. The mode can be: +Specifies how the comparator output will respond to a compare match. The mode +can be: @li Frozen - the output does not respond to a match. @li Active - the output assumes the active state on the first match. @li Inactive - the output assumes the inactive state on the first match. -@li Toggle - The output switches between active and inactive states on each match. +@li Toggle - The output switches between active and inactive states on each +match. @li Force inactive. The output is forced low regardless of the compare state. @li Force active. The output is forced high regardless of the compare state. -@li PWM1 - The output is active when the counter is less than the compare register contents -and inactive otherwise. -@li PWM2 - The output is inactive when the counter is less than the compare register contents -and active otherwise. +@li PWM1 - The output is active when the counter is less than the compare +register contents and inactive otherwise. +@li PWM2 - The output is inactive when the counter is less than the compare +register contents and active otherwise. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base @param[in] oc_id enum ::tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken) @param[in] oc_mode enum ::tim_oc_mode. OC mode designators. - TIM_OCM_FROZEN, TIM_OCM_ACTIVE, TIM_OCM_INACTIVE, TIM_OCM_TOGGLE, - TIM_OCM_FORCE_LOW, TIM_OCM_FORCE_HIGH, TIM_OCM_PWM1, TIM_OCM_PWM2 + TIM_OCM_FROZEN, TIM_OCM_ACTIVE, TIM_OCM_INACTIVE, + TIM_OCM_TOGGLE, TIM_OCM_FORCE_LOW, TIM_OCM_FORCE_HIGH, + TIM_OCM_PWM1, TIM_OCM_PWM2 */ void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id, @@ -1044,7 +1120,8 @@ void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id, /*---------------------------------------------------------------------------*/ /** @brief Timer Enable the Output Compare Preload Register -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base @param[in] oc_id enum ::tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken) */ @@ -1075,7 +1152,8 @@ void timer_enable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id) /*---------------------------------------------------------------------------*/ /** @brief Timer Disable the Output Compare Preload Register -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base @param[in] oc_id enum ::tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action) */ @@ -1108,9 +1186,11 @@ void timer_disable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id) The polarity of the channel output is set active high. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base @param[in] oc_id enum ::tim_oc_id OC channel designators - TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced timers 1 and 8) + TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced + timers 1 and 8) */ void timer_set_oc_polarity_high(u32 timer_peripheral, enum tim_oc_id oc_id) @@ -1137,8 +1217,9 @@ void timer_set_oc_polarity_high(u32 timer_peripheral, enum tim_oc_id oc_id) /* Acting for TIM1 and TIM8 only from here onwards. */ #if (defined(TIM1_BASE) || defined(TIM8_BASE)) - if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) + if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) { return; + } #else return; #endif @@ -1167,9 +1248,11 @@ void timer_set_oc_polarity_high(u32 timer_peripheral, enum tim_oc_id oc_id) The polarity of the channel output is set active low. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base @param[in] oc_id enum ::tim_oc_id OC channel designators - TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced timers 1 and 8) + TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced + timers 1 and 8) */ void timer_set_oc_polarity_low(u32 timer_peripheral, enum tim_oc_id oc_id) @@ -1196,8 +1279,9 @@ void timer_set_oc_polarity_low(u32 timer_peripheral, enum tim_oc_id oc_id) /* Acting for TIM1 and TIM8 only from here onwards. */ #if (defined(TIM1_BASE) || defined(TIM8_BASE)) - if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) + if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) { return; + } #else return; #endif @@ -1226,9 +1310,11 @@ void timer_set_oc_polarity_low(u32 timer_peripheral, enum tim_oc_id oc_id) The channel output compare functionality is enabled. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base @param[in] oc_id enum ::tim_oc_id OC channel designators - TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced timers 1 and 8) + TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced + timers 1 and 8) */ void timer_enable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id) @@ -1255,8 +1341,9 @@ void timer_enable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id) /* Acting for TIM1 and TIM8 only from here onwards. */ #if (defined(TIM1_BASE) || defined(TIM8_BASE)) - if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) + if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) { return; + } #else return; #endif @@ -1285,9 +1372,11 @@ void timer_enable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id) The channel output compare functionality is disabled. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base @param[in] oc_id enum ::tim_oc_id OC channel designators - TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced timers 1 and 8) + TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced + timers 1 and 8) */ void timer_disable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id) @@ -1314,8 +1403,9 @@ void timer_disable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id) /* Acting for TIM1 and TIM8 only from here onwards. */ #if (defined(TIM1_BASE) || defined(TIM8_BASE)) - if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) + if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) { return; + } #else return; #endif @@ -1347,17 +1437,20 @@ void timer_disable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id) @note This setting is only valid for the advanced timers. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base @param[in] oc_id enum ::tim_oc_id OC channel designators - TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced timers 1 and 8) + TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced + timers 1 and 8) */ void timer_set_oc_idle_state_set(u32 timer_peripheral, enum tim_oc_id oc_id) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) /* Acting for TIM1 and TIM8 only. */ - if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) + if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) { return; + } switch (oc_id) { case TIM_OC1: @@ -1396,17 +1489,20 @@ void timer_set_oc_idle_state_set(u32 timer_peripheral, enum tim_oc_id oc_id) @note This setting is only valid for the advanced timers. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref +tim_reg_base @param[in] oc_id enum ::tim_oc_id OC channel designators - TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced timers 1 and 8) + TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (only for advanced + timers 1 and 8) */ void timer_set_oc_idle_state_unset(u32 timer_peripheral, enum tim_oc_id oc_id) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) /* Acting for TIM1 and TIM8 only. */ - if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) + if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8)) { return; + } switch (oc_id) { case TIM_OC1: @@ -1443,8 +1539,8 @@ void timer_set_oc_idle_state_unset(u32 timer_peripheral, enum tim_oc_id oc_id) This is a convenience function to set the OC preload register value for loading to the compare register. -@param[in] timer_peripheral Unsigned int32. Timer register address base @ref tim_reg_base - (TIM9 .. TIM14 not yet supported here). +@param[in] timer_peripheral Unsigned int32. Timer register address base @ref + tim_reg_base (TIM9 .. TIM14 not yet supported here). @param[in] oc_id enum ::tim_oc_id OC channel designators TIM_OCx where x=1..4, TIM_OCxN where x=1..3 (no action taken) @param[in] value Unsigned int32. Compare value. @@ -1485,14 +1581,16 @@ the Break and Deadtime Register. @note It is necessary to call this function to enable the output on an advanced timer even if break or deadtime features are not being used. -@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 +@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or +TIM8 */ void timer_enable_break_main_output(u32 timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) |= TIM_BDTR_MOE; + } #else (void)timer_peripheral; #endif @@ -1506,14 +1604,16 @@ the Master Output Enable in the Break and Deadtime Register. @note This setting is only valid for the advanced timers. -@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 +@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or +TIM8 */ void timer_disable_break_main_output(u32 timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_MOE; + } #else (void)timer_peripheral; #endif @@ -1528,14 +1628,16 @@ break event. @note This setting is only valid for the advanced timers. -@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 +@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or +TIM8 */ void timer_enable_break_automatic_output(u32 timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) |= TIM_BDTR_AOE; + } #else (void)timer_peripheral; #endif @@ -1550,14 +1652,16 @@ break event. @note This setting is only valid for the advanced timers. -@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 +@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or +TIM8 */ void timer_disable_break_automatic_output(u32 timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_AOE; + } #else (void)timer_peripheral; #endif @@ -1570,14 +1674,16 @@ Sets the break function to activate when the break input becomes high. @note This setting is only valid for the advanced timers. -@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 +@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or +TIM8 */ void timer_set_break_polarity_high(u32 timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) |= TIM_BDTR_BKP; + } #else (void)timer_peripheral; #endif @@ -1590,14 +1696,16 @@ Sets the break function to activate when the break input becomes low. @note This setting is only valid for the advanced timers. -@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 +@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or +TIM8 */ void timer_set_break_polarity_low(u32 timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_BKP; + } #else (void)timer_peripheral; #endif @@ -1610,14 +1718,16 @@ Enables the break function of an advanced timer. @note This setting is only valid for the advanced timers. -@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 +@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or +TIM8 */ void timer_enable_break(u32 timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) |= TIM_BDTR_BKE; + } #else (void)timer_peripheral; #endif @@ -1630,14 +1740,16 @@ Disables the break function of an advanced timer. @note This setting is only valid for the advanced timers. -@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 +@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or +TIM8 */ void timer_disable_break(u32 timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_BKE; + } #else (void)timer_peripheral; #endif @@ -1654,14 +1766,16 @@ inactive level as defined by the output polarity. @note This setting is only valid for the advanced timers. -@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 +@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or +TIM8 */ void timer_set_enabled_off_state_in_run_mode(u32 timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) |= TIM_BDTR_OSSR; + } #else (void)timer_peripheral; #endif @@ -1677,14 +1791,16 @@ disabled, the output is also disabled. @note This setting is only valid for the advanced timers. -@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 +@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or +TIM8 */ void timer_set_disabled_off_state_in_run_mode(u32 timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_OSSR; + } #else (void)timer_peripheral; #endif @@ -1699,14 +1815,16 @@ inactive level as defined by the output polarity. @note This setting is only valid for the advanced timers. -@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 +@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or +TIM8 */ void timer_set_enabled_off_state_in_idle_mode(u32 timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) |= TIM_BDTR_OSSI; + } #else (void)timer_peripheral; #endif @@ -1720,14 +1838,16 @@ timer. When the master output is disabled the output is also disabled. @note This setting is only valid for the advanced timers. -@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 +@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or +TIM8 */ void timer_set_disabled_off_state_in_idle_mode(u32 timer_peripheral) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_OSSI; + } #else (void)timer_peripheral; #endif @@ -1742,15 +1862,17 @@ timer reset has occurred. @note This setting is only valid for the advanced timers. -@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 +@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or +TIM8 @param[in] lock Unsigned int32. Lock specification @ref tim_lock */ void timer_set_break_lock(u32 timer_peripheral, u32 lock) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) |= lock; + } #else (void)timer_peripheral; (void)lock; @@ -1760,9 +1882,9 @@ void timer_set_break_lock(u32 timer_peripheral, u32 lock) /*---------------------------------------------------------------------------*/ /** @brief Set Deadtime -The deadtime and sampling clock (DTSC) is set in the clock division ratio part of the -timer mode settings. The deadtime count is an 8 bit value defined in terms of the -number of DTSC cycles: +The deadtime and sampling clock (DTSC) is set in the clock division ratio part +of the timer mode settings. The deadtime count is an 8 bit value defined in +terms of the number of DTSC cycles: @li Bit 7 = 0, deadtime = bits(6:0) @li Bits 7:6 = 10, deadtime = 2x(64+bits(5:0)) @@ -1771,15 +1893,18 @@ number of DTSC cycles: @note This setting is only valid for the advanced timers. -@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or TIM8 -@param[in] deadtime Unsigned int32. Deadtime count specification as defined above. +@param[in] timer_peripheral Unsigned int32. Timer register address base TIM1 or +TIM8 +@param[in] deadtime Unsigned int32. Deadtime count specification as defined +above. */ void timer_set_deadtime(u32 timer_peripheral, u32 deadtime) { #if (defined(TIM1_BASE) || defined(TIM8_BASE)) - if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) + if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8)) { TIM_BDTR(timer_peripheral) |= deadtime; + } #else (void)timer_peripheral; (void)deadtime; @@ -1838,14 +1963,16 @@ void timer_set_counter(u32 timer_peripheral, u32 count) Set the input filter parameters for an input channel, specifying: @li the frequency of sampling from the Deadtime and Sampling clock (@see @ref timer_set_clock_division) -@li the number of events that must occur before a transition is considered valid. +@li the number of events that must occur before a transition is considered +valid. @param[in] timer_peripheral Unsigned int32. Timer register address base @param[in] ic ::tim_ic_id. Input Capture channel designator. @param[in] flt ::tim_ic_filter. Input Capture Filter identifier. */ -void timer_ic_set_filter(u32 timer_peripheral, enum tim_ic_id ic, enum tim_ic_filter flt) +void timer_ic_set_filter(u32 timer_peripheral, enum tim_ic_id ic, + enum tim_ic_filter flt) { switch (ic) { case TIM_IC1: @@ -1877,7 +2004,8 @@ Set the number of events between each capture. @param[in] psc ::tim_ic_psc. Input Capture sample clock prescaler. */ -void timer_ic_set_prescaler(u32 timer_peripheral, enum tim_ic_id ic, enum tim_ic_psc psc) +void timer_ic_set_prescaler(u32 timer_peripheral, enum tim_ic_id ic, + enum tim_ic_psc psc) { switch (ic) { case TIM_IC1: @@ -1902,8 +2030,8 @@ void timer_ic_set_prescaler(u32 timer_peripheral, enum tim_ic_id ic, enum tim_ic /*---------------------------------------------------------------------------*/ /** @brief Set Capture/Compare Channel Direction/Input -The Capture/Compare channel is defined as output (compare) or input with the input -mapping specified: +The Capture/Compare channel is defined as output (compare) or input with the +input mapping specified: @li channel is configured as output @li channel is configured as input and mapped on corresponding input @@ -1920,7 +2048,8 @@ internal trigger input selected through TS bit @param[in] in ::tim_ic_input. Input Capture channel direction and source input. */ -void timer_ic_set_input(u32 timer_peripheral, enum tim_ic_id ic, enum tim_ic_input in) +void timer_ic_set_input(u32 timer_peripheral, enum tim_ic_id ic, + enum tim_ic_input in) { in &= 3; @@ -1980,7 +2109,8 @@ void timer_ic_disable(u32 timer_peripheral, enum tim_ic_id ic) Set the input filter parameters for the external trigger, specifying: @li the frequency of sampling from the Deadtime and Sampling clock (@see @ref timer_set_clock_division) -@li the number of events that must occur before a transition is considered valid. +@li the number of events that must occur before a transition is considered +valid. @param[in] timer_peripheral Unsigned int32. Timer register address base @param[in] flt ::tim_ic_filter. Input Capture Filter identifier. @@ -2016,10 +2146,11 @@ void timer_slave_set_prescaler(u32 timer_peripheral, enum tim_ic_psc psc) void timer_slave_set_polarity(u32 timer_peripheral, enum tim_et_pol pol) { - if (pol) + if (pol) { TIM_SMCR(timer_peripheral) |= TIM_SMCR_ETP; - else + } else { TIM_SMCR(timer_peripheral) &= ~TIM_SMCR_ETP; + } } /*---------------------------------------------------------------------------*/ diff --git a/lib/stm32/common/timer_common_f24.c b/lib/stm32/common/timer_common_f24.c index bde3ee79..3c7c4102 100644 --- a/lib/stm32/common/timer_common_f24.c +++ b/lib/stm32/common/timer_common_f24.c @@ -33,7 +33,8 @@ Set timer options register on TIM2 or TIM5, used for trigger remapping on TIM2, and similarly for TIM5 for oscillator calibration purposes. @param[in] timer_peripheral Unsigned int32. Timer register address base -@returns Unsigned int32. Option flags TIM2: @ref tim2_opt_trigger_remap, TIM5: @ref tim5_opt_trigger_remap. +@returns Unsigned int32. Option flags TIM2: @ref tim2_opt_trigger_remap, TIM5: +@ref tim5_opt_trigger_remap. */ void timer_set_option(u32 timer_peripheral, u32 option) @@ -57,20 +58,22 @@ The timer channel must be set to input capture mode. @param[in] pol ::tim_ic_pol. Input Capture polarity control. */ -void timer_ic_set_polarity(u32 timer_peripheral, enum tim_ic_id ic, enum tim_ic_pol pol) +void timer_ic_set_polarity(u32 timer_peripheral, enum tim_ic_id ic, + enum tim_ic_pol pol) { -/* Clear CCxP and CCxNP to zero. For both edge trigger both fields are set. Case 10 is invalid. */ - TIM_CCER(timer_peripheral) &= ~(0x6 << (ic * 4)); - switch (pol) - { - case TIM_IC_RISING: /* 00 */ - break; - case TIM_IC_BOTH: /* 11 */ - TIM_CCER(timer_peripheral) |= (0x6 << (ic * 4)); - break; - case TIM_IC_FALLING: /* 01 */ - TIM_CCER(timer_peripheral) |= (0x2 << (ic * 4)); - } + /* Clear CCxP and CCxNP to zero. For both edge trigger both fields are + * set. Case 10 is invalid. + */ + TIM_CCER(timer_peripheral) &= ~(0x6 << (ic * 4)); + switch (pol) { + case TIM_IC_RISING: /* 00 */ + break; + case TIM_IC_BOTH: /* 11 */ + TIM_CCER(timer_peripheral) |= (0x6 << (ic * 4)); + break; + case TIM_IC_FALLING: /* 01 */ + TIM_CCER(timer_peripheral) |= (0x2 << (ic * 4)); + } } /**@}*/ diff --git a/lib/stm32/common/usart_common_all.c b/lib/stm32/common/usart_common_all.c index 198bf855..bea68e8d 100644 --- a/lib/stm32/common/usart_common_all.c +++ b/lib/stm32/common/usart_common_all.c @@ -33,15 +33,16 @@ Devices can have up to 3 USARTs and 2 UARTs. #include #include -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief USART Set Baudrate. -The baud rate is computed from the APB high-speed prescaler clock (for USART1/6) -or the APB low-speed prescaler clock (for other USARTs). These values must -be correctly set before calling this function (refer to the rcc_clock_setup-* -functions in RCC). +The baud rate is computed from the APB high-speed prescaler clock (for +USART1/6) or the APB low-speed prescaler clock (for other USARTs). These values +must be correctly set before calling this function (refer to the +rcc_clock_setup-* functions in RCC). -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] usart unsigned 32 bit. USART block register address base @ref +usart_reg_base @param[in] baud unsigned 32 bit. Baud rate specified in Hz. */ @@ -72,30 +73,34 @@ void usart_set_baudrate(u32 usart, u32 baud) USART_BRR(usart) = ((2 * clock) + baud) / (2 * baud); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief USART Set Word Length. -The word length is set to 8 or 9 bits. Note that the last bit will be a parity bit -if parity is enabled, in which case the data length will be 7 or 8 bits respectively. +The word length is set to 8 or 9 bits. Note that the last bit will be a parity +bit if parity is enabled, in which case the data length will be 7 or 8 bits +respectively. -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] usart unsigned 32 bit. USART block register address base @ref +usart_reg_base @param[in] bits unsigned 32 bit. Word length in bits 8 or 9. */ void usart_set_databits(u32 usart, u32 bits) { - if (bits == 8) + if (bits == 8) { USART_CR1(usart) &= ~USART_CR1_M; /* 8 data bits */ - else + } else { USART_CR1(usart) |= USART_CR1_M; /* 9 data bits */ + } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief USART Set Stop Bit(s). The stop bits are specified as 0.5, 1, 1.5 or 2. -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] usart unsigned 32 bit. USART block register address base @ref +usart_reg_base @param[in] stopbits unsigned 32 bit. Stop bits @ref usart_cr2_stopbits. */ @@ -108,12 +113,13 @@ void usart_set_stopbits(u32 usart, u32 stopbits) USART_CR2(usart) = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief USART Set Parity. The parity bit can be selected as none, even or odd. -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] usart unsigned 32 bit. USART block register address base @ref +usart_reg_base @param[in] parity unsigned 32 bit. Parity @ref usart_cr1_parity. */ @@ -126,12 +132,13 @@ void usart_set_parity(u32 usart, u32 parity) USART_CR1(usart) = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief USART Set Rx/Tx Mode. The mode can be selected as Rx only, Tx only or Rx+Tx. -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] usart unsigned 32 bit. USART block register address base @ref +usart_reg_base @param[in] mode unsigned 32 bit. Mode @ref usart_cr1_mode. */ @@ -144,12 +151,13 @@ void usart_set_mode(u32 usart, u32 mode) USART_CR1(usart) = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief USART Set Hardware Flow Control. The flow control bit can be selected as none, RTS, CTS or RTS+CTS. -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] usart unsigned 32 bit. USART block register address base @ref +usart_reg_base @param[in] flowcontrol unsigned 32 bit. Flowcontrol @ref usart_cr3_flowcontrol. */ @@ -162,10 +170,11 @@ void usart_set_flow_control(u32 usart, u32 flowcontrol) USART_CR3(usart) = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief USART Enable. -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] usart unsigned 32 bit. USART block register address base @ref +usart_reg_base */ void usart_enable(u32 usart) @@ -173,12 +182,13 @@ void usart_enable(u32 usart) USART_CR1(usart) |= USART_CR1_UE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief USART Disable. At the end of the current frame, the USART is disabled to reduce power. -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] usart unsigned 32 bit. USART block register address base @ref +usart_reg_base */ void usart_disable(u32 usart) @@ -186,10 +196,11 @@ void usart_disable(u32 usart) USART_CR1(usart) &= ~USART_CR1_UE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief USART Send a Data Word. -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] usart unsigned 32 bit. USART block register address base @ref +usart_reg_base @param[in] data unsigned 16 bit. */ @@ -199,12 +210,14 @@ void usart_send(u32 usart, u16 data) USART_DR(usart) = (data & USART_DR_MASK); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief USART Read a Received Data Word. -If parity is enabled the MSB (bit 7 or 8 depending on the word length) is the parity bit. +If parity is enabled the MSB (bit 7 or 8 depending on the word length) is the +parity bit. -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] usart unsigned 32 bit. USART block register address base @ref +usart_reg_base @returns unsigned 16 bit data word. */ @@ -214,13 +227,14 @@ u16 usart_recv(u32 usart) return USART_DR(usart) & USART_DR_MASK; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief USART Wait for Transmit Data Buffer Empty Blocks until the transmit data buffer becomes empty and is ready to accept the next data word. -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] usart unsigned 32 bit. USART block register address base @ref +usart_reg_base */ void usart_wait_send_ready(u32 usart) @@ -229,12 +243,13 @@ void usart_wait_send_ready(u32 usart) while ((USART_SR(usart) & USART_SR_TXE) == 0); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief USART Wait for Received Data Available Blocks until the receive data buffer holds a valid received data word. -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] usart unsigned 32 bit. USART block register address base @ref +usart_reg_base */ void usart_wait_recv_ready(u32 usart) @@ -243,13 +258,14 @@ void usart_wait_recv_ready(u32 usart) while ((USART_SR(usart) & USART_SR_RXNE) == 0); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief USART Send Data Word with Blocking -Blocks until the transmit data buffer becomes empty then writes the next data word -for transmission. +Blocks until the transmit data buffer becomes empty then writes the next data +word for transmission. -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] usart unsigned 32 bit. USART block register address base @ref +usart_reg_base @param[in] data unsigned 16 bit. */ @@ -259,12 +275,13 @@ void usart_send_blocking(u32 usart, u16 data) usart_send(usart, data); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief USART Read a Received Data Word with Blocking. Wait until a data word has been received then return the word. -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] usart unsigned 32 bit. USART block register address base @ref +usart_reg_base @returns unsigned 16 bit data word. */ @@ -275,7 +292,7 @@ u16 usart_recv_blocking(u32 usart) return usart_recv(usart); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief USART Receiver DMA Enable. DMA is available on: @@ -284,7 +301,8 @@ DMA is available on: @li USART3 Rx DMA1 channel 3. @li UART4 Rx DMA2 channel 3. -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] usart unsigned 32 bit. USART block register address base @ref +usart_reg_base */ void usart_enable_rx_dma(u32 usart) @@ -292,10 +310,11 @@ void usart_enable_rx_dma(u32 usart) USART_CR3(usart) |= USART_CR3_DMAR; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief USART Receiver DMA Disable. -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] usart unsigned 32 bit. USART block register address base @ref +usart_reg_base */ void usart_disable_rx_dma(u32 usart) @@ -303,7 +322,7 @@ void usart_disable_rx_dma(u32 usart) USART_CR3(usart) &= ~USART_CR3_DMAR; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief USART Transmitter DMA Enable. DMA is available on: @@ -312,7 +331,8 @@ DMA is available on: @li USART3 Tx DMA1 channel 2. @li UART4 Tx DMA2 channel 5. -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] usart unsigned 32 bit. USART block register address base @ref +usart_reg_base */ void usart_enable_tx_dma(u32 usart) @@ -320,10 +340,11 @@ void usart_enable_tx_dma(u32 usart) USART_CR3(usart) |= USART_CR3_DMAT; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief USART Transmitter DMA Disable. -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] usart unsigned 32 bit. USART block register address base @ref +usart_reg_base */ void usart_disable_tx_dma(u32 usart) @@ -331,10 +352,11 @@ void usart_disable_tx_dma(u32 usart) USART_CR3(usart) &= ~USART_CR3_DMAT; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief USART Receiver Interrupt Enable. -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] usart unsigned 32 bit. USART block register address base @ref +usart_reg_base */ void usart_enable_rx_interrupt(u32 usart) @@ -343,10 +365,11 @@ void usart_enable_rx_interrupt(u32 usart) } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief USART Receiver Interrupt Disable. -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] usart unsigned 32 bit. USART block register address base @ref +usart_reg_base */ void usart_disable_rx_interrupt(u32 usart) @@ -354,10 +377,11 @@ void usart_disable_rx_interrupt(u32 usart) USART_CR1(usart) &= ~USART_CR1_RXNEIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief USART Transmitter Interrupt Enable. -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] usart unsigned 32 bit. USART block register address base @ref +usart_reg_base */ void usart_enable_tx_interrupt(u32 usart) @@ -365,10 +389,11 @@ void usart_enable_tx_interrupt(u32 usart) USART_CR1(usart) |= USART_CR1_TXEIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief USART Transmitter Interrupt Disable. -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] usart unsigned 32 bit. USART block register address base @ref +usart_reg_base */ void usart_disable_tx_interrupt(u32 usart) @@ -376,10 +401,11 @@ void usart_disable_tx_interrupt(u32 usart) USART_CR1(usart) &= ~USART_CR1_TXEIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief USART Error Interrupt Enable. -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] usart unsigned 32 bit. USART block register address base @ref +usart_reg_base */ void usart_enable_error_interrupt(u32 usart) @@ -387,10 +413,11 @@ void usart_enable_error_interrupt(u32 usart) USART_CR3(usart) |= USART_CR3_EIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief USART Error Interrupt Disable. -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] usart unsigned 32 bit. USART block register address base @ref +usart_reg_base */ void usart_disable_error_interrupt(u32 usart) @@ -401,7 +428,8 @@ void usart_disable_error_interrupt(u32 usart) /*---------------------------------------------------------------------------*/ /** @brief USART Read a Status Flag. -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] usart unsigned 32 bit. USART block register address base @ref +usart_reg_base @param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags. @returns boolean: flag set. */ @@ -422,7 +450,8 @@ flag, the function returns false. relating to LIN break, and error conditions in multibuffer communication, need to be added for completeness. -@param[in] usart unsigned 32 bit. USART block register address base @ref usart_reg_base +@param[in] usart unsigned 32 bit. USART block register address base @ref +usart_reg_base @param[in] flag Unsigned int32. Status register flag @ref usart_sr_flags. @returns boolean: flag and interrupt enable both set. */ @@ -430,13 +459,15 @@ to be added for completeness. bool usart_get_interrupt_source(u32 usart, u32 flag) { u32 flag_set = (USART_SR(usart) & flag); -/* IDLE, RXNE, TC, TXE interrupts */ - if ((flag >= USART_SR_IDLE) && (flag <= USART_SR_TXE)) + /* IDLE, RXNE, TC, TXE interrupts */ + if ((flag >= USART_SR_IDLE) && (flag <= USART_SR_TXE)) { return ((flag_set & USART_CR1(usart)) != 0); -/* Overrun error */ - else if (flag == USART_SR_ORE) - return (flag_set && (USART_CR3(usart) & USART_CR3_CTSIE)); - return (false); + /* Overrun error */ + } else if (flag == USART_SR_ORE) { + return flag_set && (USART_CR3(usart) & USART_CR3_CTSIE); + } + + return false; } /**@}*/ diff --git a/lib/stm32/desig.c b/lib/stm32/desig.c index ea861aaa..a32d0d7f 100644 --- a/lib/stm32/desig.c +++ b/lib/stm32/desig.c @@ -21,19 +21,20 @@ u16 desig_get_flash_size(void) { - return DESIG_FLASH_SIZE; + return DESIG_FLASH_SIZE; } void desig_get_unique_id(u32 result[]) { - // Could also just return a pointer to the start? read it as they wish? - u16 bits15_0 = DESIG_UID_15_0; - u32 bits31_16 = DESIG_UID_31_16; - u32 bits63_32 = DESIG_UID_63_32; - u32 bits95_64 = DESIG_UID_95_64; - result[0] = bits95_64; - result[1] = bits63_32; - result[2] = bits31_16 << 16 | bits15_0; + /* Could also just return a pointer to the start? read it as they wish? + */ + u16 bits15_0 = DESIG_UID_15_0; + u32 bits31_16 = DESIG_UID_31_16; + u32 bits63_32 = DESIG_UID_63_32; + u32 bits95_64 = DESIG_UID_95_64; + result[0] = bits95_64; + result[1] = bits63_32; + result[2] = bits31_16 << 16 | bits15_0; } void desig_get_unique_id_as_string(char *string, diff --git a/lib/stm32/f1/adc.c b/lib/stm32/f1/adc.c index 148d71cc..9dcfe541 100644 --- a/lib/stm32/f1/adc.c +++ b/lib/stm32/f1/adc.c @@ -6,40 +6,46 @@ @version 1.0.0 -@author @htmlonly © @endhtmlonly 2009 Edward Cheeseman -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies +@author @htmlonly © @endhtmlonly 2009 +Edward Cheeseman +@author @htmlonly © @endhtmlonly 2012 +Ken Sarkies @date 18 August 2012 This library supports the A/D Converter Control System in the STM32F1xx series of ARM Cortex Microcontrollers by ST Microelectronics. -Devices can have up to three A/D converters each with their own set of registers. -However all the A/D converters share a common clock which is prescaled from the APB2 -clock by default by a minimum factor of 2 to a maximum of 8. +Devices can have up to three A/D converters each with their own set of +registers. However all the A/D converters share a common clock which is +prescaled from the APB2 clock by default by a minimum factor of 2 to a maximum +of 8. Each A/D converter has up to 18 channels: -@li On ADC1 the analog channels 16 and 17 are internally connected to the temperature +@li On ADC1 the analog channels 16 and 17 are internally connected to the +temperature sensor and VREFINT, respectively. -@li On ADC2 the analog channels 16 and 17 are internally connected to VSS. -@li On ADC3 the analog channels 9, 14, 15, 16 and 17 are internally connected to VSS. +@li On ADC2 the analog channels 16 and 17 are internally connected to +VSS. +@li On ADC3 the analog channels 9, 14, 15, 16 and 17 are internally connected +to VSS. -The conversions can occur as a one-off conversion whereby the process stops once -conversion is complete. The conversions can also be continuous wherein a new -conversion starts immediately the previous conversion has ended. +The conversions can occur as a one-off conversion whereby the process stops +once conversion is complete. The conversions can also be continuous wherein a +new conversion starts immediately the previous conversion has ended. Conversion can occur as a single channel conversion or a scan of a group of -channels in either continuous or one-off mode. If more than one channel is converted -in a scan group, DMA must be used to transfer the data as there is only one -result register available. An interrupt can be set to occur at the end of -conversion, which occurs after all channels have been scanned. +channels in either continuous or one-off mode. If more than one channel is +converted in a scan group, DMA must be used to transfer the data as there is +only one result register available. An interrupt can be set to occur at the end +of conversion, which occurs after all channels have been scanned. -A discontinuous mode allows a subgroup of group of a channels to be converted in -bursts of a given length. +A discontinuous mode allows a subgroup of group of a channels to be converted +in bursts of a given length. -Injected conversions allow a second group of channels to be converted separately -from the regular group. An interrupt can be set to occur at the end of -conversion, which occurs after all channels have been scanned. +Injected conversions allow a second group of channels to be converted +separately from the regular group. An interrupt can be set to occur at the end +of conversion, which occurs after all channels have been scanned. @section adc_api_ex Basic ADC Handling API. @@ -48,23 +54,23 @@ and ADC, reset ADC and set the prescaler divider. Set dual mode to independent (default). Enable triggering for a software trigger. @code - rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN); - adc_off(ADC1); - rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_ADC1RST); - rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_ADC1RST); - rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2); - adc_set_dual_mode(ADC_CR1_DUALMOD_IND); - adc_disable_scan_mode(ADC1); - adc_set_single_conversion_mode(ADC1); - adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR1_SMP_1DOT5CYC); - adc_set_single_channel(ADC1, ADC_CHANNEL0); - adc_enable_trigger(ADC1, ADC_CR2_EXTSEL_SWSTART); - adc_power_on(ADC1); - adc_reset_calibration(ADC1); - adc_calibration(ADC1); - adc_start_conversion_regular(ADC1); - while (! adc_eoc(ADC1)); - reg16 = adc_read_regular(ADC1); + rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_ADC1EN); + adc_off(ADC1); + rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_ADC1RST); + rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_ADC1RST); + rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2); + adc_set_dual_mode(ADC_CR1_DUALMOD_IND); + adc_disable_scan_mode(ADC1); + adc_set_single_conversion_mode(ADC1); + adc_set_sample_time(ADC1, ADC_CHANNEL0, ADC_SMPR1_SMP_1DOT5CYC); + adc_set_single_channel(ADC1, ADC_CHANNEL0); + adc_enable_trigger(ADC1, ADC_CR2_EXTSEL_SWSTART); + adc_power_on(ADC1); + adc_reset_calibration(ADC1); + adc_calibration(ADC1); + adc_start_conversion_regular(ADC1); + while (! adc_eoc(ADC1)); + reg16 = adc_read_regular(ADC1); @endcode LGPL License Terms @ref lgpl_license @@ -106,7 +112,7 @@ LGPL License Terms @ref lgpl_license #include -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Power On If the ADC is in power-down mode then it is powered up. The application needs @@ -118,42 +124,46 @@ If the ADC is already on this function call has no effect. void adc_power_on(u32 adc) { - if (!(ADC_CR2(adc) & ADC_CR2_ADON)) + if (!(ADC_CR2(adc) & ADC_CR2_ADON)) { ADC_CR2(adc) |= ADC_CR2_ADON; + } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Start a Conversion Without Trigger This initiates a conversion by software without a trigger. The ADC needs to be -powered on before this is called, otherwise this function has no effect. +powered on before this is called, otherwise this function has no effect. -Note that this is not available in other STM32F families. To ensure code compatibility, -enable triggering and use a software trigger source @see adc_start_conversion_regular. +Note that this is not available in other STM32F families. To ensure code +compatibility, enable triggering and use a software trigger source @see +adc_start_conversion_regular. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ void adc_start_conversion_direct(u32 adc) { - if (ADC_CR2(adc) & ADC_CR2_ADON) - ADC_CR2(adc) |= ADC_CR2_ADON; + if (ADC_CR2(adc) & ADC_CR2_ADON) { + ADC_CR2(adc) |= ADC_CR2_ADON; + } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set Dual A/D Mode The dual mode uses ADC1 as master and ADC2 in a slave arrangement. This setting -is applied to ADC1 only. Start of conversion when triggered can cause simultaneous -conversion with ADC2, or alternate conversion. Regular and injected conversions -can be configured, each one being separately simultaneous or alternate. +is applied to ADC1 only. Start of conversion when triggered can cause +simultaneous conversion with ADC2, or alternate conversion. Regular and +injected conversions can be configured, each one being separately simultaneous +or alternate. Fast interleaved mode starts ADC1 immediately on trigger, and ADC2 seven clock cycles later. -Slow interleaved mode starts ADC1 immediately on trigger, and ADC2 fourteen clock -cycles later, followed by ADC1 fourteen cycles later again. This can only be used -on a single channel. +Slow interleaved mode starts ADC1 immediately on trigger, and ADC2 fourteen +clock cycles later, followed by ADC1 fourteen cycles later again. This can only +be used on a single channel. Alternate trigger mode must occur on an injected channel group, and alternates between the ADCs on each trigger. @@ -181,116 +191,123 @@ void adc_set_dual_mode(u32 mode) ADC1_CR1 |= mode; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Read the End-of-Conversion Flag This flag is set after all channels of a regular or injected group have been converted. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. @returns bool. End of conversion flag. */ bool adc_eoc(u32 adc) { - return ((ADC_SR(adc) & ADC_SR_EOC) != 0); + return ((ADC_SR(adc) & ADC_SR_EOC) != 0); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Read the End-of-Conversion Flag for Injected Conversion This flag is set after all channels of an injected group have been converted. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. @returns bool. End of conversion flag. */ bool adc_eoc_injected(u32 adc) { - return ((ADC_SR(adc) & ADC_SR_JEOC) != 0); + return ((ADC_SR(adc) & ADC_SR_JEOC) != 0); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Read from the Regular Conversion Result Register The result read back is 12 bits, right or left aligned within the first 16 bits. For ADC1 only, the higher 16 bits will hold the result from ADC2 if an appropriate dual mode has been set @see adc_set_dual_mode. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. @returns Unsigned int32 conversion result. */ u32 adc_read_regular(u32 adc) { - return ADC_DR(adc); + return ADC_DR(adc); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Read from an Injected Conversion Result Register -The result read back from the selected injected result register (one of four) is -12 bits, right or left aligned within the first 16 bits. The result can have a -negative value if the injected channel offset has been set @see adc_set_injected_offset. +The result read back from the selected injected result register (one of four) +is 12 bits, right or left aligned within the first 16 bits. The result can have +a negative value if the injected channel offset has been set @see +adc_set_injected_offset. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. @param[in] reg Unsigned int8. Register number (1 ... 4). @returns Unsigned int32 conversion result. */ u32 adc_read_injected(u32 adc, u8 reg) { - switch (reg) { - case 1: - return ADC_JDR1(adc); - case 2: - return ADC_JDR2(adc); - case 3: - return ADC_JDR3(adc); - case 4: - return ADC_JDR4(adc); - } + switch (reg) { + case 1: + return ADC_JDR1(adc); + case 2: + return ADC_JDR2(adc); + case 3: + return ADC_JDR3(adc); + case 4: + return ADC_JDR4(adc); + } return 0; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set the Injected Channel Data Offset -This value is subtracted from the injected channel results after conversion -is complete, and can result in negative results. A separate value can be specified +This value is subtracted from the injected channel results after conversion is +complete, and can result in negative results. A separate value can be specified for each injected data register. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. @param[in] reg Unsigned int8. Register number (1 ... 4). @param[in] offset Unsigned int32. */ void adc_set_injected_offset(u32 adc, u8 reg, u32 offset) { - switch (reg) { - case 1: - ADC_JOFR1(adc) = offset; - break; - case 2: - ADC_JOFR2(adc) = offset; - break; - case 3: - ADC_JOFR3(adc) = offset; - break; - case 4: - ADC_JOFR4(adc) = offset; - break; - } + switch (reg) { + case 1: + ADC_JOFR1(adc) = offset; + break; + case 2: + ADC_JOFR2(adc) = offset; + break; + case 3: + ADC_JOFR3(adc) = offset; + break; + case 4: + ADC_JOFR4(adc) = offset; + break; + } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for Regular Conversions -The analog watchdog allows the monitoring of an analog signal between two threshold -levels. The thresholds must be preset. Comparison is done before data alignment -takes place, so the thresholds are left-aligned. +The analog watchdog allows the monitoring of an analog signal between two +threshold levels. The thresholds must be preset. Comparison is done before data +alignment takes place, so the thresholds are left-aligned. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_enable_analog_watchdog_regular(u32 adc) @@ -298,10 +315,11 @@ void adc_enable_analog_watchdog_regular(u32 adc) ADC_CR1(adc) |= ADC_CR1_AWDEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable Analog Watchdog for Regular Conversions -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_disable_analog_watchdog_regular(u32 adc) @@ -309,14 +327,15 @@ void adc_disable_analog_watchdog_regular(u32 adc) ADC_CR1(adc) &= ~ADC_CR1_AWDEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for Injected Conversions -The analog watchdog allows the monitoring of an analog signal between two threshold -levels. The thresholds must be preset. Comparison is done before data alignment -takes place, so the thresholds are left-aligned. +The analog watchdog allows the monitoring of an analog signal between two +threshold levels. The thresholds must be preset. Comparison is done before data +alignment takes place, so the thresholds are left-aligned. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_enable_analog_watchdog_injected(u32 adc) @@ -324,10 +343,11 @@ void adc_enable_analog_watchdog_injected(u32 adc) ADC_CR1(adc) |= ADC_CR1_JAWDEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable Analog Watchdog for Injected Conversions -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_disable_analog_watchdog_injected(u32 adc) @@ -335,7 +355,7 @@ void adc_disable_analog_watchdog_injected(u32 adc) ADC_CR1(adc) &= ~ADC_CR1_JAWDEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Discontinuous Mode for Regular Conversions In this mode the ADC converts, on each trigger, a subgroup of up to 8 of the @@ -346,21 +366,26 @@ of the same length or until the whole group has all been converted. When the the whole group has been converted, the next trigger will restart conversion of the subgroup at the beginning of the whole group. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. -@param[in] length Unsigned int8. Number of channels in the group @ref adc_cr1_discnum. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. +@param[in] length Unsigned int8. Number of channels in the group @ref +adc_cr1_discnum. */ void adc_enable_discontinuous_mode_regular(u32 adc, u8 length) { - if ( (length-1) > 7 ) return; - ADC_CR1(adc) |= ADC_CR1_DISCEN; - ADC_CR1(adc) |= ((length-1) << ADC_CR1_DISCNUM_SHIFT); + if ((length-1) > 7) { + return; + } + ADC_CR1(adc) |= ADC_CR1_DISCEN; + ADC_CR1(adc) |= ((length-1) << ADC_CR1_DISCNUM_SHIFT); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable Discontinuous Mode for Regular Conversions -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_disable_discontinuous_mode_regular(u32 adc) @@ -368,14 +393,15 @@ void adc_disable_discontinuous_mode_regular(u32 adc) ADC_CR1(adc) &= ~ADC_CR1_DISCEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Discontinuous Mode for Injected Conversions In this mode the ADC converts sequentially one channel of the defined group of injected channels, cycling back to the first channel in the group once the entire group has been converted. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_enable_discontinuous_mode_injected(u32 adc) @@ -383,10 +409,11 @@ void adc_enable_discontinuous_mode_injected(u32 adc) ADC_CR1(adc) |= ADC_CR1_JDISCEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable Discontinuous Mode for Injected Conversions -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_disable_discontinuous_mode_injected(u32 adc) @@ -394,26 +421,28 @@ void adc_disable_discontinuous_mode_injected(u32 adc) ADC_CR1(adc) &= ~ADC_CR1_JDISCEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Automatic Injected Conversions The ADC converts a defined injected group of channels immediately after the regular channels have been converted. The external trigger on the injected channels is disabled as required. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base */ void adc_enable_automatic_injected_group_conversion(u32 adc) { - adc_disable_external_trigger_injected(adc); + adc_disable_external_trigger_injected(adc); ADC_CR1(adc) |= ADC_CR1_JAUTO; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable Automatic Injected Conversions -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_disable_automatic_injected_group_conversion(u32 adc) @@ -421,19 +450,21 @@ void adc_disable_automatic_injected_group_conversion(u32 adc) ADC_CR1(adc) &= ~ADC_CR1_JAUTO; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for All Regular and/or Injected Channels -The analog watchdog allows the monitoring of an analog signal between two threshold -levels. The thresholds must be preset. Comparison is done before data alignment -takes place, so the thresholds are left-aligned. +The analog watchdog allows the monitoring of an analog signal between two +threshold levels. The thresholds must be preset. Comparison is done before data +alignment takes place, so the thresholds are left-aligned. @note The analog watchdog must be enabled for either or both of the regular or injected channels. If neither are enabled, the analog watchdog feature will be disabled. -@ref adc_enable_analog_watchdog_injected, @ref adc_enable_analog_watchdog_regular. +@ref adc_enable_analog_watchdog_injected, @ref +adc_enable_analog_watchdog_regular. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_enable_analog_watchdog_on_all_channels(u32 adc) @@ -441,19 +472,21 @@ void adc_enable_analog_watchdog_on_all_channels(u32 adc) ADC_CR1(adc) &= ~ADC_CR1_AWDSGL; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for a Selected Channel -The analog watchdog allows the monitoring of an analog signal between two threshold -levels. The thresholds must be preset. Comparison is done before data alignment -takes place, so the thresholds are left-aligned. +The analog watchdog allows the monitoring of an analog signal between two +threshold levels. The thresholds must be preset. Comparison is done before data +alignment takes place, so the thresholds are left-aligned. @note The analog watchdog must be enabled for either or both of the regular or injected channels. If neither are enabled, the analog watchdog feature will be disabled. If both are enabled, the same channel number is monitored. -@ref adc_enable_analog_watchdog_injected, @ref adc_enable_analog_watchdog_regular. +@ref adc_enable_analog_watchdog_injected, @ref +adc_enable_analog_watchdog_regular. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. @param[in] channel Unsigned int8. ADC channel number @ref adc_watchdog_channel. */ @@ -462,20 +495,22 @@ void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel) u32 reg32; reg32 = (ADC_CR1(adc) & 0xffffffe0); /* Clear bits [4:0]. */ - if (channel < 18) + if (channel < 18) { reg32 |= channel; + } ADC_CR1(adc) = reg32; ADC_CR1(adc) |= ADC_CR1_AWDSGL; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set Scan Mode In this mode a conversion consists of a scan of the predefined set of channels, regular and injected, each channel conversion immediately following the previous one. It can use single, continuous or discontinuous mode. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_enable_scan_mode(u32 adc) @@ -483,7 +518,7 @@ void adc_enable_scan_mode(u32 adc) ADC_CR1(adc) |= ADC_CR1_SCAN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable Scan Mode @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -494,10 +529,11 @@ void adc_disable_scan_mode(u32 adc) ADC_CR1(adc) &= ~ADC_CR1_SCAN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Injected End-Of-Conversion Interrupt -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_enable_eoc_interrupt_injected(u32 adc) @@ -505,10 +541,11 @@ void adc_enable_eoc_interrupt_injected(u32 adc) ADC_CR1(adc) |= ADC_CR1_JEOCIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable Injected End-Of-Conversion Interrupt -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_disable_eoc_interrupt_injected(u32 adc) @@ -516,10 +553,11 @@ void adc_disable_eoc_interrupt_injected(u32 adc) ADC_CR1(adc) &= ~ADC_CR1_JEOCIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog Interrupt -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_enable_awd_interrupt(u32 adc) @@ -527,10 +565,11 @@ void adc_enable_awd_interrupt(u32 adc) ADC_CR1(adc) |= ADC_CR1_AWDIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable Analog Watchdog Interrupt -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_disable_awd_interrupt(u32 adc) @@ -538,10 +577,11 @@ void adc_disable_awd_interrupt(u32 adc) ADC_CR1(adc) &= ~ADC_CR1_AWDIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Regular End-Of-Conversion Interrupt -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_enable_eoc_interrupt(u32 adc) @@ -549,10 +589,11 @@ void adc_enable_eoc_interrupt(u32 adc) ADC_CR1(adc) |= ADC_CR1_EOCIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable Regular End-Of-Conversion Interrupt -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_disable_eoc_interrupt(u32 adc) @@ -560,13 +601,14 @@ void adc_disable_eoc_interrupt(u32 adc) ADC_CR1(adc) &= ~ADC_CR1_EOCIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable The Temperature Sensor This enables both the sensor and the reference voltage measurements on channels 16 and 17. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_enable_temperature_sensor(u32 adc) @@ -574,13 +616,14 @@ void adc_enable_temperature_sensor(u32 adc) ADC_CR2(adc) |= ADC_CR2_TSVREFE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable The Temperature Sensor Disabling this will reduce power consumption from the sensor and the reference voltage measurements. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_disable_temperature_sensor(u32 adc) @@ -588,7 +631,7 @@ void adc_disable_temperature_sensor(u32 adc) ADC_CR2(adc) &= ~ADC_CR2_TSVREFE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Software Triggered Conversion on Regular Channels This starts conversion on a set of defined regular channels if the ADC trigger @@ -599,7 +642,8 @@ Note this is a software trigger and requires triggering to be enabled and the trigger source to be set appropriately otherwise conversion will not start. This is not the same as the ADC start conversion operation. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_start_conversion_regular(u32 adc) @@ -611,7 +655,7 @@ void adc_start_conversion_regular(u32 adc) while (ADC_CR2(adc) & ADC_CR2_SWSTART); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Software Triggered Conversion on Injected Channels This starts conversion on a set of defined injected channels if the ADC trigger @@ -622,7 +666,8 @@ Note this is a software trigger and requires triggering to be enabled and the trigger source to be set appropriately otherwise conversion will not start. This is not the same as the ADC start conversion operation. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_start_conversion_injected(u32 adc) @@ -634,7 +679,7 @@ void adc_start_conversion_injected(u32 adc) while (ADC_CR2(adc) & ADC_CR2_JSWSTART); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable an External Trigger for Regular Channels This enables an external trigger for set of defined regular channels. @@ -659,7 +704,8 @@ For ADC3 @li Timer 5 CC3 event @li Software Start -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. @param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_regular_12 for ADC1 and ADC2, or @ref adc_trigger_regular_3 for ADC3. */ @@ -674,10 +720,11 @@ void adc_enable_external_trigger_regular(u32 adc, u32 trigger) ADC_CR2(adc) |= ADC_CR2_EXTTRIG; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable an External Trigger for Regular Channels -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_disable_external_trigger_regular(u32 adc) @@ -685,7 +732,7 @@ void adc_disable_external_trigger_regular(u32 adc) ADC_CR2(adc) &= ~ADC_CR2_EXTTRIG; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable an External Trigger for Injected Channels This enables an external trigger for set of defined injected channels. @@ -710,24 +757,28 @@ For ADC3 @li Timer 5 CC4 event @li Software Start -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. -@param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_injected_12 -for ADC1 and ADC2, or @ref adc_trigger_injected_3 for ADC3. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. +@param[in] trigger Unsigned int8. Trigger identifier @ref +adc_trigger_injected_12 for ADC1 and ADC2, or @ref adc_trigger_injected_3 for +ADC3. */ void adc_enable_external_trigger_injected(u32 adc, u32 trigger) { u32 reg32; - reg32 = (ADC_CR2(adc) & ~(ADC_CR2_JEXTSEL_MASK)); /* Clear bits [12:14]. */ + reg32 = (ADC_CR2(adc) & ~(ADC_CR2_JEXTSEL_MASK)); /* Clear bits [12:14] + */ reg32 |= (trigger); ADC_CR2(adc) = reg32; ADC_CR2(adc) |= ADC_CR2_JEXTTRIG; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable an External Trigger for Injected Channels -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_disable_external_trigger_injected(u32 adc) @@ -735,10 +786,11 @@ void adc_disable_external_trigger_injected(u32 adc) ADC_CR2(adc) &= ~ADC_CR2_JEXTTRIG; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set the Data as Left Aligned -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_set_left_aligned(u32 adc) @@ -746,10 +798,11 @@ void adc_set_left_aligned(u32 adc) ADC_CR2(adc) |= ADC_CR2_ALIGN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set the Data as Right Aligned -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_set_right_aligned(u32 adc) @@ -757,41 +810,46 @@ void adc_set_right_aligned(u32 adc) ADC_CR2(adc) &= ~ADC_CR2_ALIGN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable DMA Transfers Only available for ADC1 through DMA1 channel1, and ADC3 through DMA2 channel5. ADC2 will use DMA if it is set as slave in dual mode with ADC1 in DMA transfer mode. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_enable_dma(u32 adc) { - if ((adc == ADC1) | (adc == ADC3)) + if ((adc == ADC1) | (adc == ADC3)) { ADC_CR2(adc) |= ADC_CR2_DMA; + } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable DMA Transfers -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_disable_dma(u32 adc) { - if ((adc == ADC1) | (adc == ADC3)) + if ((adc == ADC1) | (adc == ADC3)) { ADC_CR2(adc) &= ~ADC_CR2_DMA; + } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Initialize Calibration Registers This resets the calibration registers. It is not clear if this is required to be done before every calibration operation. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_reset_calibration(u32 adc) @@ -800,17 +858,18 @@ void adc_reset_calibration(u32 adc) while (ADC_CR2(adc) & ADC_CR2_RSTCAL); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Calibration The calibration data for the ADC is recomputed. The hardware clears the -calibration status flag when calibration is complete. This function does not return -until this happens and the ADC is ready for use. +calibration status flag when calibration is complete. This function does not +return until this happens and the ADC is ready for use. -The ADC must have been powered down for at least 2 ADC clock cycles, then powered on. -before calibration starts +The ADC must have been powered down for at least 2 ADC clock cycles, then +powered on. before calibration starts -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_calibration(u32 adc) @@ -819,13 +878,14 @@ void adc_calibration(u32 adc) while (ADC_CR2(adc) & ADC_CR2_CAL); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Continuous Conversion Mode In this mode the ADC starts a new conversion of a single channel or a channel group immediately following completion of the previous channel group conversion. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_set_continuous_conversion_mode(u32 adc) @@ -833,13 +893,14 @@ void adc_set_continuous_conversion_mode(u32 adc) ADC_CR2(adc) |= ADC_CR2_CONT; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Single Conversion Mode In this mode the ADC performs a conversion of one channel or a channel group and stops. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_set_single_conversion_mode(u32 adc) @@ -847,7 +908,7 @@ void adc_set_single_conversion_mode(u32 adc) ADC_CR2(adc) &= ~ADC_CR2_CONT; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Power On If the ADC is in power-down mode then it is powered up. The application needs @@ -856,7 +917,8 @@ If the ADC is already on this function call will initiate a conversion. @deprecated to be removed in a later release -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_on(u32 adc) @@ -864,12 +926,13 @@ void adc_on(u32 adc) ADC_CR2(adc) |= ADC_CR2_ADON; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Off Turn off the ADC to reduce power consumption to a few microamps. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. */ void adc_off(u32 adc) @@ -877,13 +940,15 @@ void adc_off(u32 adc) ADC_CR2(adc) &= ~ADC_CR2_ADON; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set the Sample Time for a Single Channel The sampling time can be selected in ADC clock cycles from 1.5 to 239.5. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. -@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref adc_channel. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. +@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref +adc_channel. @param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg. */ @@ -904,13 +969,14 @@ void adc_set_sample_time(u32 adc, u8 channel, u8 time) } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set the Sample Time for All Channels -The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same for -all channels. +The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same +for all channels. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. @param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg. */ @@ -919,19 +985,22 @@ void adc_set_sample_time_on_all_channels(u32 adc, u8 time) u8 i; u32 reg32 = 0; - for (i = 0; i <= 9; i++) + for (i = 0; i <= 9; i++) { reg32 |= (time << (i * 3)); + } ADC_SMPR2(adc) = reg32; - for (i = 10; i <= 17; i++) + for (i = 10; i <= 17; i++) { reg32 |= (time << ((i - 10) * 3)); + } ADC_SMPR1(adc) = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set Analog Watchdog Upper Threshold -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. @param[in] threshold Unsigned int8. Upper threshold value. */ @@ -944,10 +1013,11 @@ void adc_set_watchdog_high_threshold(u32 adc, u16 threshold) ADC_HTR(adc) = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set Analog Watchdog Lower Threshold -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. @param[in] threshold Unsigned int8. Lower threshold value. */ @@ -960,16 +1030,18 @@ void adc_set_watchdog_low_threshold(u32 adc, u16 threshold) ADC_LTR(adc) = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set a Regular Channel Conversion Sequence Define a sequence of channels to be converted as a regular group with a length -from 1 to 16 channels. If this is called during conversion, the current conversion -is reset and conversion begins again with the newly defined group. +from 1 to 16 channels. If this is called during conversion, the current +conversion is reset and conversion begins again with the newly defined group. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. @param[in] length Unsigned int8. Number of channels in the group. -@param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18. +@param[in] channel Unsigned int8[]. Set of channels in sequence, integers +0..18. */ void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]) @@ -978,16 +1050,20 @@ void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]) u8 i = 0; /* Maximum sequence length is 16 channels. */ - if (length > 16) + if (length > 16) { return; + } for (i = 1; i <= length; i++) { - if (i <= 6) + if (i <= 6) { reg32_3 |= (channel[i - 1] << ((i - 1) * 5)); - if ((i > 6) & (i <= 12)) + } + if ((i > 6) & (i <= 12)) { reg32_2 |= (channel[i - 1] << ((i - 6 - 1) * 5)); - if ((i > 12) & (i <= 16)) + } + if ((i > 12) & (i <= 16)) { reg32_1 |= (channel[i - 1] << ((i - 12 - 1) * 5)); + } } reg32_1 |= ((length -1) << ADC_SQR1_L_LSB); @@ -996,14 +1072,15 @@ void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]) ADC_SQR3(adc) = reg32_3; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set an Injected Channel Conversion Sequence -Defines a sequence of channels to be converted as an injected group with a length -from 1 to 4 channels. If this is called during conversion, the current conversion -is reset and conversion begins again with the newly defined group. +Defines a sequence of channels to be converted as an injected group with a +length from 1 to 4 channels. If this is called during conversion, the current +conversion is reset and conversion begins again with the newly defined group. -@param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base. +@param[in] adc Unsigned int32. ADC block register address base @ref +adc_reg_base. @param[in] length Unsigned int8. Number of channels in the group. @param[in] channel Unsigned int8[]. Set of channels in sequence, integers 0..18. */ @@ -1014,27 +1091,34 @@ void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]) u8 i = 0; /* Maximum sequence length is 4 channels. */ - if (length > 4) + if (length > 4) { return; + } - for (i = 1; i <= length; i++) + for (i = 1; i <= length; i++) { reg32 |= (channel[4 - i] << ((4 - i) * 5)); + } reg32 |= ((length - 1) << ADC_JSQR_JL_LSB); ADC_JSQR(adc) = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /* Aliases */ #ifdef __GNUC__ -void adc_set_continous_conversion_mode(u32 adc) __attribute__ ((alias("adc_set_continuous_conversion_mode"))); -void adc_set_conversion_time(u32 adc, u8 channel, u8 time) __attribute__ ((alias ("adc_set_sample_time"))); -void adc_set_conversion_time_on_all_channels(u32 adc, u8 time) __attribute__ ((alias ("adc_set_sample_time_on_all_channels"))); -void adc_enable_jeoc_interrupt(u32 adc) __attribute__ ((alias ("adc_enable_eoc_interrupt_injected"))); -void adc_disable_jeoc_interrupt(u32 adc) __attribute__ ((alias ("adc_disable_eoc_interrupt_injected"))); +void adc_set_continous_conversion_mode(u32 adc) + __attribute__((alias("adc_set_continuous_conversion_mode"))); +void adc_set_conversion_time(u32 adc, u8 channel, u8 time) + __attribute__((alias("adc_set_sample_time"))); +void adc_set_conversion_time_on_all_channels(u32 adc, u8 time) + __attribute__((alias("adc_set_sample_time_on_all_channels"))); +void adc_enable_jeoc_interrupt(u32 adc) + __attribute__((alias("adc_enable_eoc_interrupt_injected"))); +void adc_disable_jeoc_interrupt(u32 adc) + __attribute__((alias("adc_disable_eoc_interrupt_injected"))); #endif /**@}*/ diff --git a/lib/stm32/f1/crc.c b/lib/stm32/f1/crc.c index 8c880522..49e7ff70 100644 --- a/lib/stm32/f1/crc.c +++ b/lib/stm32/f1/crc.c @@ -31,4 +31,3 @@ LGPL License Terms @ref lgpl_license #include #include - diff --git a/lib/stm32/f1/flash.c b/lib/stm32/f1/flash.c index 5e29dc88..30365a76 100644 --- a/lib/stm32/f1/flash.c +++ b/lib/stm32/f1/flash.c @@ -95,7 +95,10 @@ void flash_clear_status_flags(void) u32 flash_get_status_flags(void) { - return (FLASH_SR &= (FLASH_SR_PGERR | FLASH_SR_EOP | FLASH_SR_WRPRTERR | FLASH_SR_BSY)); + return FLASH_SR &= (FLASH_SR_PGERR | + FLASH_SR_EOP | + FLASH_SR_WRPRTERR | + FLASH_SR_BSY); } void flash_unlock_option_bytes(void) @@ -174,8 +177,9 @@ void flash_erase_option_bytes(void) { flash_wait_for_last_operation(); - if ((FLASH_CR & FLASH_CR_OPTWRE) == 0) + if ((FLASH_CR & FLASH_CR_OPTWRE) == 0) { flash_unlock_option_bytes(); + } FLASH_CR |= FLASH_CR_OPTER; /* Enable option byte erase. */ FLASH_CR |= FLASH_CR_STRT; @@ -187,8 +191,9 @@ void flash_program_option_bytes(u32 address, u16 data) { flash_wait_for_last_operation(); - if ((FLASH_CR & FLASH_CR_OPTWRE) == 0) + if ((FLASH_CR & FLASH_CR_OPTWRE) == 0) { flash_unlock_option_bytes(); + } FLASH_CR |= FLASH_CR_OPTPG; /* Enable option byte programming. */ (*(volatile u16 *)address) = data; diff --git a/lib/stm32/f1/gpio.c b/lib/stm32/f1/gpio.c index 0cc4f5e0..ccb2e95e 100644 --- a/lib/stm32/f1/gpio.c +++ b/lib/stm32/f1/gpio.c @@ -6,23 +6,25 @@ @version 1.0.0 -@author @htmlonly © @endhtmlonly 2009 Uwe Hermann -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies +@author @htmlonly © @endhtmlonly 2009 +Uwe Hermann +@author @htmlonly © @endhtmlonly 2012 +Ken Sarkies @date 18 August 2012 Each I/O port has 16 individually configurable bits. Many I/O pins share GPIO -functionality with a number of alternate functions and must be configured to the -alternate function mode if these are to be accessed. A feature is available to -remap alternative functions to a limited set of alternative pins in the event -of a clash of requirements. +functionality with a number of alternate functions and must be configured to +the alternate function mode if these are to be accessed. A feature is available +to remap alternative functions to a limited set of alternative pins in the +event of a clash of requirements. -The data registers associated with each port for input and output are 32 bit with -the upper 16 bits unused. The output buffer must be written as a 32 bit word, but -individual bits may be set or reset separately in atomic operations to avoid race -conditions during interrupts. Bits may also be individually locked to prevent -accidental configuration changes. Once locked the configuration cannot be changed -until after the next reset. +The data registers associated with each port for input and output are 32 bit +with the upper 16 bits unused. The output buffer must be written as a 32 bit +word, but individual bits may be set or reset separately in atomic operations +to avoid race conditions during interrupts. Bits may also be individually +locked to prevent accidental configuration changes. Once locked the +configuration cannot be changed until after the next reset. Each port bit can be configured as analog or digital input, the latter can be floating or pulled up or down. As outputs they can be configured as either @@ -76,7 +78,7 @@ LGPL License Terms @ref lgpl_license /**@{*/ -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Set GPIO Pin Mode Sets the mode (input/output) and configuration (analog/digitial and @@ -86,7 +88,8 @@ open drain/push pull), for a set of GPIO pins on a given GPIO port. @param[in] mode Unsigned int8. Pin mode @ref gpio_mode @param[in] cnf Unsigned int8. Pin configuration @ref gpio_cnf @param[in] gpios Unsigned int16. Pin identifiers @ref gpio_pin_id - If multiple pins are to be set, use logical OR '|' to separate them. + If multiple pins are to be set, use logical OR '|' to separate + them. */ void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios) @@ -104,8 +107,9 @@ void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios) /* Iterate over all bits, use i as the bitnumber. */ for (i = 0; i < 16; i++) { /* Only set the config if the bit is set in gpios. */ - if (!((1 << i) & gpios)) + if (!((1 << i) & gpios)) { continue; + } /* Calculate bit offset. */ offset = (i < 8) ? (i * 4) : ((i - 8) * 4); @@ -126,7 +130,7 @@ void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios) GPIO_CRH(gpioport) = crh; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Map the EVENTOUT signal Enable the EVENTOUT signal and select the port and pin to be used. @@ -139,45 +143,47 @@ void gpio_set_eventout(u8 evoutport, u8 evoutpin) AFIO_EVCR = AFIO_EVCR_EVOE | evoutport | evoutpin; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Map Alternate Function Port Bits (Main Set) A number of alternate function ports can be remapped to defined alternative -port bits to avoid clashes in cases where multiple alternate functions are present. -Refer to the datasheets for the particular mapping desired. This provides the main -set of remap functionality. See @ref gpio_secondary_remap for a number of lesser used -remaps. +port bits to avoid clashes in cases where multiple alternate functions are +present. Refer to the datasheets for the particular mapping desired. This +provides the main set of remap functionality. See @ref gpio_secondary_remap for +a number of lesser used remaps. The AFIO remapping feature is used only with the STM32F10x series. -@note The Serial Wire JTAG disable controls allow certain GPIO ports to become available -in place of some of the SWJ signals. Full SWJ capability is obtained by setting this to -zero. The value of this must be specified for every call to this function as its current -value cannot be ascertained from the hardware. +@note The Serial Wire JTAG disable controls allow certain GPIO ports to become +available in place of some of the SWJ signals. Full SWJ capability is obtained +by setting this to zero. The value of this must be specified for every call to +this function as its current value cannot be ascertained from the hardware. -@param[in] swjdisable Unsigned int8. Disable parts of the SWJ capability @ref afio_swj_disable. -@param[in] maps Unsigned int32. Logical OR of map enable controls from @ref afio_remap, - @ref afio_remap_can1, @ref afio_remap_tim3, @ref afio_remap_tim2, @ref afio_remap_tim1, - @ref afio_remap_usart3. For connectivity line devices only @ref afio_remap_cld are - also available. +@param[in] swjdisable Unsigned int8. Disable parts of the SWJ capability @ref +afio_swj_disable. +@param[in] maps Unsigned int32. Logical OR of map enable controls from @ref +afio_remap, @ref afio_remap_can1, @ref afio_remap_tim3, @ref afio_remap_tim2, +@ref afio_remap_tim1, @ref afio_remap_usart3. For connectivity line devices +only @ref afio_remap_cld are also available. */ void gpio_primary_remap(u32 swjdisable, u32 maps) { AFIO_MAPR |= (swjdisable & AFIO_MAPR_SWJ_MASK) | (maps & 0x1FFFFF); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief Map Alternate Function Port Bits (Secondary Set) A number of alternate function ports can be remapped to defined alternative -port bits to avoid clashes in cases where multiple alternate functions are present. -Refer to the datasheets for the particular mapping desired. This provides the second -smaller and less used set of remap functionality. See @ref gpio_primary_remap for -the main set of remaps. +port bits to avoid clashes in cases where multiple alternate functions are +present. Refer to the datasheets for the particular mapping desired. This +provides the second smaller and less used set of remap functionality. See @ref +gpio_primary_remap for the main set of remaps. The AFIO remapping feature is used only with the STM32F10x series. -@param[in] maps Unsigned int32. Logical OR of map enable controls from @ref afio_remap2 +@param[in] maps Unsigned int32. Logical OR of map enable controls from @ref +afio_remap2 */ void gpio_secondary_remap(u32 maps) { diff --git a/lib/stm32/f1/pwr.c b/lib/stm32/f1/pwr.c index 8e59bab1..082612a8 100644 --- a/lib/stm32/f1/pwr.c +++ b/lib/stm32/f1/pwr.c @@ -6,7 +6,8 @@ @version 1.0.0 -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies +@author @htmlonly © @endhtmlonly 2012 +Ken Sarkies @date 18 August 2012 diff --git a/lib/stm32/f1/rcc.c b/lib/stm32/f1/rcc.c index 707c931d..35c40f6d 100644 --- a/lib/stm32/f1/rcc.c +++ b/lib/stm32/f1/rcc.c @@ -6,7 +6,8 @@ @version 1.0.0 -@author @htmlonly © @endhtmlonly 2009 Federico Ruiz-Ugalde \ +@author @htmlonly © @endhtmlonly 2009 +Federico Ruiz-Ugalde \ @author @htmlonly © @endhtmlonly 2009 Uwe Hermann @author @htmlonly © @endhtmlonly 2010 Thomas Otto @@ -17,8 +18,8 @@ series of ARM Cortex Microcontrollers by ST Microelectronics. @note Full support for connection line devices is not yet provided. -Clock settings and resets for many peripherals are given here rather than in the -corresponding peripheral library. +Clock settings and resets for many peripherals are given here rather than in +the corresponding peripheral library. The library also provides a number of common configurations for the processor system clock. Not all possible configurations are included. @@ -57,10 +58,11 @@ u32 rcc_ppre1_frequency = 8000000; /** Default ppre2 peripheral clock frequency after reset. */ u32 rcc_ppre2_frequency = 8000000; -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Clear the Oscillator Ready Interrupt Flag -Clear the interrupt flag that was set when a clock oscillator became ready to use. +Clear the interrupt flag that was set when a clock oscillator became ready to +use. @param[in] osc enum ::osc_t. Oscillator ID */ @@ -92,7 +94,7 @@ void rcc_osc_ready_int_clear(osc_t osc) } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Enable the Oscillator Ready Interrupt @param[in] osc enum ::osc_t. Oscillator ID @@ -125,7 +127,7 @@ void rcc_osc_ready_int_enable(osc_t osc) } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Disable the Oscillator Ready Interrupt @param[in] osc enum ::osc_t. Oscillator ID @@ -158,7 +160,7 @@ void rcc_osc_ready_int_disable(osc_t osc) } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Read the Oscillator Ready Interrupt Flag @param[in] osc enum ::osc_t. Oscillator ID @@ -194,7 +196,7 @@ int rcc_osc_ready_int_flag(osc_t osc) cm3_assert_not_reached(); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Clear the Clock Security System Interrupt Flag */ @@ -204,7 +206,7 @@ void rcc_css_int_clear(void) RCC_CIR |= RCC_CIR_CSSC; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Read the Clock Security System Interrupt Flag @returns int. Boolean value for flag set. @@ -215,7 +217,7 @@ int rcc_css_int_flag(void) return ((RCC_CIR & RCC_CIR_CSSF) != 0); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Wait for Oscillator Ready. @param[in] osc enum ::osc_t. Oscillator ID @@ -248,16 +250,17 @@ void rcc_wait_for_osc_ready(osc_t osc) } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Turn on an Oscillator. -Enable an oscillator and power on. Each oscillator requires an amount of time to -settle to a usable state. Refer to datasheets for time delay information. A status -flag is available to indicate when the oscillator becomes ready (see +Enable an oscillator and power on. Each oscillator requires an amount of time +to settle to a usable state. Refer to datasheets for time delay information. A +status flag is available to indicate when the oscillator becomes ready (see @ref rcc_osc_ready_int_flag and @ref rcc_wait_for_osc_ready). @note The LSE clock is in the backup domain and cannot be enabled until the -backup domain write protection has been removed (see @ref pwr_disable_backup_domain_write_protect). +backup domain write protection has been removed (see @ref +pwr_disable_backup_domain_write_protect). @param[in] osc enum ::osc_t. Oscillator ID */ @@ -289,7 +292,7 @@ void rcc_osc_on(osc_t osc) } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Turn off an Oscillator. Disable an oscillator and power off. @@ -330,7 +333,7 @@ void rcc_osc_off(osc_t osc) } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Enable the Clock Security System. */ @@ -340,7 +343,7 @@ void rcc_css_enable(void) RCC_CR |= RCC_CR_CSSON; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Disable the Clock Security System. */ @@ -350,15 +353,16 @@ void rcc_css_disable(void) RCC_CR &= ~RCC_CR_CSSON; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Enable Bypass. Enable an external clock to bypass the internal clock (high speed and low speed -clocks only). The external clock must be enabled (see @ref rcc_osc_on) -and the internal clock must be disabled (see @ref rcc_osc_off) for this to have effect. +clocks only). The external clock must be enabled (see @ref rcc_osc_on) and the +internal clock must be disabled (see @ref rcc_osc_off) for this to have effect. @note The LSE clock is in the backup domain and cannot be bypassed until the -backup domain write protection has been removed (see @ref pwr_disable_backup_domain_write_protect). +backup domain write protection has been removed (see @ref +pwr_disable_backup_domain_write_protect). @param[in] osc enum ::osc_t. Oscillator ID. Only HSE and LSE have effect. */ @@ -382,15 +386,16 @@ void rcc_osc_bypass_enable(osc_t osc) } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Disable Bypass. -Re-enable the internal clock (high speed and low speed clocks only). The internal -clock must be disabled (see @ref rcc_osc_off) for this to have effect. +Re-enable the internal clock (high speed and low speed clocks only). The +internal clock must be disabled (see @ref rcc_osc_off) for this to have effect. -@note The LSE clock is in the backup domain and cannot have bypass removed until the -backup domain write protection has been removed (see @ref pwr_disable_backup_domain_write_protect) -or the backup domain has been reset (see @ref rcc_backupdomain_reset). +@note The LSE clock is in the backup domain and cannot have bypass removed +until the backup domain write protection has been removed (see @ref +pwr_disable_backup_domain_write_protect) or the backup domain has been reset +(see @ref rcc_backupdomain_reset). @param[in] osc enum ::osc_t. Oscillator ID. Only HSE and LSE have effect. */ @@ -414,13 +419,13 @@ void rcc_osc_bypass_disable(osc_t osc) } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Enable Peripheral Clocks. -Enable the clock on particular peripherals. There are three registers -involved, each one controlling the enabling of clocks associated with the AHB, -APB1 and APB2 respectively. Several peripherals could be -enabled simultaneously only if they are controlled by the same register. +Enable the clock on particular peripherals. There are three registers involved, +each one controlling the enabling of clocks associated with the AHB, APB1 and +APB2 respectively. Several peripherals could be enabled simultaneously only +if they are controlled by the same register. @param[in] *reg Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR) @@ -435,17 +440,18 @@ void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en) *reg |= en; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Disable Peripheral Clocks. -Enable the clock on particular peripherals. There are three registers -involved, each one controlling the enabling of clocks associated with the AHB, -APB1 and APB2 respectively. Several peripherals could be -disabled simultaneously only if they are controlled by the same register. +Enable the clock on particular peripherals. There are three registers involved, +each one controlling the enabling of clocks associated with the AHB, APB1 and +APB2 respectively. Several peripherals could be disabled simultaneously +only if they are controlled by the same register. @param[in] *reg Unsigned int32. Pointer to a Clock Enable Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR) -@param[in] en Unsigned int32. Logical OR of all enables to be used for disabling. +@param[in] en Unsigned int32. Logical OR of all enables to be used for +disabling. @li If register is RCC_AHBER, from @ref rcc_ahbenr_en @li If register is RCC_APB1ENR, from @ref rcc_apb1enr_en @li If register is RCC_APB2ENR, from @ref rcc_apb2enr_en @@ -456,13 +462,13 @@ void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en) *reg &= ~en; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Reset Peripherals. -Reset particular peripherals. There are three registers -involved, each one controlling reset of peripherals associated with the AHB, -APB1 and APB2 respectively. Several peripherals could be reset simultaneously -only if they are controlled by the same register. +Reset particular peripherals. There are three registers involved, each one +controlling reset of peripherals associated with the AHB, APB1 and APB2 +respectively. Several peripherals could be reset simultaneously only if +they are controlled by the same register. @param[in] *reg Unsigned int32. Pointer to a Reset Register (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR) @@ -477,7 +483,7 @@ void rcc_peripheral_reset(volatile u32 *reg, u32 reset) *reg |= reset; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Remove Reset on Peripherals. Remove the reset on particular peripherals. There are three registers @@ -498,7 +504,7 @@ void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset) *reg &= ~clear_reset; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Set the Source for the System Clock. @param[in] clk Unsigned int32. System Clock Selection @ref rcc_cfgr_scs @@ -513,7 +519,7 @@ void rcc_set_sysclk_source(u32 clk) RCC_CFGR = (reg32 | clk); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Set the PLL Multiplication Factor. @note This only has effect when the PLL is disabled. @@ -530,7 +536,7 @@ void rcc_set_pll_multiplication_factor(u32 mul) RCC_CFGR = (reg32 | (mul << 18)); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Set the PLL2 Multiplication Factor. @note This only has effect when the PLL is disabled. @@ -547,7 +553,7 @@ void rcc_set_pll2_multiplication_factor(u32 mul) RCC_CFGR2 = (reg32 | (mul << 8)); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Set the PLL3 Multiplication Factor. @note This only has effect when the PLL is disabled. @@ -564,7 +570,7 @@ void rcc_set_pll3_multiplication_factor(u32 mul) RCC_CFGR2 = (reg32 | (mul << 12)); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Set the PLL Clock Source. @note This only has effect when the PLL is disabled. @@ -581,7 +587,7 @@ void rcc_set_pll_source(u32 pllsrc) RCC_CFGR = (reg32 | (pllsrc << 16)); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Set the HSE Frequency Divider used as PLL Clock Source. @note This only has effect when the PLL is disabled. @@ -598,7 +604,7 @@ void rcc_set_pllxtpre(u32 pllxtpre) RCC_CFGR = (reg32 | (pllxtpre << 17)); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Setup the A/D Clock The ADC's have a common clock prescale setting. @@ -615,7 +621,7 @@ void rcc_set_adcpre(u32 adcpre) RCC_CFGR = (reg32 | (adcpre << 14)); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Set the APB2 Prescale Factor. @param[in] ppre2 Unsigned int32. APB2 prescale factor @ref rcc_cfgr_apb2pre @@ -630,7 +636,7 @@ void rcc_set_ppre2(u32 ppre2) RCC_CFGR = (reg32 | (ppre2 << 11)); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Set the APB1 Prescale Factor. @note The APB1 clock frequency must not exceed 36MHz. @@ -647,7 +653,7 @@ void rcc_set_ppre1(u32 ppre1) RCC_CFGR = (reg32 | (ppre1 << 8)); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Set the AHB Prescale Factor. @param[in] hpre Unsigned int32. AHB prescale factor @ref rcc_cfgr_ahbpre @@ -662,7 +668,7 @@ void rcc_set_hpre(u32 hpre) RCC_CFGR = (reg32 | (hpre << 4)); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Set the USB Prescale Factor. The prescale factor can be set to 1 (no prescale) for use when the PLL clock is @@ -712,7 +718,7 @@ void rcc_set_mco(u32 mcosrc) RCC_CFGR |= (reg32 | (mcosrc << 24)); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Get the System Clock Source. @returns Unsigned int32. System clock source: @@ -724,15 +730,15 @@ void rcc_set_mco(u32 mcosrc) u32 rcc_system_clock_source(void) { /* Return the clock source which is used as system clock. */ - return ((RCC_CFGR & 0x000c) >> 2); + return (RCC_CFGR & 0x000c) >> 2; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /* * These functions are setting up the whole clock system for the most common * input clock and output clock configurations. */ -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Set System Clock PLL at 64MHz from HSI */ @@ -750,10 +756,10 @@ void rcc_clock_setup_in_hsi_out_64mhz(void) * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ - rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 64MHz Max. 72MHz */ - rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 8MHz Max. 14MHz */ - rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 32MHz Max. 36MHz */ - rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 64MHz Max. 72MHz */ + rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 64MHz Max. 72MHz */ + rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 8MHz Max. 14MHz */ + rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 32MHz Max. 36MHz */ + rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 64MHz Max. 72MHz */ /* * Sysclk is running with 64MHz -> 2 waitstates. @@ -784,7 +790,7 @@ void rcc_clock_setup_in_hsi_out_64mhz(void) rcc_ppre2_frequency = 64000000; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Set System Clock PLL at 48MHz from HSI */ @@ -802,11 +808,11 @@ void rcc_clock_setup_in_hsi_out_48mhz(void) * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ - rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 48MHz Max. 72MHz */ - rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 6MHz Max. 14MHz */ - rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 24MHz Max. 36MHz */ - rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 48MHz Max. 72MHz */ - rcc_set_usbpre(RCC_CFGR_USBPRE_PLL_CLK_NODIV); /* Set. 48MHz Max. 48MHz */ + rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /*Set.48MHz Max.72MHz */ + rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /*Set. 6MHz Max.14MHz */ + rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /*Set.24MHz Max.36MHz */ + rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /*Set.48MHz Max.72MHz */ + rcc_set_usbpre(RCC_CFGR_USBPRE_PLL_CLK_NODIV); /*Set.48MHz Max.48MHz */ /* * Sysclk runs with 48MHz -> 1 waitstates. @@ -837,12 +843,13 @@ void rcc_clock_setup_in_hsi_out_48mhz(void) rcc_ppre2_frequency = 48000000; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Set System Clock PLL at 24MHz from HSI */ -void rcc_clock_setup_in_hsi_out_24mhz(void) { +void rcc_clock_setup_in_hsi_out_24mhz(void) +{ /* Enable internal high-speed oscillator. */ rcc_osc_on(HSI); rcc_wait_for_osc_ready(HSI); @@ -888,7 +895,7 @@ void rcc_clock_setup_in_hsi_out_24mhz(void) { rcc_ppre2_frequency = 24000000; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Set System Clock PLL at 24MHz from HSE at 8MHz */ @@ -911,10 +918,10 @@ void rcc_clock_setup_in_hse_8mhz_out_24mhz(void) * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ - rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 24MHz Max. 72MHz */ - rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2); /* Set. 12MHz Max. 14MHz */ - rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_NODIV); /* Set. 24MHz Max. 36MHz */ - rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 24MHz Max. 72MHz */ + rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 24MHz Max. 72MHz */ + rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV2); /* Set. 12MHz Max. 14MHz */ + rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_NODIV); /* Set. 24MHz Max. 36MHz */ + rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 24MHz Max. 72MHz */ /* * Sysclk runs with 24MHz -> 0 waitstates. @@ -951,7 +958,7 @@ void rcc_clock_setup_in_hse_8mhz_out_24mhz(void) rcc_ppre2_frequency = 24000000; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Set System Clock PLL at 72MHz from HSE at 8MHz */ @@ -974,10 +981,10 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void) * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ - rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ - rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 9MHz Max. 14MHz */ - rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ - rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ + rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ + rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV8); /* Set. 9MHz Max. 14MHz */ + rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ + rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ /* * Sysclk runs with 72MHz -> 2 waitstates. @@ -1014,7 +1021,7 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void) rcc_ppre2_frequency = 72000000; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Set System Clock PLL at 24MHz from HSE at 12MHz */ @@ -1037,10 +1044,10 @@ void rcc_clock_setup_in_hse_12mhz_out_72mhz(void) * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ - rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ - rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */ - rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ - rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ + rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ + rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */ + rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ + rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ /* * Sysclk runs with 72MHz -> 2 waitstates. @@ -1077,7 +1084,7 @@ void rcc_clock_setup_in_hse_12mhz_out_72mhz(void) rcc_ppre2_frequency = 72000000; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Set System Clock PLL at 24MHz from HSE at 16MHz */ @@ -1100,10 +1107,10 @@ void rcc_clock_setup_in_hse_16mhz_out_72mhz(void) * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ - rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ - rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */ - rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ - rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ + rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ + rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */ + rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ + rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ /* * Sysclk runs with 72MHz -> 2 waitstates. @@ -1140,7 +1147,7 @@ void rcc_clock_setup_in_hse_16mhz_out_72mhz(void) rcc_ppre2_frequency = 72000000; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Set System Clock PLL at 72MHz from HSE at 25MHz */ @@ -1164,10 +1171,10 @@ void rcc_clock_setup_in_hse_25mhz_out_72mhz(void) * Set prescalers for AHB, ADC, ABP1, ABP2. * Do this before touching the PLL (TODO: why?). */ - rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ - rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */ - rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ - rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ + rcc_set_hpre(RCC_CFGR_HPRE_SYSCLK_NODIV); /* Set. 72MHz Max. 72MHz */ + rcc_set_adcpre(RCC_CFGR_ADCPRE_PCLK2_DIV6); /* Set. 12MHz Max. 14MHz */ + rcc_set_ppre1(RCC_CFGR_PPRE1_HCLK_DIV2); /* Set. 36MHz Max. 36MHz */ + rcc_set_ppre2(RCC_CFGR_PPRE2_HCLK_NODIV); /* Set. 72MHz Max. 72MHz */ /* Set pll2 prediv and multiplier */ rcc_set_prediv2(RCC_CFGR2_PREDIV2_DIV5); @@ -1197,7 +1204,7 @@ void rcc_clock_setup_in_hse_25mhz_out_72mhz(void) rcc_ppre2_frequency = 72000000; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief RCC Reset the backup domain The backup domain register is reset to disable all controls. diff --git a/lib/stm32/f1/rtc.c b/lib/stm32/f1/rtc.c index 24b19ce3..a7affe9e 100644 --- a/lib/stm32/f1/rtc.c +++ b/lib/stm32/f1/rtc.c @@ -290,7 +290,9 @@ void rtc_auto_awake(osc_t clock_source, u32 prescale_val) /* TODO: Not sure if this is necessary to just read the flag. */ PWR_CR |= PWR_CR_DBP; - if ((reg32 = RCC_BDCR & RCC_BDCR_RTCEN) != 0) { + reg32 = RCC_BDCR & RCC_BDCR_RTCEN; + + if (reg32 != 0) { rtc_awake_from_standby(); } else { rtc_awake_from_off(clock_source); diff --git a/lib/stm32/f1/timer.c b/lib/stm32/f1/timer.c index a1035a9d..f63c9f05 100644 --- a/lib/stm32/f1/timer.c +++ b/lib/stm32/f1/timer.c @@ -46,11 +46,13 @@ in which case this file must be added to the compile list. */ @param[in] pol ::tim_ic_pol. Input Capture polarity. */ -void timer_ic_set_polarity(u32 timer_peripheral, enum tim_ic_id ic, enum tim_ic_pol pol) +void timer_ic_set_polarity(u32 timer_peripheral, enum tim_ic_id ic, + enum tim_ic_pol pol) { - if (pol) + if (pol) { TIM_CCER(timer_peripheral) |= (0x2 << (ic * 4)); - else + } else { TIM_CCER(timer_peripheral) &= ~(0x2 << (ic * 4)); + } } diff --git a/lib/stm32/f2/rcc.c b/lib/stm32/f2/rcc.c index d60c2325..a34ce57f 100644 --- a/lib/stm32/f2/rcc.c +++ b/lib/stm32/f2/rcc.c @@ -27,8 +27,7 @@ u32 rcc_ppre1_frequency = 16000000; u32 rcc_ppre2_frequency = 16000000; -const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] = -{ +const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] = { { /* 120MHz */ .pllm = 8, .plln = 240, @@ -37,7 +36,8 @@ const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] = .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS, + .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + FLASH_ACR_LATENCY_3WS, .apb1_frequency = 30000000, .apb2_frequency = 60000000, }, @@ -358,7 +358,7 @@ void rcc_set_main_pll_hse(u32 pllm, u32 plln, u32 pllp, u32 pllq) u32 rcc_system_clock_source(void) { /* Return the clock source which is used as system clock. */ - return ((RCC_CFGR & 0x000c) >> 2); + return (RCC_CFGR & 0x000c) >> 2; } void rcc_clock_setup_hse_3v3(const clock_scale_t *clock) diff --git a/lib/stm32/f4/adc.c b/lib/stm32/f4/adc.c index 00edcc35..59993c67 100644 --- a/lib/stm32/f4/adc.c +++ b/lib/stm32/f4/adc.c @@ -4,44 +4,46 @@ @brief libopencm3 STM32F4xx Analog to Digital Converters -@author @htmlonly © @endhtmlonly 2012 Ken Sarkies +@author @htmlonly © @endhtmlonly 2012 +Ken Sarkies @date 30 August 2012 This library supports the A/D Converter Control System in the STM32 series of ARM Cortex Microcontrollers by ST Microelectronics. -Devices can have up to three A/D converters each with their own set of registers. -However all the A/D converters share a common clock which is prescaled from the APB2 -clock by default by a minimum factor of 2 to a maximum of 8. The ADC resolution -can be set to 12, 10, 8 or 6 bits. +Devices can have up to three A/D converters each with their own set of +registers. However all the A/D converters share a common clock which is +prescaled from the APB2 clock by default by a minimum factor of 2 to a maximum +of 8. The ADC resolution can be set to 12, 10, 8 or 6 bits. Each A/D converter has up to 19 channels: @li On ADC1 the analog channels 16 is internally connected to the temperature sensor, channel 17 to VREFINT, and channel 18 to VBATT. @li On ADC2 and ADC3 the analog channels 16 - 18 are not used. -The conversions can occur as a one-off conversion whereby the process stops once -conversion is complete. The conversions can also be continuous wherein a new -conversion starts immediately the previous conversion has ended. +The conversions can occur as a one-off conversion whereby the process stops +once conversion is complete. The conversions can also be continuous wherein a +new conversion starts immediately the previous conversion has ended. Conversion can occur as a single channel conversion or a scan of a group of -channels in either continuous or one-off mode. If more than one channel is converted -in a scan group, DMA must be used to transfer the data as there is only one -result register available. An interrupt can be set to occur at the end of -conversion, which occurs after all channels have been scanned. +channels in either continuous or one-off mode. If more than one channel is +converted in a scan group, DMA must be used to transfer the data as there is +only one result register available. An interrupt can be set to occur at the end +of conversion, which occurs after all channels have been scanned. -A discontinuous mode allows a subgroup of group of a channels to be converted in -bursts of a given length. +A discontinuous mode allows a subgroup of group of a channels to be converted +in bursts of a given length. -Injected conversions allow a second group of channels to be converted separately -from the regular group. An interrupt can be set to occur at the end of -conversion, which occurs after all channels have been scanned. +Injected conversions allow a second group of channels to be converted +separately from the regular group. An interrupt can be set to occur at the end +of conversion, which occurs after all channels have been scanned. @section adc_f4_api_ex Basic ADC Handling API. Example 1: Simple single channel conversion polled. Enable the peripheral clock -and ADC, reset ADC and set the prescaler divider. Set multiple mode to independent. +and ADC, reset ADC and set the prescaler divider. Set multiple mode to +independent. @code gpio_mode_setup(GPIOA, GPIO_MODE_ANALOG, GPIO_PUPD_NONE, GPIO1); @@ -84,7 +86,7 @@ LGPL License Terms @ref lgpl_license /**@{*/ -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Off Turn off the ADC to reduce power consumption to a few microamps. @@ -97,12 +99,12 @@ void adc_off(u32 adc) ADC_CR2(adc) &= ~ADC_CR2_ADON; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for Regular Conversions -The analog watchdog allows the monitoring of an analog signal between two threshold -levels. The thresholds must be preset. Comparison is done before data alignment -takes place, so the thresholds are left-aligned. +The analog watchdog allows the monitoring of an analog signal between two +threshold levels. The thresholds must be preset. Comparison is done before data +alignment takes place, so the thresholds are left-aligned. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ @@ -112,7 +114,7 @@ void adc_enable_analog_watchdog_regular(u32 adc) ADC_CR1(adc) |= ADC_CR1_AWDEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable Analog Watchdog for Regular Conversions @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -123,12 +125,12 @@ void adc_disable_analog_watchdog_regular(u32 adc) ADC_CR1(adc) &= ~ADC_CR1_AWDEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for Injected Conversions -The analog watchdog allows the monitoring of an analog signal between two threshold -levels. The thresholds must be preset. Comparison is done before data alignment -takes place, so the thresholds are left-aligned. +The analog watchdog allows the monitoring of an analog signal between two +threshold levels. The thresholds must be preset. Comparison is done before data +alignment takes place, so the thresholds are left-aligned. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ @@ -138,7 +140,7 @@ void adc_enable_analog_watchdog_injected(u32 adc) ADC_CR1(adc) |= ADC_CR1_JAWDEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable Analog Watchdog for Injected Conversions @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -149,7 +151,7 @@ void adc_disable_analog_watchdog_injected(u32 adc) ADC_CR1(adc) &= ~ADC_CR1_JAWDEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Discontinuous Mode for Regular Conversions In this mode the ADC converts, on each trigger, a subgroup of up to 8 of the @@ -161,17 +163,20 @@ the whole group has been converted, the next trigger will restart conversion of the subgroup at the beginning of the whole group. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] length Unsigned int8. Number of channels in the group @ref adc_cr1_discnum +@param[in] length Unsigned int8. Number of channels in the group @ref +adc_cr1_discnum */ void adc_enable_discontinuous_mode_regular(u32 adc, u8 length) { - if ( (length-1) > 7 ) return; - ADC_CR1(adc) |= ADC_CR1_DISCEN; - ADC_CR1(adc) |= ((length-1) << ADC_CR1_DISCNUM_SHIFT); + if ((length-1) > 7) { + return; + } + ADC_CR1(adc) |= ADC_CR1_DISCEN; + ADC_CR1(adc) |= ((length-1) << ADC_CR1_DISCNUM_SHIFT); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable Discontinuous Mode for Regular Conversions @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -182,7 +187,7 @@ void adc_disable_discontinuous_mode_regular(u32 adc) ADC_CR1(adc) &= ~ADC_CR1_DISCEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Discontinuous Mode for Injected Conversions In this mode the ADC converts sequentially one channel of the defined group of @@ -197,7 +202,7 @@ void adc_enable_discontinuous_mode_injected(u32 adc) ADC_CR1(adc) |= ADC_CR1_JDISCEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable Discontinuous Mode for Injected Conversions @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -208,7 +213,7 @@ void adc_disable_discontinuous_mode_injected(u32 adc) ADC_CR1(adc) &= ~ADC_CR1_JDISCEN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Automatic Injected Conversions The ADC converts a defined injected group of channels immediately after the @@ -220,11 +225,11 @@ channels is disabled as required. void adc_enable_automatic_injected_group_conversion(u32 adc) { - adc_disable_external_trigger_injected(adc); + adc_disable_external_trigger_injected(adc); ADC_CR1(adc) |= ADC_CR1_JAUTO; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable Automatic Injected Conversions @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -235,17 +240,18 @@ void adc_disable_automatic_injected_group_conversion(u32 adc) ADC_CR1(adc) &= ~ADC_CR1_JAUTO; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for All Regular and/or Injected Channels -The analog watchdog allows the monitoring of an analog signal between two threshold -levels. The thresholds must be preset. Comparison is done before data alignment -takes place, so the thresholds are left-aligned. +The analog watchdog allows the monitoring of an analog signal between two +threshold levels. The thresholds must be preset. Comparison is done before data +alignment takes place, so the thresholds are left-aligned. @note The analog watchdog must be enabled for either or both of the regular or injected channels. If neither are enabled, the analog watchdog feature will be disabled. -@ref adc_enable_analog_watchdog_injected, @ref adc_enable_analog_watchdog_regular. +@ref adc_enable_analog_watchdog_injected, @ref +adc_enable_analog_watchdog_regular. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ @@ -255,17 +261,18 @@ void adc_enable_analog_watchdog_on_all_channels(u32 adc) ADC_CR1(adc) &= ~ADC_CR1_AWDSGL; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog for a Selected Channel -The analog watchdog allows the monitoring of an analog signal between two threshold -levels. The thresholds must be preset. Comparison is done before data alignment -takes place, so the thresholds are left-aligned. +The analog watchdog allows the monitoring of an analog signal between two +threshold levels. The thresholds must be preset. Comparison is done before data +alignment takes place, so the thresholds are left-aligned. @note The analog watchdog must be enabled for either or both of the regular or injected channels. If neither are enabled, the analog watchdog feature will be disabled. If both are enabled, the same channel number is monitored. -@ref adc_enable_analog_watchdog_injected, @ref adc_enable_analog_watchdog_regular. +@ref adc_enable_analog_watchdog_injected, @ref +adc_enable_analog_watchdog_regular. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @param[in] channel Unsigned int8. ADC channel number @ref adc_watchdog_channel @@ -276,13 +283,14 @@ void adc_enable_analog_watchdog_on_selected_channel(u32 adc, u8 channel) u32 reg32; reg32 = (ADC_CR1(adc) & ~ADC_CR1_AWDCH_MASK); /* Clear bits [4:0]. */ - if (channel < 18) + if (channel < 18) { reg32 |= channel; + } ADC_CR1(adc) = reg32; ADC_CR1(adc) |= ADC_CR1_AWDSGL; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set Scan Mode In this mode a conversion consists of a scan of the predefined set of channels, @@ -297,7 +305,7 @@ void adc_enable_scan_mode(u32 adc) ADC_CR1(adc) |= ADC_CR1_SCAN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable Scan Mode @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -308,7 +316,7 @@ void adc_disable_scan_mode(u32 adc) ADC_CR1(adc) &= ~ADC_CR1_SCAN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Injected End-Of-Conversion Interrupt @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -319,7 +327,7 @@ void adc_enable_eoc_interrupt_injected(u32 adc) ADC_CR1(adc) |= ADC_CR1_JEOCIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable Injected End-Of-Conversion Interrupt @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -330,7 +338,7 @@ void adc_disable_eoc_interrupt_injected(u32 adc) ADC_CR1(adc) &= ~ADC_CR1_JEOCIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Analog Watchdog Interrupt @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -341,7 +349,7 @@ void adc_enable_awd_interrupt(u32 adc) ADC_CR1(adc) |= ADC_CR1_AWDIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable Analog Watchdog Interrupt @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -352,7 +360,7 @@ void adc_disable_awd_interrupt(u32 adc) ADC_CR1(adc) &= ~ADC_CR1_AWDIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Regular End-Of-Conversion Interrupt @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -363,7 +371,7 @@ void adc_enable_eoc_interrupt(u32 adc) ADC_CR1(adc) |= ADC_CR1_EOCIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable Regular End-Of-Conversion Interrupt @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -374,7 +382,7 @@ void adc_disable_eoc_interrupt(u32 adc) ADC_CR1(adc) &= ~ADC_CR1_EOCIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Software Triggered Conversion on Regular Channels This starts conversion on a set of defined regular channels. It is cleared by @@ -392,7 +400,7 @@ void adc_start_conversion_regular(u32 adc) while (ADC_CR2(adc) & ADC_CR2_SWSTART); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Software Triggered Conversion on Injected Channels This starts conversion on a set of defined injected channels. It is cleared by @@ -410,7 +418,7 @@ void adc_start_conversion_injected(u32 adc) while (ADC_CR2(adc) & ADC_CR2_JSWSTART); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set the Data as Left Aligned @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -421,7 +429,7 @@ void adc_set_left_aligned(u32 adc) ADC_CR2(adc) |= ADC_CR2_ALIGN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set the Data as Right Aligned @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -432,7 +440,7 @@ void adc_set_right_aligned(u32 adc) ADC_CR2(adc) &= ~ADC_CR2_ALIGN; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable DMA Transfers @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -440,10 +448,10 @@ void adc_set_right_aligned(u32 adc) void adc_enable_dma(u32 adc) { - ADC_CR2(adc) |= ADC_CR2_DMA; + ADC_CR2(adc) |= ADC_CR2_DMA; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable DMA Transfers @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -451,10 +459,10 @@ void adc_enable_dma(u32 adc) void adc_disable_dma(u32 adc) { - ADC_CR2(adc) &= ~ADC_CR2_DMA; + ADC_CR2(adc) &= ~ADC_CR2_DMA; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Continuous Conversion Mode In this mode the ADC starts a new conversion of a single channel or a channel @@ -468,7 +476,7 @@ void adc_set_continuous_conversion_mode(u32 adc) ADC_CR2(adc) |= ADC_CR2_CONT; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable Single Conversion Mode In this mode the ADC performs a conversion of one channel or a channel group @@ -482,13 +490,14 @@ void adc_set_single_conversion_mode(u32 adc) ADC_CR2(adc) &= ~ADC_CR2_CONT; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set the Sample Time for a Single Channel The sampling time can be selected in ADC clock cycles from 1.5 to 239.5. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base -@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref adc_channel +@param[in] channel Unsigned int8. ADC Channel integer 0..18 or from @ref +adc_channel @param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg */ @@ -509,11 +518,11 @@ void adc_set_sample_time(u32 adc, u8 channel, u8 time) } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set the Sample Time for All Channels -The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same for -all channels. +The sampling time can be selected in ADC clock cycles from 1.5 to 239.5, same +for all channels. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @param[in] time Unsigned int8. Sampling time selection from @ref adc_sample_rg @@ -524,16 +533,18 @@ void adc_set_sample_time_on_all_channels(u32 adc, u8 time) u8 i; u32 reg32 = 0; - for (i = 0; i <= 9; i++) + for (i = 0; i <= 9; i++) { reg32 |= (time << (i * 3)); + } ADC_SMPR2(adc) = reg32; - for (i = 10; i <= 17; i++) + for (i = 10; i <= 17; i++) { reg32 |= (time << ((i - 10) * 3)); + } ADC_SMPR1(adc) = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set Analog Watchdog Upper Threshold @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -549,7 +560,7 @@ void adc_set_watchdog_high_threshold(u32 adc, u16 threshold) ADC_HTR(adc) = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set Analog Watchdog Lower Threshold @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -565,12 +576,12 @@ void adc_set_watchdog_low_threshold(u32 adc, u16 threshold) ADC_LTR(adc) = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set a Regular Channel Conversion Sequence Define a sequence of channels to be converted as a regular group with a length -from 1 to 16 channels. If this is called during conversion, the current conversion -is reset and conversion begins again with the newly defined group. +from 1 to 16 channels. If this is called during conversion, the current +conversion is reset and conversion begins again with the newly defined group. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @param[in] length Unsigned int8. Number of channels in the group. @@ -583,30 +594,34 @@ void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]) u8 i = 0; /* Maximum sequence length is 16 channels. */ - if (length > 16) + if (length > 16) { return; + } for (i = 1; i <= length; i++) { - if (i <= 6) + if (i <= 6) { reg32_3 |= (channel[i - 1] << ((i - 1) * 5)); - if ((i > 6) & (i <= 12)) + } + if ((i > 6) & (i <= 12)) { reg32_2 |= (channel[i - 1] << ((i - 6 - 1) * 5)); - if ((i > 12) & (i <= 16)) + } + if ((i > 12) & (i <= 16)) { reg32_1 |= (channel[i - 1] << ((i - 12 - 1) * 5)); + } } - reg32_1 |= ((length -1) << ADC_SQR1_L_LSB); + reg32_1 |= ((length - 1) << ADC_SQR1_L_LSB); ADC_SQR1(adc) = reg32_1; ADC_SQR2(adc) = reg32_2; ADC_SQR3(adc) = reg32_3; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set an Injected Channel Conversion Sequence -Defines a sequence of channels to be converted as an injected group with a length -from 1 to 4 channels. If this is called during conversion, the current conversion -is reset and conversion begins again with the newly defined group. +Defines a sequence of channels to be converted as an injected group with a +length from 1 to 4 channels. If this is called during conversion, the current +conversion is reset and conversion begins again with the newly defined group. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @param[in] length Unsigned int8. Number of channels in the group. @@ -619,18 +634,20 @@ void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]) u8 i = 0; /* Maximum sequence length is 4 channels. */ - if ((length-1) > 3) + if ((length-1) > 3) { return; + } - for (i = 1; i <= length; i++) + for (i = 1; i <= length; i++) { reg32 |= (channel[4 - i] << ((4 - i) * 5)); + } reg32 |= ((length - 1) << ADC_JSQR_JL_LSB); ADC_JSQR(adc) = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Read the End-of-Conversion Flag This flag is set after all channels of a regular or injected group have been @@ -642,10 +659,10 @@ converted. bool adc_eoc(u32 adc) { - return ((ADC_SR(adc) & ADC_SR_EOC) != 0); + return (ADC_SR(adc) & ADC_SR_EOC) != 0; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Read the End-of-Conversion Flag for Injected Conversion This flag is set after all channels of an injected group have been converted. @@ -656,10 +673,10 @@ This flag is set after all channels of an injected group have been converted. bool adc_eoc_injected(u32 adc) { - return ((ADC_SR(adc) & ADC_SR_JEOC) != 0); + return (ADC_SR(adc) & ADC_SR_JEOC) != 0; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Read from the Regular Conversion Result Register The result read back is 12 bits, right or left aligned within the first 16 bits. @@ -672,15 +689,16 @@ an appropriate dual mode has been set @see adc_set_dual_mode. u32 adc_read_regular(u32 adc) { - return ADC_DR(adc); + return ADC_DR(adc); } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Read from an Injected Conversion Result Register -The result read back from the selected injected result register (one of four) is -12 bits, right or left aligned within the first 16 bits. The result can have a -negative value if the injected channel offset has been set @see adc_set_injected_offset. +The result read back from the selected injected result register (one of four) +is 12 bits, right or left aligned within the first 16 bits. The result can have +a negative value if the injected channel offset has been set @see +adc_set_injected_offset. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @param[in] reg Unsigned int8. Register number (1 ... 4). @@ -689,24 +707,24 @@ negative value if the injected channel offset has been set @see adc_set_injected u32 adc_read_injected(u32 adc, u8 reg) { - switch (reg) { - case 1: - return ADC_JDR1(adc); - case 2: - return ADC_JDR2(adc); - case 3: - return ADC_JDR3(adc); - case 4: - return ADC_JDR4(adc); - } + switch (reg) { + case 1: + return ADC_JDR1(adc); + case 2: + return ADC_JDR2(adc); + case 3: + return ADC_JDR3(adc); + case 4: + return ADC_JDR4(adc); + } return 0; } -/*-----------------------------------------------------------------------------*/ +/*----------------------------------------------------------------------------*/ /** @brief ADC Set the Injected Channel Data Offset -This value is subtracted from the injected channel results after conversion -is complete, and can result in negative results. A separate value can be specified +This value is subtracted from the injected channel results after conversion is +complete, and can result in negative results. A separate value can be specified for each injected data register. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -716,23 +734,23 @@ for each injected data register. void adc_set_injected_offset(u32 adc, u8 reg, u32 offset) { - switch (reg) { - case 1: - ADC_JOFR1(adc) = offset; - break; - case 2: - ADC_JOFR2(adc) = offset; - break; - case 3: - ADC_JOFR3(adc) = offset; - break; - case 4: - ADC_JOFR4(adc) = offset; - break; - } + switch (reg) { + case 1: + ADC_JOFR1(adc) = offset; + break; + case 2: + ADC_JOFR2(adc) = offset; + break; + case 3: + ADC_JOFR3(adc) = offset; + break; + case 4: + ADC_JOFR4(adc) = offset; + break; + } } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Power On If the ADC is in power-down mode then it is powered up. The application needs @@ -747,12 +765,13 @@ void adc_power_on(u32 adc) ADC_CR2(adc) |= ADC_CR2_ADON; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set Clock Prescale The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8. -@param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref adc_ccr_adcpre +@param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref +adc_ccr_adcpre */ void adc_set_clk_prescale(u32 prescale) @@ -761,7 +780,7 @@ void adc_set_clk_prescale(u32 prescale) ADC_CCR = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set Dual/Triple Mode The multiple mode uses ADC1 as master, ADC2 and optionally ADC3 in a slave @@ -777,16 +796,17 @@ void adc_set_multi_mode(u32 mode) ADC_CCR |= mode; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable an External Trigger for Regular Channels -This enables an external trigger for set of defined regular channels, and sets the -polarity of the trigger event: rising or falling edge or both. Note that if the -trigger polarity is zero, triggering is disabled. +This enables an external trigger for set of defined regular channels, and sets +the polarity of the trigger event: rising or falling edge or both. Note that if +the trigger polarity is zero, triggering is disabled. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @param[in] trigger Unsigned int32. Trigger identifier @ref adc_trigger_regular -@param[in] polarity Unsigned int32. Trigger polarity @ref adc_trigger_polarity_regular +@param[in] polarity Unsigned int32. Trigger polarity @ref +adc_trigger_polarity_regular */ void adc_enable_external_trigger_regular(u32 adc, u32 trigger, u32 polarity) @@ -798,7 +818,7 @@ void adc_enable_external_trigger_regular(u32 adc, u32 trigger, u32 polarity) ADC_CR2(adc) = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable an External Trigger for Regular Channels @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -809,15 +829,16 @@ void adc_disable_external_trigger_regular(u32 adc) ADC_CR2(adc) &= ~ADC_CR2_EXTEN_MASK; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable an External Trigger for Injected Channels -This enables an external trigger for set of defined injected channels, and sets the -polarity of the trigger event: rising or falling edge or both. +This enables an external trigger for set of defined injected channels, and sets +the polarity of the trigger event: rising or falling edge or both. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @param[in] trigger Unsigned int8. Trigger identifier @ref adc_trigger_injected -@param[in] polarity Unsigned int32. Trigger polarity @ref adc_trigger_polarity_injected +@param[in] polarity Unsigned int32. Trigger polarity @ref +adc_trigger_polarity_injected */ void adc_enable_external_trigger_injected(u32 adc, u32 trigger, u32 polarity) @@ -829,7 +850,7 @@ void adc_enable_external_trigger_injected(u32 adc, u32 trigger, u32 polarity) ADC_CR2(adc) = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable an External Trigger for Injected Channels @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -840,11 +861,11 @@ void adc_disable_external_trigger_injected(u32 adc) ADC_CR2(adc) &= ~ADC_CR2_JEXTEN_MASK; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set Resolution -ADC Resolution can be reduced from 12 bits to 10, 8 or 6 bits for a corresponding -reduction in conversion time (resolution + 3 ADC clock cycles). +ADC Resolution can be reduced from 12 bits to 10, 8 or 6 bits for a +corresponding reduction in conversion time (resolution + 3 ADC clock cycles). @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @param[in] resolution Unsigned int8. Resolution value @ref adc_cr1_res @@ -859,7 +880,7 @@ void adc_set_resolution(u32 adc, u16 resolution) ADC_CR1(adc) = reg32; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable the Overrun Interrupt The overrun interrupt is generated when data is not read from a result register @@ -874,7 +895,7 @@ void adc_enable_overrun_interrupt(u32 adc) ADC_CR1(adc) |= ADC_CR1_OVRIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable the Overrun Interrupt @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @@ -885,12 +906,12 @@ void adc_disable_overrun_interrupt(u32 adc) ADC_CR1(adc) &= ~ADC_CR1_OVRIE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Read the Overrun Flag -The overrun flag is set when data is not read from a result register before the next -conversion is written. If DMA is enabled, all transfers are terminated and any -conversion sequence is aborted. +The overrun flag is set when data is not read from a result register before the +next conversion is written. If DMA is enabled, all transfers are terminated and +any conversion sequence is aborted. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base @returns Unsigned int32 conversion result. @@ -898,10 +919,10 @@ conversion sequence is aborted. bool adc_get_overrun_flag(u32 adc) { - return (ADC_SR(adc) & ADC_SR_OVR); + return ADC_SR(adc) & ADC_SR_OVR; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Clear Overrun Flags The overrun flag is cleared. Note that if an overrun occurs, DMA is terminated. @@ -918,7 +939,7 @@ void adc_clear_overrun_flag(u32 adc) ADC_SR(adc) &= ~ADC_SR_OVR; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable an EOC for Each Conversion The EOC is set after each conversion in a sequence rather than at the end of the @@ -932,11 +953,11 @@ void adc_eoc_after_each(u32 adc) ADC_CR2(adc) |= ADC_CR2_EOCS; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable the EOC for Each Conversion -The EOC is set at the end of each sequence rather than after each conversion in the -sequence. Overrun detection is enabled always. +The EOC is set at the end of each sequence rather than after each conversion in +the sequence. Overrun detection is enabled always. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ @@ -946,11 +967,11 @@ void adc_eoc_after_group(u32 adc) ADC_CR2(adc) &= ~ADC_CR2_EOCS; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set DMA to Continue -This must be set to allow DMA to continue to operate after the last conversion in -the DMA sequence. This allows DMA to be used in continuous circular mode. +This must be set to allow DMA to continue to operate after the last conversion +in the DMA sequence. This allows DMA to be used in continuous circular mode. @param[in] adc Unsigned int32. ADC block register address base @ref adc_reg_base */ @@ -960,7 +981,7 @@ void adc_set_dma_continue(u32 adc) ADC_CR2(adc) |= ADC_CR2_DDS; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Set DMA to Terminate This must be set to allow DMA to terminate after the last conversion in the DMA @@ -973,7 +994,7 @@ void adc_set_dma_terminate(u32 adc) { ADC_CR2(adc) &= ~ADC_CR2_DDS; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Read the Analog Watchdog Flag This flag is set when the converted voltage crosses the high or low thresholds. @@ -984,10 +1005,10 @@ This flag is set when the converted voltage crosses the high or low thresholds. bool adc_awd(u32 adc) { - return (ADC_SR(adc) & ADC_SR_AWD); + return ADC_SR(adc) & ADC_SR_AWD; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Enable The Temperature Sensor This enables both the sensor and the reference voltage measurements on channels @@ -1001,7 +1022,7 @@ void adc_enable_temperature_sensor() ADC_CCR |= ADC_CCR_TSVREFE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /** @brief ADC Disable The Temperature Sensor Disabling this will reduce power consumption from the sensor and the reference @@ -1015,7 +1036,7 @@ void adc_disable_temperature_sensor() ADC_CCR &= ~ADC_CCR_TSVREFE; } -/*-----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ /**@}*/ diff --git a/lib/stm32/f4/pwr.c b/lib/stm32/f4/pwr.c index e4921925..b44ab5a6 100644 --- a/lib/stm32/f4/pwr.c +++ b/lib/stm32/f4/pwr.c @@ -38,8 +38,9 @@ LGPL License Terms @ref lgpl_license void pwr_set_vos_scale(vos_scale_t scale) { - if (scale == SCALE1) + if (scale == SCALE1) { PWR_CR |= PWR_CR_VOS; - else if (scale == SCALE2) + } else if (scale == SCALE2) { PWR_CR &= PWR_CR_VOS; + } } diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c index 22502836..6b56e584 100644 --- a/lib/stm32/f4/rcc.c +++ b/lib/stm32/f4/rcc.c @@ -28,506 +28,513 @@ u32 rcc_ppre1_frequency = 16000000; u32 rcc_ppre2_frequency = 16000000; -const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] = -{ - { /* 48MHz */ - .pllm = 8, - .plln = 96, - .pllp = 2, - .pllq = 2, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, - .power_save = 1, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS, - .apb1_frequency = 12000000, - .apb2_frequency = 24000000, - }, - { /* 120MHz */ - .pllm = 8, - .plln = 240, - .pllp = 2, - .pllq = 5, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, - .power_save = 1, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS, - .apb1_frequency = 30000000, - .apb2_frequency = 60000000, - }, - { /* 168MHz */ - .pllm = 8, - .plln = 336, - .pllp = 2, - .pllq = 7, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_5WS, - .apb1_frequency = 42000000, - .apb2_frequency = 84000000, - }, +const clock_scale_t hse_8mhz_3v3[CLOCK_3V3_END] = { + { /* 48MHz */ + .pllm = 8, + .plln = 96, + .pllp = 2, + .pllq = 2, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_4, + .ppre2 = RCC_CFGR_PPRE_DIV_2, + .power_save = 1, + .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + FLASH_ACR_LATENCY_3WS, + .apb1_frequency = 12000000, + .apb2_frequency = 24000000, + }, + { /* 120MHz */ + .pllm = 8, + .plln = 240, + .pllp = 2, + .pllq = 5, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_4, + .ppre2 = RCC_CFGR_PPRE_DIV_2, + .power_save = 1, + .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + FLASH_ACR_LATENCY_3WS, + .apb1_frequency = 30000000, + .apb2_frequency = 60000000, + }, + { /* 168MHz */ + .pllm = 8, + .plln = 336, + .pllp = 2, + .pllq = 7, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_4, + .ppre2 = RCC_CFGR_PPRE_DIV_2, + .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + FLASH_ACR_LATENCY_5WS, + .apb1_frequency = 42000000, + .apb2_frequency = 84000000, + }, }; -const clock_scale_t hse_12mhz_3v3[CLOCK_3V3_END] = -{ - { /* 48MHz */ - .pllm = 12, - .plln = 96, - .pllp = 2, - .pllq = 2, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, - .power_save = 1, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS, - .apb1_frequency = 12000000, - .apb2_frequency = 24000000, - }, - { /* 120MHz */ - .pllm = 12, - .plln = 240, - .pllp = 2, - .pllq = 5, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, - .power_save = 1, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS, - .apb1_frequency = 30000000, - .apb2_frequency = 60000000, - }, - { /* 168MHz */ - .pllm = 12, - .plln = 336, - .pllp = 2, - .pllq = 7, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_5WS, - .apb1_frequency = 42000000, - .apb2_frequency = 84000000, - }, +const clock_scale_t hse_12mhz_3v3[CLOCK_3V3_END] = { + { /* 48MHz */ + .pllm = 12, + .plln = 96, + .pllp = 2, + .pllq = 2, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_4, + .ppre2 = RCC_CFGR_PPRE_DIV_2, + .power_save = 1, + .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + FLASH_ACR_LATENCY_3WS, + .apb1_frequency = 12000000, + .apb2_frequency = 24000000, + }, + { /* 120MHz */ + .pllm = 12, + .plln = 240, + .pllp = 2, + .pllq = 5, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_4, + .ppre2 = RCC_CFGR_PPRE_DIV_2, + .power_save = 1, + .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + FLASH_ACR_LATENCY_3WS, + .apb1_frequency = 30000000, + .apb2_frequency = 60000000, + }, + { /* 168MHz */ + .pllm = 12, + .plln = 336, + .pllp = 2, + .pllq = 7, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_4, + .ppre2 = RCC_CFGR_PPRE_DIV_2, + .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + FLASH_ACR_LATENCY_5WS, + .apb1_frequency = 42000000, + .apb2_frequency = 84000000, + }, }; -const clock_scale_t hse_16mhz_3v3[CLOCK_3V3_END] = -{ - { /* 48MHz */ - .pllm = 16, - .plln = 96, - .pllp = 2, - .pllq = 2, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, - .power_save = 1, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS, - .apb1_frequency = 12000000, - .apb2_frequency = 24000000, - }, - { /* 120MHz */ - .pllm = 16, - .plln = 240, - .pllp = 2, - .pllq = 5, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, - .power_save = 1, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_3WS, - .apb1_frequency = 30000000, - .apb2_frequency = 60000000, - }, - { /* 168MHz */ - .pllm = 16, - .plln = 336, - .pllp = 2, - .pllq = 7, - .hpre = RCC_CFGR_HPRE_DIV_NONE, - .ppre1 = RCC_CFGR_PPRE_DIV_4, - .ppre2 = RCC_CFGR_PPRE_DIV_2, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | FLASH_ACR_LATENCY_5WS, - .apb1_frequency = 42000000, - .apb2_frequency = 84000000, - }, +const clock_scale_t hse_16mhz_3v3[CLOCK_3V3_END] = { + { /* 48MHz */ + .pllm = 16, + .plln = 96, + .pllp = 2, + .pllq = 2, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_4, + .ppre2 = RCC_CFGR_PPRE_DIV_2, + .power_save = 1, + .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + FLASH_ACR_LATENCY_3WS, + .apb1_frequency = 12000000, + .apb2_frequency = 24000000, + }, + { /* 120MHz */ + .pllm = 16, + .plln = 240, + .pllp = 2, + .pllq = 5, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_4, + .ppre2 = RCC_CFGR_PPRE_DIV_2, + .power_save = 1, + .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + FLASH_ACR_LATENCY_3WS, + .apb1_frequency = 30000000, + .apb2_frequency = 60000000, + }, + { /* 168MHz */ + .pllm = 16, + .plln = 336, + .pllp = 2, + .pllq = 7, + .hpre = RCC_CFGR_HPRE_DIV_NONE, + .ppre1 = RCC_CFGR_PPRE_DIV_4, + .ppre2 = RCC_CFGR_PPRE_DIV_2, + .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + FLASH_ACR_LATENCY_5WS, + .apb1_frequency = 42000000, + .apb2_frequency = 84000000, + }, }; void rcc_osc_ready_int_clear(osc_t osc) { - switch (osc) { - case PLL: - RCC_CIR |= RCC_CIR_PLLRDYC; - break; - case HSE: - RCC_CIR |= RCC_CIR_HSERDYC; - break; - case HSI: - RCC_CIR |= RCC_CIR_HSIRDYC; - break; - case LSE: - RCC_CIR |= RCC_CIR_LSERDYC; - break; - case LSI: - RCC_CIR |= RCC_CIR_LSIRDYC; - break; - } + switch (osc) { + case PLL: + RCC_CIR |= RCC_CIR_PLLRDYC; + break; + case HSE: + RCC_CIR |= RCC_CIR_HSERDYC; + break; + case HSI: + RCC_CIR |= RCC_CIR_HSIRDYC; + break; + case LSE: + RCC_CIR |= RCC_CIR_LSERDYC; + break; + case LSI: + RCC_CIR |= RCC_CIR_LSIRDYC; + break; + } } void rcc_osc_ready_int_enable(osc_t osc) { - switch (osc) { - case PLL: - RCC_CIR |= RCC_CIR_PLLRDYIE; - break; - case HSE: - RCC_CIR |= RCC_CIR_HSERDYIE; - break; - case HSI: - RCC_CIR |= RCC_CIR_HSIRDYIE; - break; - case LSE: - RCC_CIR |= RCC_CIR_LSERDYIE; - break; - case LSI: - RCC_CIR |= RCC_CIR_LSIRDYIE; - break; - } + switch (osc) { + case PLL: + RCC_CIR |= RCC_CIR_PLLRDYIE; + break; + case HSE: + RCC_CIR |= RCC_CIR_HSERDYIE; + break; + case HSI: + RCC_CIR |= RCC_CIR_HSIRDYIE; + break; + case LSE: + RCC_CIR |= RCC_CIR_LSERDYIE; + break; + case LSI: + RCC_CIR |= RCC_CIR_LSIRDYIE; + break; + } } void rcc_osc_ready_int_disable(osc_t osc) { - switch (osc) { - case PLL: - RCC_CIR &= ~RCC_CIR_PLLRDYIE; - break; - case HSE: - RCC_CIR &= ~RCC_CIR_HSERDYIE; - break; - case HSI: - RCC_CIR &= ~RCC_CIR_HSIRDYIE; - break; - case LSE: - RCC_CIR &= ~RCC_CIR_LSERDYIE; - break; - case LSI: - RCC_CIR &= ~RCC_CIR_LSIRDYIE; - break; - } + switch (osc) { + case PLL: + RCC_CIR &= ~RCC_CIR_PLLRDYIE; + break; + case HSE: + RCC_CIR &= ~RCC_CIR_HSERDYIE; + break; + case HSI: + RCC_CIR &= ~RCC_CIR_HSIRDYIE; + break; + case LSE: + RCC_CIR &= ~RCC_CIR_LSERDYIE; + break; + case LSI: + RCC_CIR &= ~RCC_CIR_LSIRDYIE; + break; + } } int rcc_osc_ready_int_flag(osc_t osc) { - switch (osc) { - case PLL: - return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0); - break; - case HSE: - return ((RCC_CIR & RCC_CIR_HSERDYF) != 0); - break; - case HSI: - return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0); - break; - case LSE: - return ((RCC_CIR & RCC_CIR_LSERDYF) != 0); - break; - case LSI: - return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0); - break; - } + switch (osc) { + case PLL: + return ((RCC_CIR & RCC_CIR_PLLRDYF) != 0); + break; + case HSE: + return ((RCC_CIR & RCC_CIR_HSERDYF) != 0); + break; + case HSI: + return ((RCC_CIR & RCC_CIR_HSIRDYF) != 0); + break; + case LSE: + return ((RCC_CIR & RCC_CIR_LSERDYF) != 0); + break; + case LSI: + return ((RCC_CIR & RCC_CIR_LSIRDYF) != 0); + break; + } - cm3_assert_not_reached(); + cm3_assert_not_reached(); } void rcc_css_int_clear(void) { - RCC_CIR |= RCC_CIR_CSSC; + RCC_CIR |= RCC_CIR_CSSC; } int rcc_css_int_flag(void) { - return ((RCC_CIR & RCC_CIR_CSSF) != 0); + return ((RCC_CIR & RCC_CIR_CSSF) != 0); } void rcc_wait_for_osc_ready(osc_t osc) { - switch (osc) { - case PLL: - while ((RCC_CR & RCC_CR_PLLRDY) == 0); - break; - case HSE: - while ((RCC_CR & RCC_CR_HSERDY) == 0); - break; - case HSI: - while ((RCC_CR & RCC_CR_HSIRDY) == 0); - break; - case LSE: - while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0); - break; - case LSI: - while ((RCC_CSR & RCC_CSR_LSIRDY) == 0); - break; - } + switch (osc) { + case PLL: + while ((RCC_CR & RCC_CR_PLLRDY) == 0); + break; + case HSE: + while ((RCC_CR & RCC_CR_HSERDY) == 0); + break; + case HSI: + while ((RCC_CR & RCC_CR_HSIRDY) == 0); + break; + case LSE: + while ((RCC_BDCR & RCC_BDCR_LSERDY) == 0); + break; + case LSI: + while ((RCC_CSR & RCC_CSR_LSIRDY) == 0); + break; + } } void rcc_wait_for_sysclk_status(osc_t osc) { - switch (osc) { - case PLL: - while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL); - break; - case HSE: - while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE); - break; - case HSI: - while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI); - break; - default: - /* Shouldn't be reached. */ - break; - } + switch (osc) { + case PLL: + while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_PLL); + break; + case HSE: + while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSE); + break; + case HSI: + while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_HSI); + break; + default: + /* Shouldn't be reached. */ + break; + } } void rcc_osc_on(osc_t osc) { - switch (osc) { - case PLL: - RCC_CR |= RCC_CR_PLLON; - break; - case HSE: - RCC_CR |= RCC_CR_HSEON; - break; - case HSI: - RCC_CR |= RCC_CR_HSION; - break; - case LSE: - RCC_BDCR |= RCC_BDCR_LSEON; - break; - case LSI: - RCC_CSR |= RCC_CSR_LSION; - break; - } + switch (osc) { + case PLL: + RCC_CR |= RCC_CR_PLLON; + break; + case HSE: + RCC_CR |= RCC_CR_HSEON; + break; + case HSI: + RCC_CR |= RCC_CR_HSION; + break; + case LSE: + RCC_BDCR |= RCC_BDCR_LSEON; + break; + case LSI: + RCC_CSR |= RCC_CSR_LSION; + break; + } } void rcc_osc_off(osc_t osc) { - switch (osc) { - case PLL: - RCC_CR &= ~RCC_CR_PLLON; - break; - case HSE: - RCC_CR &= ~RCC_CR_HSEON; - break; - case HSI: - RCC_CR &= ~RCC_CR_HSION; - break; - case LSE: - RCC_BDCR &= ~RCC_BDCR_LSEON; - break; - case LSI: - RCC_CSR &= ~RCC_CSR_LSION; - break; - } + switch (osc) { + case PLL: + RCC_CR &= ~RCC_CR_PLLON; + break; + case HSE: + RCC_CR &= ~RCC_CR_HSEON; + break; + case HSI: + RCC_CR &= ~RCC_CR_HSION; + break; + case LSE: + RCC_BDCR &= ~RCC_BDCR_LSEON; + break; + case LSI: + RCC_CSR &= ~RCC_CSR_LSION; + break; + } } void rcc_css_enable(void) { - RCC_CR |= RCC_CR_CSSON; + RCC_CR |= RCC_CR_CSSON; } void rcc_css_disable(void) { - RCC_CR &= ~RCC_CR_CSSON; + RCC_CR &= ~RCC_CR_CSSON; } void rcc_osc_bypass_enable(osc_t osc) { - switch (osc) { - case HSE: - RCC_CR |= RCC_CR_HSEBYP; - break; - case LSE: - RCC_BDCR |= RCC_BDCR_LSEBYP; - break; - case PLL: - case HSI: - case LSI: - /* Do nothing, only HSE/LSE allowed here. */ - break; - } + switch (osc) { + case HSE: + RCC_CR |= RCC_CR_HSEBYP; + break; + case LSE: + RCC_BDCR |= RCC_BDCR_LSEBYP; + break; + case PLL: + case HSI: + case LSI: + /* Do nothing, only HSE/LSE allowed here. */ + break; + } } void rcc_osc_bypass_disable(osc_t osc) { - switch (osc) { - case HSE: - RCC_CR &= ~RCC_CR_HSEBYP; - break; - case LSE: - RCC_BDCR &= ~RCC_BDCR_LSEBYP; - break; - case PLL: - case HSI: - case LSI: - /* Do nothing, only HSE/LSE allowed here. */ - break; - } + switch (osc) { + case HSE: + RCC_CR &= ~RCC_CR_HSEBYP; + break; + case LSE: + RCC_BDCR &= ~RCC_BDCR_LSEBYP; + break; + case PLL: + case HSI: + case LSI: + /* Do nothing, only HSE/LSE allowed here. */ + break; + } } void rcc_peripheral_enable_clock(volatile u32 *reg, u32 en) { - *reg |= en; + *reg |= en; } void rcc_peripheral_disable_clock(volatile u32 *reg, u32 en) { - *reg &= ~en; + *reg &= ~en; } void rcc_peripheral_reset(volatile u32 *reg, u32 reset) { - *reg |= reset; + *reg |= reset; } void rcc_peripheral_clear_reset(volatile u32 *reg, u32 clear_reset) { - *reg &= ~clear_reset; + *reg &= ~clear_reset; } void rcc_set_sysclk_source(u32 clk) { - u32 reg32; + u32 reg32; - reg32 = RCC_CFGR; - reg32 &= ~((1 << 1) | (1 << 0)); - RCC_CFGR = (reg32 | clk); + reg32 = RCC_CFGR; + reg32 &= ~((1 << 1) | (1 << 0)); + RCC_CFGR = (reg32 | clk); } void rcc_set_pll_source(u32 pllsrc) { - u32 reg32; + u32 reg32; - reg32 = RCC_PLLCFGR; - reg32 &= ~(1 << 22); - RCC_PLLCFGR = (reg32 | (pllsrc << 22)); + reg32 = RCC_PLLCFGR; + reg32 &= ~(1 << 22); + RCC_PLLCFGR = (reg32 | (pllsrc << 22)); } void rcc_set_ppre2(u32 ppre2) { - u32 reg32; + u32 reg32; - reg32 = RCC_CFGR; - reg32 &= ~((1 << 13) | (1 << 14) | (1 << 15)); - RCC_CFGR = (reg32 | (ppre2 << 13)); + reg32 = RCC_CFGR; + reg32 &= ~((1 << 13) | (1 << 14) | (1 << 15)); + RCC_CFGR = (reg32 | (ppre2 << 13)); } void rcc_set_ppre1(u32 ppre1) { - u32 reg32; + u32 reg32; - reg32 = RCC_CFGR; - reg32 &= ~((1 << 10) | (1 << 11) | (1 << 12)); - RCC_CFGR = (reg32 | (ppre1 << 10)); + reg32 = RCC_CFGR; + reg32 &= ~((1 << 10) | (1 << 11) | (1 << 12)); + RCC_CFGR = (reg32 | (ppre1 << 10)); } void rcc_set_hpre(u32 hpre) { - u32 reg32; + u32 reg32; - reg32 = RCC_CFGR; - reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7)); - RCC_CFGR = (reg32 | (hpre << 4)); + reg32 = RCC_CFGR; + reg32 &= ~((1 << 4) | (1 << 5) | (1 << 6) | (1 << 7)); + RCC_CFGR = (reg32 | (hpre << 4)); } void rcc_set_rtcpre(u32 rtcpre) { - u32 reg32; + u32 reg32; - reg32 = RCC_CFGR; - reg32 &= ~((1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20)); - RCC_CFGR = (reg32 | (rtcpre << 16)); + reg32 = RCC_CFGR; + reg32 &= ~((1 << 16) | (1 << 17) | (1 << 18) | (1 << 19) | (1 << 20)); + RCC_CFGR = (reg32 | (rtcpre << 16)); } void rcc_set_main_pll_hsi(u32 pllm, u32 plln, u32 pllp, u32 pllq) { - RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) | - (plln << RCC_PLLCFGR_PLLN_SHIFT) | - (((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) | - (pllq << RCC_PLLCFGR_PLLQ_SHIFT); + RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) | + (plln << RCC_PLLCFGR_PLLN_SHIFT) | + (((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) | + (pllq << RCC_PLLCFGR_PLLQ_SHIFT); } void rcc_set_main_pll_hse(u32 pllm, u32 plln, u32 pllp, u32 pllq) { - RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) | - (plln << RCC_PLLCFGR_PLLN_SHIFT) | - (((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) | - RCC_PLLCFGR_PLLSRC | - (pllq << RCC_PLLCFGR_PLLQ_SHIFT); + RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) | + (plln << RCC_PLLCFGR_PLLN_SHIFT) | + (((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT) | + RCC_PLLCFGR_PLLSRC | + (pllq << RCC_PLLCFGR_PLLQ_SHIFT); } u32 rcc_system_clock_source(void) { - /* Return the clock source which is used as system clock. */ - return ((RCC_CFGR & 0x000c) >> 2); + /* Return the clock source which is used as system clock. */ + return (RCC_CFGR & 0x000c) >> 2; } void rcc_clock_setup_hse_3v3(const clock_scale_t *clock) { - /* Enable internal high-speed oscillator. */ - rcc_osc_on(HSI); - rcc_wait_for_osc_ready(HSI); + /* Enable internal high-speed oscillator. */ + rcc_osc_on(HSI); + rcc_wait_for_osc_ready(HSI); - /* Select HSI as SYSCLK source. */ - rcc_set_sysclk_source(RCC_CFGR_SW_HSI); + /* Select HSI as SYSCLK source. */ + rcc_set_sysclk_source(RCC_CFGR_SW_HSI); - /* Enable external high-speed oscillator 8MHz. */ - rcc_osc_on(HSE); - rcc_wait_for_osc_ready(HSE); + /* Enable external high-speed oscillator 8MHz. */ + rcc_osc_on(HSE); + rcc_wait_for_osc_ready(HSE); - /* Enable/disable high performance mode */ - if (!clock->power_save) - pwr_set_vos_scale(SCALE1); - else - pwr_set_vos_scale(SCALE2); + /* Enable/disable high performance mode */ + if (!clock->power_save) { + pwr_set_vos_scale(SCALE1); + } else { + pwr_set_vos_scale(SCALE2); + } - /* - * Set prescalers for AHB, ADC, ABP1, ABP2. - * Do this before touching the PLL (TODO: why?). - */ - rcc_set_hpre(clock->hpre); - rcc_set_ppre1(clock->ppre1); - rcc_set_ppre2(clock->ppre2); + /* + * Set prescalers for AHB, ADC, ABP1, ABP2. + * Do this before touching the PLL (TODO: why?). + */ + rcc_set_hpre(clock->hpre); + rcc_set_ppre1(clock->ppre1); + rcc_set_ppre2(clock->ppre2); - rcc_set_main_pll_hse(clock->pllm, clock->plln, - clock->pllp, clock->pllq); + rcc_set_main_pll_hse(clock->pllm, clock->plln, + clock->pllp, clock->pllq); - /* Enable PLL oscillator and wait for it to stabilize. */ - rcc_osc_on(PLL); - rcc_wait_for_osc_ready(PLL); + /* Enable PLL oscillator and wait for it to stabilize. */ + rcc_osc_on(PLL); + rcc_wait_for_osc_ready(PLL); - /* Configure flash settings. */ - flash_set_ws(clock->flash_config); + /* Configure flash settings. */ + flash_set_ws(clock->flash_config); - /* Select PLL as SYSCLK source. */ - rcc_set_sysclk_source(RCC_CFGR_SW_PLL); + /* Select PLL as SYSCLK source. */ + rcc_set_sysclk_source(RCC_CFGR_SW_PLL); - /* Wait for PLL clock to be selected. */ - rcc_wait_for_sysclk_status(PLL); + /* Wait for PLL clock to be selected. */ + rcc_wait_for_sysclk_status(PLL); - /* Set the peripheral clock frequencies used. */ - rcc_ppre1_frequency = clock->apb1_frequency; - rcc_ppre2_frequency = clock->apb2_frequency; + /* Set the peripheral clock frequencies used. */ + rcc_ppre1_frequency = clock->apb1_frequency; + rcc_ppre2_frequency = clock->apb2_frequency; - /* Disable internal high-speed oscillator. */ - rcc_osc_off(HSI); + /* Disable internal high-speed oscillator. */ + rcc_osc_off(HSI); } void rcc_backupdomain_reset(void) { - /* Set the backup domain software reset. */ - RCC_BDCR |= RCC_BDCR_BDRST; + /* Set the backup domain software reset. */ + RCC_BDCR |= RCC_BDCR_BDRST; - /* Clear the backup domain software reset. */ - RCC_BDCR &= ~RCC_BDCR_BDRST; + /* Clear the backup domain software reset. */ + RCC_BDCR &= ~RCC_BDCR_BDRST; } diff --git a/lib/stm32/f4/rtc.c b/lib/stm32/f4/rtc.c index 77f56318..4de488da 100644 --- a/lib/stm32/f4/rtc.c +++ b/lib/stm32/f4/rtc.c @@ -39,9 +39,10 @@ LGPL License Terms @ref lgpl_license @warning You must unlock the registers before using this function */ -void rtc_enable_wakeup_timer(void) { - RTC_CR |= RTC_CR_WUTE | (RTC_CR_OSEL_WAKEUP << RTC_CR_OSEL_SHIFT); - rtc_enable_wakeup_timer_interrupt(); +void rtc_enable_wakeup_timer(void) +{ + RTC_CR |= RTC_CR_WUTE | (RTC_CR_OSEL_WAKEUP << RTC_CR_OSEL_SHIFT); + rtc_enable_wakeup_timer_interrupt(); } /*---------------------------------------------------------------------------*/ @@ -49,9 +50,10 @@ void rtc_enable_wakeup_timer(void) { @warning You must unlock the registers before using this function */ -void rtc_disable_wakeup_timer(void) { - RTC_CR &= ~RTC_CR_WUTE; - rtc_disable_wakeup_timer_interrupt(); +void rtc_disable_wakeup_timer(void) +{ + RTC_CR &= ~RTC_CR_WUTE; + rtc_disable_wakeup_timer_interrupt(); } /*---------------------------------------------------------------------------*/ @@ -59,20 +61,23 @@ void rtc_disable_wakeup_timer(void) { @warning You must unlock the registers before using this function */ -void rtc_enable_wakeup_timer_interrupt(void) { -// FTFM: -// To enable the RTC Wakeup interrupt, the following sequence is required: -// 1. Configure and enable the EXTI Line 22 in interrupt mode and select the -// rising edge sensitivity. - exti_enable_request(EXTI22); - exti_set_trigger(EXTI22, EXTI_TRIGGER_RISING); +void rtc_enable_wakeup_timer_interrupt(void) +{ + /* FTFM: + * To enable the RTC Wakeup interrupt, the following sequence is + * required: + * 1. Configure and enable the EXTI Line 22 in interrupt mode and + * select the rising edge sensitivity. + */ + exti_enable_request(EXTI22); + exti_set_trigger(EXTI22, EXTI_TRIGGER_RISING); -// 2. Configure and enable the RTC_WKUP IRQ channel in the NVIC. - nvic_enable_irq(NVIC_RTC_WKUP_IRQ); - nvic_set_priority(NVIC_RTC_WKUP_IRQ, 1); + /* 2. Configure and enable the RTC_WKUP IRQ channel in the NVIC. */ + nvic_enable_irq(NVIC_RTC_WKUP_IRQ); + nvic_set_priority(NVIC_RTC_WKUP_IRQ, 1); -// 3. Configure the RTC to generate the RTC wakeup timer event. - RTC_CR |= RTC_CR_WUTIE; // Enable the interrupt + /* 3. Configure the RTC to generate the RTC wakeup timer event. */ + RTC_CR |= RTC_CR_WUTIE; /* Enable the interrupt */ } /*---------------------------------------------------------------------------*/ @@ -80,13 +85,14 @@ void rtc_enable_wakeup_timer_interrupt(void) { @warning You must unlock the registers before using this function */ -void rtc_disable_wakeup_timer_interrupt(void) { -// 1. Disable EXTI Line 22 - exti_disable_request(EXTI22); +void rtc_disable_wakeup_timer_interrupt(void) +{ + /* 1. Disable EXTI Line 22 */ + exti_disable_request(EXTI22); -// 2. Disable RTC_WKUP IRQ channel in the NVIC. - nvic_disable_irq(NVIC_RTC_WKUP_IRQ); + /* 2. Disable RTC_WKUP IRQ channel in the NVIC. */ + nvic_disable_irq(NVIC_RTC_WKUP_IRQ); -// 3. Disable RTC wakeup timer event. - RTC_CR &= ~RTC_CR_WUTIE; + /* 3. Disable RTC wakeup timer event. */ + RTC_CR &= ~RTC_CR_WUTIE; } diff --git a/lib/stm32/l1/flash.c b/lib/stm32/l1/flash.c index 7b20f699..f0cfb38f 100644 --- a/lib/stm32/l1/flash.c +++ b/lib/stm32/l1/flash.c @@ -49,4 +49,4 @@ void flash_set_ws(u32 ws) reg32 &= ~(1 << 0); reg32 |= ws; FLASH_ACR = reg32; -} \ No newline at end of file +} diff --git a/lib/stm32/l1/rcc.c b/lib/stm32/l1/rcc.c index 9799e53a..9bbb4806 100644 --- a/lib/stm32/l1/rcc.c +++ b/lib/stm32/l1/rcc.c @@ -29,8 +29,7 @@ u32 rcc_ppre1_frequency = 2097000; u32 rcc_ppre2_frequency = 2097000; -const clock_scale_t clock_config[CLOCK_CONFIG_END] = -{ +const clock_scale_t clock_config[CLOCK_CONFIG_END] = { { /* 24MHz PLL from HSI */ .pll_source = RCC_CFGR_PLLSRC_HSI_CLK, .pll_mul = RCC_CFGR_PLLMUL_MUL3, @@ -232,16 +231,20 @@ void rcc_wait_for_sysclk_status(osc_t osc) { switch (osc) { case PLL: - while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_SYSCLKSEL_PLLCLK); + while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != + RCC_CFGR_SWS_SYSCLKSEL_PLLCLK); break; case HSE: - while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_SYSCLKSEL_HSECLK); + while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != + RCC_CFGR_SWS_SYSCLKSEL_HSECLK); break; case HSI: - while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_SYSCLKSEL_HSICLK); + while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != + RCC_CFGR_SWS_SYSCLKSEL_HSICLK); break; case MSI: - while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != RCC_CFGR_SWS_SYSCLKSEL_MSICLK); + while ((RCC_CFGR & ((1 << 1) | (1 << 0))) != + RCC_CFGR_SWS_SYSCLKSEL_MSICLK); break; default: /* Shouldn't be reached. */ @@ -434,7 +437,7 @@ void rcc_set_rtcpre(u32 rtcpre) u32 rcc_system_clock_source(void) { /* Return the clock source which is used as system clock. */ - return ((RCC_CFGR & 0x000c) >> 2); + return (RCC_CFGR & 0x000c) >> 2; } void rcc_rtc_select_clock(u32 clock) @@ -469,7 +472,7 @@ void rcc_clock_setup_msi(const clock_scale_t *clock) rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_PWREN); pwr_set_vos_scale(clock->voltage_scale); - // I guess this should be in the settings? + /* I guess this should be in the settings? */ flash_64bit_enable(); flash_prefetch_enable(); /* Configure flash settings. */ @@ -500,7 +503,7 @@ void rcc_clock_setup_hsi(const clock_scale_t *clock) rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_PWREN); pwr_set_vos_scale(clock->voltage_scale); - // I guess this should be in the settings? + /* I guess this should be in the settings? */ flash_64bit_enable(); flash_prefetch_enable(); /* Configure flash settings. */ @@ -528,13 +531,14 @@ void rcc_clock_setup_pll(const clock_scale_t *clock) rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_PWREN); pwr_set_vos_scale(clock->voltage_scale); - // I guess this should be in the settings? + /* I guess this should be in the settings? */ flash_64bit_enable(); flash_prefetch_enable(); /* Configure flash settings. */ flash_set_ws(clock->flash_config); - rcc_set_pll_configuration(clock->pll_source, clock->pll_mul, clock->pll_div); + rcc_set_pll_configuration(clock->pll_source, clock->pll_mul, + clock->pll_div); /* Enable PLL oscillator and wait for it to stabilize. */ rcc_osc_on(PLL); diff --git a/lib/stm32/l1/timer.c b/lib/stm32/l1/timer.c index 053c5015..2d452898 100644 --- a/lib/stm32/l1/timer.c +++ b/lib/stm32/l1/timer.c @@ -41,7 +41,8 @@ Set timer options register on TIM2 or TIM3, used for trigger remapping. @param[in] timer_peripheral Unsigned int32. Timer register address base -@returns Unsigned int32. Option flags TIM2: @ref tim2_opt_trigger_remap, TIM3: @ref tim3_opt_trigger_remap. +@returns Unsigned int32. Option flags TIM2: @ref tim2_opt_trigger_remap, TIM3: +@ref tim3_opt_trigger_remap. */ void timer_set_option(u32 timer_peripheral, u32 option) diff --git a/lib/usb/usb.c b/lib/usb/usb.c index c1b62f60..09e65385 100644 --- a/lib/usb/usb.c +++ b/lib/usb/usb.c @@ -6,7 +6,8 @@ @version 1.0.0 -@author @htmlonly © @endhtmlonly 2010 Gareth McMullin +@author @htmlonly © @endhtmlonly 2010 +Gareth McMullin @date 10 March 2013 @@ -61,8 +62,8 @@ LGPL License Terms @ref lgpl_license * @return Zero on success (currently cannot fail). */ usbd_device *usbd_init(const usbd_driver *driver, - const struct usb_device_descriptor *dev, - const struct usb_config_descriptor *conf, + const struct usb_device_descriptor *dev, + const struct usb_config_descriptor *conf, const char **strings, int num_strings, u8 *control_buffer, u16 control_buffer_size) { @@ -117,8 +118,9 @@ void _usbd_reset(usbd_device *usbd_dev) usbd_ep_setup(usbd_dev, 0, USB_ENDPOINT_ATTR_CONTROL, 64, NULL); usbd_dev->driver->set_address(usbd_dev, 0); - if (usbd_dev->user_callback_reset) + if (usbd_dev->user_callback_reset) { usbd_dev->user_callback_reset(); + } } /* Functions to wrap the low-level driver */ @@ -130,8 +132,9 @@ void usbd_poll(usbd_device *usbd_dev) void usbd_disconnect(usbd_device *usbd_dev, bool disconnected) { /* not all drivers support disconnection */ - if (usbd_dev->driver->disconnect) + if (usbd_dev->driver->disconnect) { usbd_dev->driver->disconnect(usbd_dev, disconnected); + } } void usbd_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size, diff --git a/lib/usb/usb_control.c b/lib/usb/usb_control.c index b387d4b3..4fe9b9d0 100644 --- a/lib/usb/usb_control.c +++ b/lib/usb/usb_control.c @@ -6,7 +6,8 @@ @version 1.0.0 -@author @htmlonly © @endhtmlonly 2010 Gareth McMullin +@author @htmlonly © @endhtmlonly 2010 +Gareth McMullin @date 10 March 2013 @@ -45,8 +46,9 @@ int usbd_register_control_callback(usbd_device *usbd_dev, u8 type, u8 type_mask, int i; for (i = 0; i < MAX_USER_CONTROL_CALLBACK; i++) { - if (usbd_dev->user_control_callback[i].cb) + if (usbd_dev->user_control_callback[i].cb) { continue; + } usbd_dev->user_control_callback[i].type = type; usbd_dev->user_control_callback[i].type_mask = type_mask; @@ -59,7 +61,8 @@ int usbd_register_control_callback(usbd_device *usbd_dev, u8 type, u8 type_mask, static void usb_control_send_chunk(usbd_device *usbd_dev) { - if (usbd_dev->desc->bMaxPacketSize0 < usbd_dev->control_state.ctrl_len) { + if (usbd_dev->desc->bMaxPacketSize0 < + usbd_dev->control_state.ctrl_len) { /* Data stage, normal transmission */ usbd_ep_write_packet(usbd_dev, 0, usbd_dev->control_state.ctrl_buf, @@ -108,8 +111,9 @@ static int usb_control_request_dispatch(usbd_device *usbd_dev, /* Call user command hook function. */ for (i = 0; i < MAX_USER_CONTROL_CALLBACK; i++) { - if (cb[i].cb == NULL) + if (cb[i].cb == NULL) { break; + } if ((req->bmRequestType & cb[i].type_mask) == cb[i].type) { result = cb[i].cb(usbd_dev, req, @@ -117,11 +121,12 @@ static int usb_control_request_dispatch(usbd_device *usbd_dev, &(usbd_dev->control_state.ctrl_len), &(usbd_dev->control_state.complete)); if (result == USBD_REQ_HANDLED || - result == USBD_REQ_NOTSUPP) + result == USBD_REQ_NOTSUPP) { return result; + } } } - + /* Try standard request if not already handled. */ return _usbd_standard_request(usbd_dev, req, &(usbd_dev->control_state.ctrl_buf), @@ -162,10 +167,11 @@ static void usb_control_setup_write(usbd_device *usbd_dev, usbd_dev->control_state.ctrl_buf = usbd_dev->ctrl_buf; usbd_dev->control_state.ctrl_len = 0; /* Wait for DATA OUT stage. */ - if (req->wLength > usbd_dev->desc->bMaxPacketSize0) + if (req->wLength > usbd_dev->desc->bMaxPacketSize0) { usbd_dev->control_state.state = DATA_OUT; - else + } else { usbd_dev->control_state.state = LAST_DATA_OUT; + } } /* Do not appear to belong to the API, so are omitted from docs */ @@ -198,16 +204,19 @@ void _usbd_control_out(usbd_device *usbd_dev, u8 ea) switch (usbd_dev->control_state.state) { case DATA_OUT: - if (usb_control_recv_chunk(usbd_dev) < 0) + if (usb_control_recv_chunk(usbd_dev) < 0) { break; + } if ((usbd_dev->control_state.req.wLength - usbd_dev->control_state.ctrl_len) <= - usbd_dev->desc->bMaxPacketSize0) + usbd_dev->desc->bMaxPacketSize0) { usbd_dev->control_state.state = LAST_DATA_OUT; + } break; case LAST_DATA_OUT: - if (usb_control_recv_chunk(usbd_dev) < 0) + if (usb_control_recv_chunk(usbd_dev) < 0) { break; + } /* * We have now received the full data payload. * Invoke callback to process. @@ -224,9 +233,10 @@ void _usbd_control_out(usbd_device *usbd_dev, u8 ea) case STATUS_OUT: usbd_ep_read_packet(usbd_dev, 0, NULL, 0); usbd_dev->control_state.state = IDLE; - if (usbd_dev->control_state.complete) + if (usbd_dev->control_state.complete) { usbd_dev->control_state.complete(usbd_dev, &(usbd_dev->control_state.req)); + } usbd_dev->control_state.complete = NULL; break; default: @@ -247,14 +257,16 @@ void _usbd_control_in(usbd_device *usbd_dev, u8 ea) usbd_dev->control_state.state = STATUS_OUT; break; case STATUS_IN: - if (usbd_dev->control_state.complete) + if (usbd_dev->control_state.complete) { usbd_dev->control_state.complete(usbd_dev, &(usbd_dev->control_state.req)); + } /* Exception: Handle SET ADDRESS function here... */ if ((req->bmRequestType == 0) && - (req->bRequest == USB_REQ_SET_ADDRESS)) + (req->bRequest == USB_REQ_SET_ADDRESS)) { usbd_dev->driver->set_address(usbd_dev, req->wValue); + } usbd_dev->control_state.state = IDLE; break; default: diff --git a/lib/usb/usb_f103.c b/lib/usb/usb_f103.c index ec98f357..ffab2953 100644 --- a/lib/usb/usb_f103.c +++ b/lib/usb/usb_f103.c @@ -86,12 +86,14 @@ static void usb_set_ep_rx_bufsize(usbd_device *dev, u8 ep, u32 size) { (void)dev; if (size > 62) { - if (size & 0x1f) + if (size & 0x1f) { size -= 32; + } USB_SET_EP_RX_COUNT(ep, (size << 5) | 0x8000); } else { - if (size & 1) + if (size & 1) { size++; + } USB_SET_EP_RX_COUNT(ep, size << 10); } } @@ -153,9 +155,10 @@ static void stm32f103_endpoints_reset(usbd_device *dev) static void stm32f103_ep_stall_set(usbd_device *dev, u8 addr, u8 stall) { (void)dev; - if (addr == 0) + if (addr == 0) { USB_SET_EP_TX_STAT(addr, stall ? USB_EP_TX_STAT_STALL : USB_EP_TX_STAT_NAK); + } if (addr & 0x80) { addr &= 0x7F; @@ -164,12 +167,14 @@ static void stm32f103_ep_stall_set(usbd_device *dev, u8 addr, u8 stall) USB_EP_TX_STAT_NAK); /* Reset to DATA0 if clearing stall condition. */ - if (!stall) + if (!stall) { USB_CLR_EP_TX_DTOG(addr); + } } else { /* Reset to DATA0 if clearing stall condition. */ - if (!stall) + if (!stall) { USB_CLR_EP_RX_DTOG(addr); + } USB_SET_EP_RX_STAT(addr, stall ? USB_EP_RX_STAT_STALL : USB_EP_RX_STAT_VALID); @@ -195,13 +200,15 @@ static void stm32f103_ep_nak_set(usbd_device *dev, u8 addr, u8 nak) { (void)dev; /* It does not make sence to force NAK on IN endpoints. */ - if (addr & 0x80) + if (addr & 0x80) { return; + } force_nak[addr] = nak; - if (nak) + if (nak) { USB_SET_EP_RX_STAT(addr, USB_EP_RX_STAT_NAK); + } else USB_SET_EP_RX_STAT(addr, USB_EP_RX_STAT_VALID); } @@ -218,8 +225,9 @@ static void usb_copy_to_pm(volatile void *vPM, const void *buf, u16 len) const u16 *lbuf = buf; volatile u16 *PM = vPM; - for (len = (len + 1) >> 1; len; PM += 2, lbuf++, len--) + for (len = (len + 1) >> 1; len; PM += 2, lbuf++, len--) { *PM = *lbuf; + } } static u16 stm32f103_ep_write_packet(usbd_device *dev, u8 addr, @@ -228,8 +236,9 @@ static u16 stm32f103_ep_write_packet(usbd_device *dev, u8 addr, (void)dev; addr &= 0x7F; - if ((*USB_EP_REG(addr) & USB_EP_TX_STAT) == USB_EP_TX_STAT_VALID) + if ((*USB_EP_REG(addr) & USB_EP_TX_STAT) == USB_EP_TX_STAT_VALID) { return 0; + } usb_copy_to_pm(USB_GET_EP_TX_BUFF(addr), buf, len); USB_SET_EP_TX_COUNT(addr, len); @@ -251,26 +260,30 @@ static void usb_copy_from_pm(void *buf, const volatile void *vPM, u16 len) const volatile u16 *PM = vPM; u8 odd = len & 1; - for (len >>= 1; len; PM += 2, lbuf++, len--) + for (len >>= 1; len; PM += 2, lbuf++, len--) { *lbuf = *PM; + } - if (odd) + if (odd) { *(u8 *) lbuf = *(u8 *) PM; + } } static u16 stm32f103_ep_read_packet(usbd_device *dev, u8 addr, void *buf, u16 len) { (void)dev; - if ((*USB_EP_REG(addr) & USB_EP_RX_STAT) == USB_EP_RX_STAT_VALID) + if ((*USB_EP_REG(addr) & USB_EP_RX_STAT) == USB_EP_RX_STAT_VALID) { return 0; + } len = MIN(USB_GET_EP_RX_COUNT(addr) & 0x3ff, len); usb_copy_from_pm(buf, USB_GET_EP_RX_BUFF(addr), len); USB_CLR_EP_RX_CTR(addr); - if (!force_nak[addr]) + if (!force_nak[addr]) { USB_SET_EP_RX_STAT(addr, USB_EP_RX_STAT_VALID); + } return len; } @@ -295,27 +308,31 @@ static void stm32f103_poll(usbd_device *dev) else /* IN transaction */ USB_CLR_EP_TX_CTR(ep); - if (dev->user_callback_ctr[ep][type]) + if (dev->user_callback_ctr[ep][type]) { dev->user_callback_ctr[ep][type] (dev, ep); - else + } else { USB_CLR_EP_RX_CTR(ep); + } } if (istr & USB_ISTR_SUSP) { USB_CLR_ISTR_SUSP(); - if (dev->user_callback_suspend) + if (dev->user_callback_suspend) { dev->user_callback_suspend(); + } } if (istr & USB_ISTR_WKUP) { USB_CLR_ISTR_WKUP(); - if (dev->user_callback_resume) + if (dev->user_callback_resume) { dev->user_callback_resume(); + } } if (istr & USB_ISTR_SOF) { - if (dev->user_callback_sof) + if (dev->user_callback_sof) { dev->user_callback_sof(); + } USB_CLR_ISTR_SOF(); } } diff --git a/lib/usb/usb_f107.c b/lib/usb/usb_f107.c index 009979d6..32aecab6 100644 --- a/lib/usb/usb_f107.c +++ b/lib/usb/usb_f107.c @@ -59,10 +59,10 @@ static usbd_device *stm32f107_usbd_init(void) OTG_FS_GCCFG |= OTG_FS_GCCFG_VBUSBSEN | OTG_FS_GCCFG_PWRDWN; /* Wait for AHB idle. */ - while (!(OTG_FS_GRSTCTL & OTG_FS_GRSTCTL_AHBIDL)) ; + while (!(OTG_FS_GRSTCTL & OTG_FS_GRSTCTL_AHBIDL)); /* Do core soft reset. */ OTG_FS_GRSTCTL |= OTG_FS_GRSTCTL_CSRST; - while (OTG_FS_GRSTCTL & OTG_FS_GRSTCTL_CSRST) ; + while (OTG_FS_GRSTCTL & OTG_FS_GRSTCTL_CSRST); /* Force peripheral only mode. */ OTG_FS_GUSBCFG |= OTG_FS_GUSBCFG_FDMOD | OTG_FS_GUSBCFG_TRDT_MASK; diff --git a/lib/usb/usb_f207.c b/lib/usb/usb_f207.c index b2509e5e..b27d3cd2 100644 --- a/lib/usb/usb_f207.c +++ b/lib/usb/usb_f207.c @@ -59,10 +59,10 @@ static usbd_device *stm32f207_usbd_init(void) OTG_HS_GCCFG |= OTG_HS_GCCFG_VBUSBSEN | OTG_HS_GCCFG_PWRDWN; /* Wait for AHB idle. */ - while (!(OTG_HS_GRSTCTL & OTG_HS_GRSTCTL_AHBIDL)) ; + while (!(OTG_HS_GRSTCTL & OTG_HS_GRSTCTL_AHBIDL)); /* Do core soft reset. */ OTG_HS_GRSTCTL |= OTG_HS_GRSTCTL_CSRST; - while (OTG_HS_GRSTCTL & OTG_HS_GRSTCTL_CSRST) ; + while (OTG_HS_GRSTCTL & OTG_HS_GRSTCTL_CSRST); /* Force peripheral only mode. */ OTG_HS_GUSBCFG |= OTG_HS_GUSBCFG_FDMOD | OTG_HS_GUSBCFG_TRDT_MASK; diff --git a/lib/usb/usb_fx07_common.c b/lib/usb/usb_fx07_common.c index 9178092c..ae5df9fe 100644 --- a/lib/usb/usb_fx07_common.c +++ b/lib/usb/usb_fx07_common.c @@ -29,9 +29,9 @@ /* The FS core and the HS core have the same register layout. * As the code can be used on both cores, the registers offset is modified * according to the selected cores base address. */ -#define dev_base_address (usbd_dev->driver->base_address) -#define REBASE(x) MMIO32((x)+(dev_base_address)) -#define REBASE_FIFO(x) ((volatile u32*)((dev_base_address) + (OTG_FIFO(x)))) +#define dev_base_address (usbd_dev->driver->base_address) +#define REBASE(x) MMIO32((x)+(dev_base_address)) +#define REBASE_FIFO(x) ((volatile u32*)((dev_base_address) + (OTG_FIFO(x)))) void stm32fx07_set_address(usbd_device *usbd_dev, u8 addr) { @@ -59,6 +59,7 @@ void stm32fx07_ep_setup(usbd_device *usbd_dev, u8 addr, u8 type, u16 max_size, } else { REBASE(OTG_DIEPCTL0) = OTG_FS_DIEPCTL0_MPSIZ_8; } + REBASE(OTG_DIEPTSIZ0) = (max_size & OTG_FS_DIEPSIZ0_XFRSIZ_MASK); REBASE(OTG_DIEPCTL0) |= @@ -122,10 +123,11 @@ void stm32fx07_endpoints_reset(usbd_device *usbd_dev) void stm32fx07_ep_stall_set(usbd_device *usbd_dev, u8 addr, u8 stall) { if (addr == 0) { - if (stall) + if (stall) { REBASE(OTG_DIEPCTL(addr)) |= OTG_FS_DIEPCTL0_STALL; - else + } else { REBASE(OTG_DIEPCTL(addr)) &= ~OTG_FS_DIEPCTL0_STALL; + } } if (addr & 0x80) { @@ -150,26 +152,29 @@ void stm32fx07_ep_stall_set(usbd_device *usbd_dev, u8 addr, u8 stall) u8 stm32fx07_ep_stall_get(usbd_device *usbd_dev, u8 addr) { /* Return non-zero if STALL set. */ - if (addr & 0x80) + if (addr & 0x80) { return (REBASE(OTG_DIEPCTL(addr & 0x7f)) & OTG_FS_DIEPCTL0_STALL) ? 1 : 0; - else + } else { return (REBASE(OTG_DOEPCTL(addr)) & OTG_FS_DOEPCTL0_STALL) ? 1 : 0; + } } void stm32fx07_ep_nak_set(usbd_device *usbd_dev, u8 addr, u8 nak) { /* It does not make sence to force NAK on IN endpoints. */ - if (addr & 0x80) + if (addr & 0x80) { return; + } usbd_dev->force_nak[addr] = nak; - if (nak) + if (nak) { REBASE(OTG_DOEPCTL(addr)) |= OTG_FS_DOEPCTL0_SNAK; - else + } else { REBASE(OTG_DOEPCTL(addr)) |= OTG_FS_DOEPCTL0_CNAK; + } } u16 stm32fx07_ep_write_packet(usbd_device *usbd_dev, u8 addr, @@ -181,8 +186,9 @@ u16 stm32fx07_ep_write_packet(usbd_device *usbd_dev, u8 addr, addr &= 0x7F; /* Return if endpoint is already enabled. */ - if (REBASE(OTG_DIEPTSIZ(addr)) & OTG_FS_DIEPSIZ0_PKTCNT) + if (REBASE(OTG_DIEPTSIZ(addr)) & OTG_FS_DIEPSIZ0_PKTCNT) { return 0; + } /* Enable endpoint for transmission. */ REBASE(OTG_DIEPTSIZ(addr)) = OTG_FS_DIEPSIZ0_PKTCNT | len; @@ -191,8 +197,9 @@ u16 stm32fx07_ep_write_packet(usbd_device *usbd_dev, u8 addr, volatile u32 *fifo = REBASE_FIFO(addr); /* Copy buffer to endpoint FIFO, note - memcpy does not work */ - for (i = len; i > 0; i -= 4) + for (i = len; i > 0; i -= 4) { *fifo++ = *buf32++; + } return len; } @@ -207,8 +214,9 @@ u16 stm32fx07_ep_read_packet(usbd_device *usbd_dev, u8 addr, void *buf, u16 len) usbd_dev->rxbcnt -= len; volatile u32 *fifo = REBASE_FIFO(addr); - for (i = len; i >= 4; i -= 4) + for (i = len; i >= 4; i -= 4) { *buf32++ = *fifo++; + } if (i) { extra = *fifo++; @@ -243,15 +251,17 @@ void stm32fx07_poll(usbd_device *usbd_dev) u32 rxstsp = REBASE(OTG_GRXSTSP); u32 pktsts = rxstsp & OTG_FS_GRXSTSP_PKTSTS_MASK; if ((pktsts != OTG_FS_GRXSTSP_PKTSTS_OUT) && - (pktsts != OTG_FS_GRXSTSP_PKTSTS_SETUP)) + (pktsts != OTG_FS_GRXSTSP_PKTSTS_SETUP)) { return; + } u8 ep = rxstsp & OTG_FS_GRXSTSP_EPNUM_MASK; u8 type; - if (pktsts == OTG_FS_GRXSTSP_PKTSTS_SETUP) + if (pktsts == OTG_FS_GRXSTSP_PKTSTS_SETUP) { type = USB_TRANSACTION_SETUP; - else + } else { type = USB_TRANSACTION_OUT; + } /* Save packet size for stm32f107_ep_read_packet(). */ usbd_dev->rxbcnt = (rxstsp & OTG_FS_GRXSTSP_BCNT_MASK) >> 4; @@ -261,15 +271,18 @@ void stm32fx07_poll(usbd_device *usbd_dev) * This appears to fix a problem where the first 4 bytes * of the DATA OUT stage of a control transaction are lost. */ - for (i = 0; i < 1000; i++) + for (i = 0; i < 1000; i++) { __asm__("nop"); + } - if (usbd_dev->user_callback_ctr[ep][type]) + if (usbd_dev->user_callback_ctr[ep][type]) { usbd_dev->user_callback_ctr[ep][type] (usbd_dev, ep); + } /* Discard unread packet data. */ - for (i = 0; i < usbd_dev->rxbcnt; i += 4) + for (i = 0; i < usbd_dev->rxbcnt; i += 4) { (void)*REBASE_FIFO(ep); + } usbd_dev->rxbcnt = 0; } @@ -281,29 +294,33 @@ void stm32fx07_poll(usbd_device *usbd_dev) for (i = 0; i < 4; i++) { /* Iterate over endpoints. */ if (REBASE(OTG_DIEPINT(i)) & OTG_FS_DIEPINTX_XFRC) { /* Transfer complete. */ - if (usbd_dev->user_callback_ctr[i][USB_TRANSACTION_IN]) + if (usbd_dev->user_callback_ctr[i][USB_TRANSACTION_IN]) { usbd_dev->user_callback_ctr[i] [USB_TRANSACTION_IN](usbd_dev, i); + } REBASE(OTG_DIEPINT(i)) = OTG_FS_DIEPINTX_XFRC; } } if (intsts & OTG_FS_GINTSTS_USBSUSP) { - if (usbd_dev->user_callback_suspend) + if (usbd_dev->user_callback_suspend) { usbd_dev->user_callback_suspend(); + } REBASE(OTG_GINTSTS) = OTG_FS_GINTSTS_USBSUSP; } if (intsts & OTG_FS_GINTSTS_WKUPINT) { - if (usbd_dev->user_callback_resume) + if (usbd_dev->user_callback_resume) { usbd_dev->user_callback_resume(); + } REBASE(OTG_GINTSTS) = OTG_FS_GINTSTS_WKUPINT; } if (intsts & OTG_FS_GINTSTS_SOF) { - if (usbd_dev->user_callback_sof) + if (usbd_dev->user_callback_sof) { usbd_dev->user_callback_sof(); + } REBASE(OTG_GINTSTS) = OTG_FS_GINTSTS_SOF; } } diff --git a/lib/usb/usb_private.h b/lib/usb/usb_private.h index dcf14875..1c293875 100644 --- a/lib/usb/usb_private.h +++ b/lib/usb/usb_private.h @@ -39,7 +39,7 @@ LGPL License Terms @ref lgpl_license #define MAX_USER_CONTROL_CALLBACK 4 -#define MIN(a, b) ((a)<(b) ? (a) : (b)) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) /** Internal collection of device information. */ struct _usbd_device { @@ -68,7 +68,7 @@ struct _usbd_device { DATA_IN, LAST_DATA_IN, STATUS_IN, DATA_OUT, LAST_DATA_OUT, STATUS_OUT, } state; - struct usb_setup_data req __attribute__((aligned(4))); + struct usb_setup_data req __aligned(4); u8 *ctrl_buf; u16 ctrl_len; void (*complete)(usbd_device *usbd_dev, @@ -92,18 +92,18 @@ struct _usbd_device { uint16_t fifo_mem_top; uint16_t fifo_mem_top_ep0; - u8 force_nak[4]; - /* - * We keep a backup copy of the out endpoint size registers to restore them - * after a transaction. - */ - u32 doeptsiz[4]; - /* - * Received packet size for each endpoint. This is assigned in - * stm32f107_poll() which reads the packet status push register GRXSTSP - * for use in stm32f107_ep_read_packet(). - */ - uint16_t rxbcnt; + u8 force_nak[4]; + /* + * We keep a backup copy of the out endpoint size registers to restore + * them after a transaction. + */ + u32 doeptsiz[4]; + /* + * Received packet size for each endpoint. This is assigned in + * stm32f107_poll() which reads the packet status push register GRXSTSP + * for use in stm32f107_ep_read_packet(). + */ + uint16_t rxbcnt; }; enum _usbd_transaction { diff --git a/lib/usb/usb_standard.c b/lib/usb/usb_standard.c index aebc4c0d..7ebec045 100644 --- a/lib/usb/usb_standard.c +++ b/lib/usb/usb_standard.c @@ -6,7 +6,8 @@ @version 1.0.0 -@author @htmlonly © @endhtmlonly 2010 Gareth McMullin +@author @htmlonly © @endhtmlonly 2010 +Gareth McMullin @date 10 March 2013 @@ -40,7 +41,7 @@ LGPL License Terms @ref lgpl_license void usbd_register_set_config_callback(usbd_device *usbd_dev, void (*callback)(usbd_device *usbd_dev, - u16 wValue)) + u16 wValue)) { usbd_dev->user_callback_set_config = callback; } @@ -141,33 +142,43 @@ static int usb_standard_get_descriptor(usbd_device *usbd_dev, if (descr_idx == 0) { /* Send sane Language ID descriptor... */ sd->wData[0] = USB_LANGID_ENGLISH_US; - sd->bLength = sizeof(sd->bLength) + sizeof(sd->bDescriptorType) - + sizeof(sd->wData[0]); + sd->bLength = sizeof(sd->bLength) + + sizeof(sd->bDescriptorType) + + sizeof(sd->wData[0]); *len = MIN(*len, sd->bLength); } else { array_idx = descr_idx - 1; - if (!usbd_dev->strings) - return USBD_REQ_NOTSUPP; /* Device doesn't support strings. */ - /* Check that string index is in range. */ - if (array_idx >= usbd_dev->num_strings) + if (!usbd_dev->strings) { + /* Device doesn't support strings. */ return USBD_REQ_NOTSUPP; + } + + /* Check that string index is in range. */ + if (array_idx >= usbd_dev->num_strings) { + return USBD_REQ_NOTSUPP; + } /* Strings with Language ID differnet from * USB_LANGID_ENGLISH_US are not supported */ - if (req->wIndex != USB_LANGID_ENGLISH_US) + if (req->wIndex != USB_LANGID_ENGLISH_US) { return USBD_REQ_NOTSUPP; + } - /* Ths string is returned as UTF16, hence the multiplication */ + /* Ths string is returned as UTF16, hence the + * multiplication + */ sd->bLength = strlen(usbd_dev->strings[array_idx]) * 2 + - sizeof(sd->bLength) + sizeof(sd->bDescriptorType); + sizeof(sd->bLength) + + sizeof(sd->bDescriptorType); *len = MIN(*len, sd->bLength); - for (i = 0; i < (*len / 2) - 1; i++) + for (i = 0; i < (*len / 2) - 1; i++) { sd->wData[i] = usbd_dev->strings[array_idx][i]; + } } sd->bDescriptorType = USB_DT_STRING; @@ -187,8 +198,9 @@ static int usb_standard_set_address(usbd_device *usbd_dev, (void)len; /* The actual address is only latched at the STATUS IN stage. */ - if ((req->bmRequestType != 0) || (req->wValue >= 128)) + if ((req->bmRequestType != 0) || (req->wValue >= 128)) { return 0; + } usbd_dev->current_address = req->wValue; @@ -196,8 +208,9 @@ static int usb_standard_set_address(usbd_device *usbd_dev, * Special workaround for STM32F10[57] that require the address * to be set here. This is undocumented! */ - if ( usbd_dev->driver->set_address_before_status) + if (usbd_dev->driver->set_address_before_status) { usbd_dev->driver->set_address(usbd_dev, req->wValue); + } return 1; } @@ -213,8 +226,9 @@ static int usb_standard_set_configuration(usbd_device *usbd_dev, (void)len; /* Is this correct, or should we reset alternate settings. */ - if (req->wValue == usbd_dev->current_config) + if (req->wValue == usbd_dev->current_config) { return 1; + } usbd_dev->current_config = req->wValue; @@ -226,8 +240,9 @@ static int usb_standard_set_configuration(usbd_device *usbd_dev, * Flush control callbacks. These will be reregistered * by the user handler. */ - for (i = 0; i < MAX_USER_CONTROL_CALLBACK; i++) + for (i = 0; i < MAX_USER_CONTROL_CALLBACK; i++) { usbd_dev->user_control_callback[i].cb = NULL; + } usbd_dev->user_callback_set_config(usbd_dev, req->wValue); } @@ -241,8 +256,9 @@ static int usb_standard_get_configuration(usbd_device *usbd_dev, { (void)req; - if (*len > 1) + if (*len > 1) { *len = 1; + } (*buf)[0] = usbd_dev->current_config; return 1; @@ -257,8 +273,9 @@ static int usb_standard_set_interface(usbd_device *usbd_dev, (void)buf; /* FIXME: Adapt if we have more than one interface. */ - if (req->wValue != 0) + if (req->wValue != 0) { return 0; + } *len = 0; return 1; @@ -288,8 +305,9 @@ static int usb_standard_device_get_status(usbd_device *usbd_dev, /* bit 0: self powered */ /* bit 1: remote wakeup */ - if (*len > 2) + if (*len > 2) { *len = 2; + } (*buf)[0] = 0; (*buf)[1] = 0; @@ -304,8 +322,9 @@ static int usb_standard_interface_get_status(usbd_device *usbd_dev, (void)req; /* not defined */ - if (*len > 2) + if (*len > 2) { *len = 2; + } (*buf)[0] = 0; (*buf)[1] = 0; @@ -318,8 +337,9 @@ static int usb_standard_endpoint_get_status(usbd_device *usbd_dev, { (void)req; - if (*len > 2) + if (*len > 2) { *len = 2; + } (*buf)[0] = usbd_ep_stall_get(usbd_dev, req->wIndex) ? 1 : 0; (*buf)[1] = 0; @@ -366,9 +386,11 @@ int _usbd_standard_request_device(usbd_device *usbd_dev, if (req->wValue == USB_FEAT_DEVICE_REMOTE_WAKEUP) { /* Device wakeup code goes here. */ } + if (req->wValue == USB_FEAT_TEST_MODE) { /* Test mode code goes here. */ } + break; case USB_REQ_SET_ADDRESS: /* @@ -398,8 +420,9 @@ int _usbd_standard_request_device(usbd_device *usbd_dev, break; } - if (!command) + if (!command) { return 0; + } return command(usbd_dev, req, buf, len); } @@ -427,8 +450,9 @@ int _usbd_standard_request_interface(usbd_device *usbd_dev, break; } - if (!command) + if (!command) { return 0; + } return command(usbd_dev, req, buf, len); } @@ -442,12 +466,14 @@ int _usbd_standard_request_endpoint(usbd_device *usbd_dev, switch (req->bRequest) { case USB_REQ_CLEAR_FEATURE: - if (req->wValue == USB_FEAT_ENDPOINT_HALT) + if (req->wValue == USB_FEAT_ENDPOINT_HALT) { command = usb_standard_endpoint_unstall; + } break; case USB_REQ_SET_FEATURE: - if (req->wValue == USB_FEAT_ENDPOINT_HALT) + if (req->wValue == USB_FEAT_ENDPOINT_HALT) { command = usb_standard_endpoint_stall; + } break; case USB_REQ_GET_STATUS: command = usb_standard_endpoint_get_status; @@ -461,8 +487,9 @@ int _usbd_standard_request_endpoint(usbd_device *usbd_dev, break; } - if (!command) + if (!command) { return 0; + } return command(usbd_dev, req, buf, len); } @@ -471,8 +498,9 @@ int _usbd_standard_request(usbd_device *usbd_dev, struct usb_setup_data *req, u8 **buf, u16 *len) { /* FIXME: Have class/vendor requests as well. */ - if ((req->bmRequestType & USB_REQ_TYPE_TYPE) != USB_REQ_TYPE_STANDARD) + if ((req->bmRequestType & USB_REQ_TYPE_TYPE) != USB_REQ_TYPE_STANDARD) { return 0; + } switch (req->bmRequestType & USB_REQ_TYPE_RECIPIENT) { case USB_REQ_TYPE_DEVICE: diff --git a/scripts/irq2nvic_h b/scripts/irq2nvic_h index d1a8a40f..7f57d43e 100755 --- a/scripts/irq2nvic_h +++ b/scripts/irq2nvic_h @@ -53,8 +53,6 @@ template_nvic_h = '''\ /**@}}*/ -#define WEAK __attribute__ ((weak)) - /** @defgroup CM3_nvic_isrprototypes_{partname_doxygen} User interrupt service routines (ISR) prototypes for {partname_humanreadable} @ingroup CM3_nvic_isrprototypes