jackcartersmith/blackmagic
1
0
Fork 0
Code Issues Pull Requests Releases Activity

cm3: extract SCB SHPR to the SCB world it belongs to

Browse Source 
Pull out the duplicate into the right file, keeping the newly fixed
version.
This commit is contained in:
Karl Palsson 2019-10-18 22:33:23 +00:00
parent 3ebd71b464
commit 833da4b672
3 changed files with 12 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
include/libopencm3/cm3/scb.h
View File

@ -52,13 +52,16 @@
/** CCR: Configuration Control Register */
#define SCB_CCR MMIO32(SCB_BASE + 0x14)
/** SHP: System Handler Priority Registers.
* Note: 12 8bit registers
/** System Handler Priority 8 bits Registers, SHPR1/2/3.
* @note: 12 8bit Registers
* @note: 2 32bit Registers on CM0, requires word access,
* (shpr1 doesn't actually exist)
*/
#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + (shpr_id))
#define SCB_SHPR1 MMIO32(SCB_BASE + 0x18)
#define SCB_SHPR2 MMIO32(SCB_BASE + 0x1C)
#define SCB_SHPR3 MMIO32(SCB_BASE + 0x20)
#if defined(__ARM_ARCH_6M__)
#define SCB_SHPR32(ipr_id) MMIO32(SCS_BASE + 0xD18 + ((ipr_id) * 4))
#else
#define SCB_SHPR(ipr_id) MMIO8(SCS_BASE + 0xD18 + (ipr_id))
#endif
/** SHCSR: System Handler Control and State Register */
#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)

11
include/libopencm3/cm3/scs.h
View File

@ -50,17 +50,6 @@
* @{
*/
/** System Handler Priority 8 bits Registers, SHPR1/2/3.
* Note: 12 8bit Registers
* Note: 3 32bit Registers on CM0, requires word access
*/
#if defined(__ARM_ARCH_6M__)
#define SCS_SHPR32(ipr_id) MMIO32(SCS_BASE + 0xD18 + ((ipr_id) * 4))
#else
#define SCS_SHPR(ipr_id) MMIO8(SCS_BASE + 0xD18 + (ipr_id))
#endif
/**
* Debug Halting Control and Status Register (DHCSR).
*

6
lib/cm3/nvic.c
View File

@ -44,7 +44,7 @@
/**@{*/
#include <libopencm3/cm3/nvic.h>
#include <libopencm3/cm3/scs.h>
#include <libopencm3/cm3/scb.h>
/*---------------------------------------------------------------------------*/
/** @brief NVIC Enable Interrupt
@ -161,10 +161,10 @@ void nvic_set_priority(uint8_t irqn, uint8_t priority)
irqn = (irqn & 0xF) - 4;
uint8_t shift = (irqn & 0x3) << 3;
uint8_t reg = irqn >> 2;
SCS_SHPR32(reg) = ((SCS_SHPR32(reg) & ~(0xFFUL << shift)) |
SCB_SHPR32(reg) = ((SCB_SHPR32(reg) & ~(0xFFUL << shift)) |
((uint32_t) priority) << shift);
#else
SCS_SHPR((irqn & 0xF) - 4) = priority;
SCB_SHPR((irqn & 0xF) - 4) = priority;
#endif
} else {
/* Device specific interrupts */