cm3: extract SCB SHPR to the SCB world it belongs to
Pull out the duplicate into the right file, keeping the newly fixed version.
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@ -52,13 +52,16 @@
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/** CCR: Configuration Control Register */
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/** CCR: Configuration Control Register */
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#define SCB_CCR MMIO32(SCB_BASE + 0x14)
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#define SCB_CCR MMIO32(SCB_BASE + 0x14)
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/** SHP: System Handler Priority Registers.
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/** System Handler Priority 8 bits Registers, SHPR1/2/3.
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* Note: 12 8bit registers
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* @note: 12 8bit Registers
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* @note: 2 32bit Registers on CM0, requires word access,
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* (shpr1 doesn't actually exist)
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*/
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*/
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#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + (shpr_id))
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#if defined(__ARM_ARCH_6M__)
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#define SCB_SHPR1 MMIO32(SCB_BASE + 0x18)
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#define SCB_SHPR32(ipr_id) MMIO32(SCS_BASE + 0xD18 + ((ipr_id) * 4))
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#define SCB_SHPR2 MMIO32(SCB_BASE + 0x1C)
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#else
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#define SCB_SHPR3 MMIO32(SCB_BASE + 0x20)
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#define SCB_SHPR(ipr_id) MMIO8(SCS_BASE + 0xD18 + (ipr_id))
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#endif
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/** SHCSR: System Handler Control and State Register */
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/** SHCSR: System Handler Control and State Register */
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#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
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#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
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@ -50,17 +50,6 @@
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* @{
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* @{
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*/
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*/
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/** System Handler Priority 8 bits Registers, SHPR1/2/3.
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* Note: 12 8bit Registers
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* Note: 3 32bit Registers on CM0, requires word access
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*/
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#if defined(__ARM_ARCH_6M__)
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#define SCS_SHPR32(ipr_id) MMIO32(SCS_BASE + 0xD18 + ((ipr_id) * 4))
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#else
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#define SCS_SHPR(ipr_id) MMIO8(SCS_BASE + 0xD18 + (ipr_id))
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#endif
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/**
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/**
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* Debug Halting Control and Status Register (DHCSR).
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* Debug Halting Control and Status Register (DHCSR).
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*
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*
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@ -44,7 +44,7 @@
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/**@{*/
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/**@{*/
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#include <libopencm3/cm3/nvic.h>
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#include <libopencm3/cm3/nvic.h>
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#include <libopencm3/cm3/scs.h>
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#include <libopencm3/cm3/scb.h>
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/*---------------------------------------------------------------------------*/
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/*---------------------------------------------------------------------------*/
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/** @brief NVIC Enable Interrupt
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/** @brief NVIC Enable Interrupt
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@ -161,10 +161,10 @@ void nvic_set_priority(uint8_t irqn, uint8_t priority)
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irqn = (irqn & 0xF) - 4;
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irqn = (irqn & 0xF) - 4;
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uint8_t shift = (irqn & 0x3) << 3;
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uint8_t shift = (irqn & 0x3) << 3;
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uint8_t reg = irqn >> 2;
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uint8_t reg = irqn >> 2;
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SCS_SHPR32(reg) = ((SCS_SHPR32(reg) & ~(0xFFUL << shift)) |
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SCB_SHPR32(reg) = ((SCB_SHPR32(reg) & ~(0xFFUL << shift)) |
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((uint32_t) priority) << shift);
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((uint32_t) priority) << shift);
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#else
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#else
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SCS_SHPR((irqn & 0xF) - 4) = priority;
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SCB_SHPR((irqn & 0xF) - 4) = priority;
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#endif
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#endif
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} else {
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} else {
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/* Device specific interrupts */
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/* Device specific interrupts */
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