cosmetic
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17dca6f791
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@ -47,51 +47,27 @@ extern const struct command_s stm32f1_cmd_list[]; // Reuse stm32f1 stuff
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static int ch32f1_flash_write(struct target_flash *f,
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static int ch32f1_flash_write(struct target_flash *f,
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target_addr dest, const void *src, size_t len);
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target_addr dest, const void *src, size_t len);
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// these are common with stm32f1/gd32f1/...
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#define FPEC_BASE 0x40022000
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#define FPEC_BASE 0x40022000
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#define FLASH_ACR (FPEC_BASE+0x00)
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#define FLASH_ACR (FPEC_BASE+0x00)
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#define FLASH_KEYR (FPEC_BASE+0x04)
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#define FLASH_KEYR (FPEC_BASE+0x04)
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#define FLASH_OPTKEYR (FPEC_BASE+0x08)
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#define FLASH_SR (FPEC_BASE+0x0C)
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#define FLASH_SR (FPEC_BASE+0x0C)
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#define FLASH_CR (FPEC_BASE+0x10)
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#define FLASH_CR (FPEC_BASE+0x10)
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#define FLASH_AR (FPEC_BASE+0x14)
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#define FLASH_AR (FPEC_BASE+0x14)
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#define FLASH_OBR (FPEC_BASE+0x1C)
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#define FLASH_WRPR (FPEC_BASE+0x20)
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#define FLASH_BANK2_OFFSET 0x40
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#define FLASH_BANK_SPLIT 0x08080000
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#define FLASH_CR_OBL_LAUNCH (1<<13)
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#define FLASH_CR_OPTWRE (1 << 9)
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#define FLASH_CR_LOCK (1 << 7)
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#define FLASH_CR_LOCK (1 << 7)
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#define FLASH_CR_STRT (1 << 6)
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#define FLASH_CR_STRT (1 << 6)
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#define FLASH_CR_OPTER (1 << 5)
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#define FLASH_CR_OPTPG (1 << 4)
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#define FLASH_CR_MER (1 << 2)
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#define FLASH_CR_PER (1 << 1)
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#define FLASH_CR_PG (1 << 0)
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#define FLASH_OBR_RDPRT (1 << 1)
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#define FLASH_SR_BSY (1 << 0)
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#define FLASH_SR_BSY (1 << 0)
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#define FLASH_OBP_RDP 0x1FFFF800
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#define FLASH_OBP_RDP_KEY 0x5aa5
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#define FLASH_OBP_RDP_KEY_F3 0x55AA
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#define KEY1 0x45670123
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#define KEY1 0x45670123
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#define KEY2 0xCDEF89AB
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#define KEY2 0xCDEF89AB
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#define SR_ERROR_MASK 0x14
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#define SR_ERROR_MASK 0x14
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#define SR_EOP 0x20
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#define SR_EOP 0x20
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#define DBGMCU_IDCODE 0xE0042000
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#define DBGMCU_IDCODE 0xE0042000
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#define DBGMCU_IDCODE_F0 0x40015800
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#define FLASHSIZE 0x1FFFF7E0
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#define FLASHSIZE 0x1FFFF7E0
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#define FLASHSIZE_F0 0x1FFFF7CC
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// these are specific to ch32f1
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#define FLASH_MAGIC (FPEC_BASE+0x34)
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#define FLASH_MODEKEYR_CH32 (FPEC_BASE+0x24) // Fast mode for CH32F10x
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#define FLASH_MODEKEYR_CH32 (FPEC_BASE+0x24) // Fast mode for CH32F10x
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#define FLASH_CR_FLOCK_CH32 (1<<15) // fast unlock
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#define FLASH_CR_FLOCK_CH32 (1<<15) // fast unlock
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#define FLASH_CR_FTPG_CH32 (1<<16) // fast page program
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#define FLASH_CR_FTPG_CH32 (1<<16) // fast page program
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#define FLASH_CR_FTER_CH32 (1<<17) // fast page erase
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#define FLASH_CR_FTER_CH32 (1<<17) // fast page erase
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@ -99,7 +75,7 @@ extern const struct command_s stm32f1_cmd_list[]; // Reuse stm32f1 stuff
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#define FLASH_CR_BUF_RESET_CH32 (1<<19) // Buffer reset
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#define FLASH_CR_BUF_RESET_CH32 (1<<19) // Buffer reset
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#define FLASH_SR_EOP (1<<5) // End of programming
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#define FLASH_SR_EOP (1<<5) // End of programming
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#define FLASH_BEGIN_ADDRESS_CH32 0x8000000
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#define FLASH_BEGIN_ADDRESS_CH32 0x8000000
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#define FLASH_MAGIC (FPEC_BASE+0x34)
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static volatile uint32_t magic,sr,ct;
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static volatile uint32_t magic,sr,ct;
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@ -154,7 +130,7 @@ static void ch32f1_add_flash(target *t, uint32_t addr, size_t length, size_t era
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// Which one is the right value ?
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// Which one is the right value ?
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#define MAGIC_WORD 0x100
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#define MAGIC_WORD 0x100
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// #define MAGIC_WORD 0x100
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// #define MAGIC_WORD 0x1000
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#define MAGIC(adr) { magic=target_mem_read32(t,(adr) ^ MAGIC_WORD); \
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#define MAGIC(adr) { magic=target_mem_read32(t,(adr) ^ MAGIC_WORD); \
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target_mem_write32(t, FLASH_MAGIC , magic); }
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target_mem_write32(t, FLASH_MAGIC , magic); }
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@ -172,8 +148,7 @@ static int ch32f1_flash_unlock(target *t)
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target_mem_write32(t, FLASH_MODEKEYR_CH32 , KEY1);
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target_mem_write32(t, FLASH_MODEKEYR_CH32 , KEY1);
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target_mem_write32(t, FLASH_MODEKEYR_CH32 , KEY2);
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target_mem_write32(t, FLASH_MODEKEYR_CH32 , KEY2);
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uint32_t cr = target_mem_read32(t, FLASH_CR);
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uint32_t cr = target_mem_read32(t, FLASH_CR);
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if (cr & FLASH_CR_FLOCK_CH32)
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if (cr & FLASH_CR_FLOCK_CH32){
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{
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ERROR_CH("Fast unlock failed, cr: 0x%08" PRIx32 "\n", cr);
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ERROR_CH("Fast unlock failed, cr: 0x%08" PRIx32 "\n", cr);
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return -1;
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return -1;
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}
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}
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