From 868d65d872626d57c97da9ee6cdee5c8c7f70b29 Mon Sep 17 00:00:00 2001 From: Onno Kortmann Date: Wed, 4 Dec 2013 22:36:11 -0800 Subject: [PATCH] STM32F0: Turn on PLL clock source when asked to The STM32F05xxx/06xxx manual describes on p.98 (Sec 7.4.1) the RCC_CR register, on which it says that bit 24 is the PLLON bit which has to be enabled before using the PLL. This causes the PLL to be enabled with rcc_osc_on(PLL). --- lib/stm32/f0/rcc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/stm32/f0/rcc.c b/lib/stm32/f0/rcc.c index 8f964639..69bdbd88 100644 --- a/lib/stm32/f0/rcc.c +++ b/lib/stm32/f0/rcc.c @@ -250,7 +250,7 @@ void rcc_osc_on(enum rcc_osc osc) RCC_CSR |= RCC_CSR_LSION; break; case PLL: - /* don't do anything */ + RCC_CR|=RCC_CR_PLLON; break; } }