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lib/stm32/f1: Coding-style fixes.

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This commit is contained in:
Uwe Hermann 2011-11-16 19:31:47 +01:00
parent 6e7403f769
commit 8725bc5171
10 changed files with 452 additions and 482 deletions
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67
lib/stm32/f1/adc.c
View File

@ -177,19 +177,19 @@ void adc_disable_temperature_sensor(u32 adc)
void adc_start_conversion_regular(u32 adc)
{
/* start conversion on regular channels */
/* Start conversion on regular channels. */
ADC_CR2(adc) |= ADC_CR2_SWSTART;
/* wait til the ADC starts the conversion */
/* Wait until the ADC starts the conversion. */
while (ADC_CR2(adc) & ADC_CR2_SWSTART);
}
void adc_start_conversion_injected(u32 adc)
{
/* start conversion on injected channels */
/* Start conversion on injected channels. */
ADC_CR2(adc) |= ADC_CR2_JSWSTART;
/* wait til the ADC starts the conversion */
/* Wait until the ADC starts the conversion. */
while (ADC_CR2(adc) & ADC_CR2_JSWSTART);
}
@ -237,16 +237,16 @@ void adc_set_right_aligned(u32 adc)
void adc_enable_dma(u32 adc)
{
if ((adc == ADC1) | (adc==ADC3))
if ((adc == ADC1) | (adc == ADC3))
ADC_CR2(adc) |= ADC_CR2_DMA;
}
void adc_disable_dma(u32 adc)
{
if ((adc == ADC1) | (adc==ADC3))
if ((adc == ADC1) | (adc == ADC3))
ADC_CR2(adc) &= ~ADC_CR2_DMA;
}
void adc_reset_calibration(u32 adc)
{
ADC_CR2(adc) |= ADC_CR2_RSTCAL;
@ -285,31 +285,28 @@ void adc_set_conversion_time(u32 adc, u8 channel, u8 time)
if (channel < 10) {
reg32 = ADC_SMPR2(adc);
reg32 &= ~(0b111 << (channel * 3));
reg32 &= ~(0x7 << (channel * 3));
reg32 |= (time << (channel * 3));
ADC_SMPR2(adc) = reg32;
}
else {
} else {
reg32 = ADC_SMPR1(adc);
reg32 &= ~(0b111 << ((channel-10) * 3));
reg32 |= (time << ((channel-10) * 3));
reg32 &= ~(0x7 << ((channel - 10) * 3));
reg32 |= (time << ((channel - 10) * 3));
ADC_SMPR1(adc) = reg32;
}
}
void adc_set_conversion_time_on_all_channels(u32 adc, u8 time)
{
u32 reg32 = 0;
u8 i;
u32 reg32 = 0;
for (i = 0; i <= 9; i++) {
for (i = 0; i <= 9; i++)
reg32 |= (time << (i * 3));
}
ADC_SMPR2(adc) = reg32;
for (i = 10; i <= 17; i++) {
reg32 |= (time << ((i-10) * 3));
}
for (i = 10; i <= 17; i++)
reg32 |= (time << ((i - 10) * 3));
ADC_SMPR1(adc) = reg32;
}
@ -318,7 +315,7 @@ void adc_set_watchdog_high_threshold(u32 adc, u16 threshold)
u32 reg32 = 0;
reg32 = (u32)threshold;
reg32 &= ~0xfffff000; /* clear all bits above 11 */
reg32 &= ~0xfffff000; /* Clear all bits above 11. */
ADC_HTR(adc) = reg32;
}
@ -327,28 +324,26 @@ void adc_set_watchdog_low_threshold(u32 adc, u16 threshold)
u32 reg32 = 0;
reg32 = (u32)threshold;
reg32 &= ~0xfffff000; /* clear all bits above 11 */
reg32 &= ~0xfffff000; /* Clear all bits above 11. */
ADC_LTR(adc) = reg32;
}
void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[])
{
u32 reg32_1 = 0;
u32 reg32_2 = 0;
u32 reg32_3 = 0;
u32 reg32_1 = 0, reg32_2 = 0, reg32_3 = 0;
u8 i = 0;
/* maximum sequence length is 16 channels */
/* Maximum sequence length is 16 channels. */
if (length > 16)
return;
for (i=1; i<=length; i++) {
if (i <= 6)
reg32_3 |= (channel[i-1] << ((i-1) * 5));
for (i = 1; i <= length; i++) {
if (i <= 6)
reg32_3 |= (channel[i - 1] << ((i - 1) * 5));
if ((i > 6) & (i <= 12))
reg32_2 |= (channel[i-1] << ((i-6-1) * 5));
reg32_2 |= (channel[i - 1] << ((i - 6 - 1) * 5));
if ((i > 12) & (i <= 16))
reg32_1 |= (channel[i-1] << ((i-12-1) * 5));
reg32_1 |= (channel[i - 1] << ((i - 12 - 1) * 5));
}
reg32_1 |= ((length -1) << ADC_SQR1_L_LSB);
@ -362,14 +357,14 @@ void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[])
u32 reg32 = 0;
u8 i = 0;
/* maximum sequence length is 4 channels */
/* Maximum sequence length is 4 channels. */
if (length > 4)
return;
for (i = 1; i <= length; i++) {
reg32 |= (channel[i-1] << ((i-1) * 5));
}
reg32 |= ((length-1) << ADC_JSQR_JL_LSB);
for (i = 1; i <= length; i++)
reg32 |= (channel[i - 1] << ((i - 1) * 5));
reg32 |= ((length - 1) << ADC_JSQR_JL_LSB);
ADC_JSQR(adc) = reg32;
}

18
lib/stm32/f1/can.c
View File

@ -56,32 +56,32 @@ int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart,
/* Set the automatic bus-off management. */
if (ttcm)
CAN_MCR(canport) |= CAN_MCR_TTCM;
CAN_MCR(canport) |= CAN_MCR_TTCM;
else
CAN_MCR(canport) &= ~CAN_MCR_TTCM;
if (abom)
CAN_MCR(canport) |= CAN_MCR_ABOM;
CAN_MCR(canport) |= CAN_MCR_ABOM;
else
CAN_MCR(canport) &= ~CAN_MCR_ABOM;
if (awum)
CAN_MCR(canport) |= CAN_MCR_AWUM;
CAN_MCR(canport) |= CAN_MCR_AWUM;
else
CAN_MCR(canport) &= ~CAN_MCR_AWUM;
if (nart)
CAN_MCR(canport) |= CAN_MCR_NART;
CAN_MCR(canport) |= CAN_MCR_NART;
else
CAN_MCR(canport) &= ~CAN_MCR_NART;
if (rflm)
CAN_MCR(canport) |= CAN_MCR_RFLM;
CAN_MCR(canport) |= CAN_MCR_RFLM;
else
CAN_MCR(canport) &= ~CAN_MCR_RFLM;
if (txfp)
CAN_MCR(canport) |= CAN_MCR_TXFP;
CAN_MCR(canport) |= CAN_MCR_TXFP;
else
CAN_MCR(canport) &= ~CAN_MCR_TXFP;
@ -126,7 +126,7 @@ void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode,
if (id_list_mode) {
/* Set filter mode to ID list mode. */
CAN_FM1R(canport) |= filter_select_bit;
CAN_FM1R(canport) |= filter_select_bit;
} else {
/* Set filter mode to id/mask mode. */
CAN_FM1R(canport) &= ~filter_select_bit;
@ -140,7 +140,7 @@ void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode,
/* Select FIFO0 or FIFO1 as filter assignement. */
if (fifo)
CAN_FFA1R(canport) |= filter_select_bit; /* FIFO1 */
CAN_FFA1R(canport) |= filter_select_bit; /* FIFO1 */
else
CAN_FFA1R(canport) &= ~filter_select_bit; /* FIFO0 */
@ -225,7 +225,7 @@ int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data)
/* Set/clear remote transmission request bit. */
if (rtr)
CAN_TIxR(canport, mailbox) |= CAN_TIxR_RTR; /* Set */
CAN_TIxR(canport, mailbox) |= CAN_TIxR_RTR; /* Set */
/* Set the DLC. */
CAN_TDTxR(canport, mailbox) &= 0xFFFFFFFF0;

801
lib/stm32/f1/dma.c
View File

@ -21,523 +21,496 @@
void dma_enable_mem2mem_mode(u32 dma, u8 channel)
{
switch (channel)
{
case 1:
DMA_CCR1(dma) |= DMA_CCR1_MEM2MEM;
DMA_CCR1(dma) &= ~DMA_CCR1_CIRC;
case 2:
DMA_CCR2(dma) |= DMA_CCR2_MEM2MEM;
DMA_CCR2(dma) &= ~DMA_CCR2_CIRC;
case 3:
DMA_CCR3(dma) |= DMA_CCR3_MEM2MEM;
DMA_CCR3(dma) &= ~DMA_CCR3_CIRC;
case 4:
DMA_CCR4(dma) |= DMA_CCR4_MEM2MEM;
DMA_CCR4(dma) &= ~DMA_CCR4_CIRC;
case 5:
DMA_CCR5(dma) |= DMA_CCR5_MEM2MEM;
DMA_CCR5(dma) &= ~DMA_CCR5_CIRC;
case 6:
if (dma == DMA1) {
DMA_CCR6(dma) |= DMA_CCR6_MEM2MEM;
DMA_CCR6(dma) &= ~DMA_CCR6_CIRC;
}
case 7:
if (dma == DMA1) {
DMA_CCR7(dma) |= DMA_CCR7_MEM2MEM;
DMA_CCR7(dma) &= ~DMA_CCR7_CIRC;
}
switch (channel) {
case 1:
DMA_CCR1(dma) |= DMA_CCR1_MEM2MEM;
DMA_CCR1(dma) &= ~DMA_CCR1_CIRC;
case 2:
DMA_CCR2(dma) |= DMA_CCR2_MEM2MEM;
DMA_CCR2(dma) &= ~DMA_CCR2_CIRC;
case 3:
DMA_CCR3(dma) |= DMA_CCR3_MEM2MEM;
DMA_CCR3(dma) &= ~DMA_CCR3_CIRC;
case 4:
DMA_CCR4(dma) |= DMA_CCR4_MEM2MEM;
DMA_CCR4(dma) &= ~DMA_CCR4_CIRC;
case 5:
DMA_CCR5(dma) |= DMA_CCR5_MEM2MEM;
DMA_CCR5(dma) &= ~DMA_CCR5_CIRC;
case 6:
if (dma == DMA1) {
DMA_CCR6(dma) |= DMA_CCR6_MEM2MEM;
DMA_CCR6(dma) &= ~DMA_CCR6_CIRC;
}
case 7:
if (dma == DMA1) {
DMA_CCR7(dma) |= DMA_CCR7_MEM2MEM;
DMA_CCR7(dma) &= ~DMA_CCR7_CIRC;
}
}
}
void dma_set_priority(u32 dma, u8 channel, u8 prio)
{
/* parameter check */
if (prio > 3)
return;
switch (channel)
{
case 1:
DMA_CCR1(dma) &= ~(0x3 << DMA_CCR1_PL_LSB);
DMA_CCR1(dma) |= (prio << DMA_CCR1_PL_LSB);
case 2:
DMA_CCR2(dma) &= ~(0x3 << DMA_CCR2_PL_LSB);
DMA_CCR2(dma) |= (prio << DMA_CCR2_PL_LSB);
case 3:
DMA_CCR3(dma) &= ~(0x3 << DMA_CCR3_PL_LSB);
DMA_CCR3(dma) |= (prio << DMA_CCR3_PL_LSB);
case 4:
DMA_CCR4(dma) &= ~(0x3 << DMA_CCR4_PL_LSB);
DMA_CCR4(dma) |= (prio << DMA_CCR4_PL_LSB);
case 5:
DMA_CCR5(dma) &= ~(0x3 << DMA_CCR5_PL_LSB);
DMA_CCR5(dma) |= (prio << DMA_CCR5_PL_LSB);
case 6:
if (dma == DMA1) {
DMA_CCR6(dma) &= ~(0x3 << DMA_CCR6_PL_LSB);
DMA_CCR6(dma) |= (prio << DMA_CCR6_PL_LSB);
}
case 7:
if (dma == DMA1) {
DMA_CCR7(dma) &= ~(0x3 << DMA_CCR7_PL_LSB);
DMA_CCR7(dma) |= (prio << DMA_CCR7_PL_LSB);
}
switch (channel) {
case 1:
DMA_CCR1(dma) &= ~(0x3 << DMA_CCR1_PL_LSB);
DMA_CCR1(dma) |= (prio << DMA_CCR1_PL_LSB);
case 2:
DMA_CCR2(dma) &= ~(0x3 << DMA_CCR2_PL_LSB);
DMA_CCR2(dma) |= (prio << DMA_CCR2_PL_LSB);
case 3:
DMA_CCR3(dma) &= ~(0x3 << DMA_CCR3_PL_LSB);
DMA_CCR3(dma) |= (prio << DMA_CCR3_PL_LSB);
case 4:
DMA_CCR4(dma) &= ~(0x3 << DMA_CCR4_PL_LSB);
DMA_CCR4(dma) |= (prio << DMA_CCR4_PL_LSB);
case 5:
DMA_CCR5(dma) &= ~(0x3 << DMA_CCR5_PL_LSB);
DMA_CCR5(dma) |= (prio << DMA_CCR5_PL_LSB);
case 6:
if (dma == DMA1) {
DMA_CCR6(dma) &= ~(0x3 << DMA_CCR6_PL_LSB);
DMA_CCR6(dma) |= (prio << DMA_CCR6_PL_LSB);
}
case 7:
if (dma == DMA1) {
DMA_CCR7(dma) &= ~(0x3 << DMA_CCR7_PL_LSB);
DMA_CCR7(dma) |= (prio << DMA_CCR7_PL_LSB);
}
}
}
void dma_set_memory_size(u32 dma, u8 channel, u8 mem_size)
{
/* parameter check */
if (mem_size > 2)
return;
switch (channel)
{
case 1:
DMA_CCR1(dma) &= ~(0x3 << DMA_CCR1_MSIZE_LSB);
DMA_CCR1(dma) |= (mem_size << DMA_CCR1_MSIZE_LSB);
case 2:
DMA_CCR2(dma) &= ~(0x3 << DMA_CCR2_MSIZE_LSB);
DMA_CCR2(dma) |= (mem_size << DMA_CCR2_MSIZE_LSB);
case 3:
DMA_CCR3(dma) &= ~(0x3 << DMA_CCR3_MSIZE_LSB);
DMA_CCR3(dma) |= (mem_size << DMA_CCR3_MSIZE_LSB);
case 4:
DMA_CCR4(dma) &= ~(0x3 << DMA_CCR4_MSIZE_LSB);
DMA_CCR4(dma) |= (mem_size << DMA_CCR4_MSIZE_LSB);
case 5:
DMA_CCR5(dma) &= ~(0x3 << DMA_CCR5_MSIZE_LSB);
DMA_CCR5(dma) |= (mem_size << DMA_CCR5_MSIZE_LSB);
case 6:
if (dma == DMA1) {
DMA_CCR6(dma) &= ~(0x3 << DMA_CCR6_MSIZE_LSB);
DMA_CCR6(dma) |= (mem_size << DMA_CCR6_MSIZE_LSB);
}
case 7:
if (dma == DMA1) {
DMA_CCR7(dma) &= ~(0x3 << DMA_CCR7_MSIZE_LSB);
DMA_CCR7(dma) |= (mem_size << DMA_CCR7_MSIZE_LSB);
}
switch (channel) {
case 1:
DMA_CCR1(dma) &= ~(0x3 << DMA_CCR1_MSIZE_LSB);
DMA_CCR1(dma) |= (mem_size << DMA_CCR1_MSIZE_LSB);
case 2:
DMA_CCR2(dma) &= ~(0x3 << DMA_CCR2_MSIZE_LSB);
DMA_CCR2(dma) |= (mem_size << DMA_CCR2_MSIZE_LSB);
case 3:
DMA_CCR3(dma) &= ~(0x3 << DMA_CCR3_MSIZE_LSB);
DMA_CCR3(dma) |= (mem_size << DMA_CCR3_MSIZE_LSB);
case 4:
DMA_CCR4(dma) &= ~(0x3 << DMA_CCR4_MSIZE_LSB);
DMA_CCR4(dma) |= (mem_size << DMA_CCR4_MSIZE_LSB);
case 5:
DMA_CCR5(dma) &= ~(0x3 << DMA_CCR5_MSIZE_LSB);
DMA_CCR5(dma) |= (mem_size << DMA_CCR5_MSIZE_LSB);
case 6:
if (dma == DMA1) {
DMA_CCR6(dma) &= ~(0x3 << DMA_CCR6_MSIZE_LSB);
DMA_CCR6(dma) |= (mem_size << DMA_CCR6_MSIZE_LSB);
}
case 7:
if (dma == DMA1) {
DMA_CCR7(dma) &= ~(0x3 << DMA_CCR7_MSIZE_LSB);
DMA_CCR7(dma) |= (mem_size << DMA_CCR7_MSIZE_LSB);
}
}
}
void dma_set_peripheral_size(u32 dma, u8 channel, u8 peripheral_size)
{
/* parameter check */
if (peripheral_size > 2)
return;
switch (channel)
{
case 1:
DMA_CCR1(dma) &= ~(0x3 << DMA_CCR1_PSIZE_LSB);
DMA_CCR1(dma) |= (peripheral_size << DMA_CCR1_PSIZE_LSB);
case 2:
DMA_CCR2(dma) &= ~(0x3 << DMA_CCR2_PSIZE_LSB);
DMA_CCR2(dma) |= (peripheral_size << DMA_CCR2_PSIZE_LSB);
case 3:
DMA_CCR3(dma) &= ~(0x3 << DMA_CCR3_PSIZE_LSB);
DMA_CCR3(dma) |= (peripheral_size << DMA_CCR3_PSIZE_LSB);
case 4:
DMA_CCR4(dma) &= ~(0x3 << DMA_CCR4_PSIZE_LSB);
DMA_CCR4(dma) |= (peripheral_size << DMA_CCR4_PSIZE_LSB);
case 5:
DMA_CCR5(dma) &= ~(0x3 << DMA_CCR5_PSIZE_LSB);
DMA_CCR5(dma) |= (peripheral_size << DMA_CCR5_PSIZE_LSB);
case 6:
if (dma == DMA1) {
DMA_CCR6(dma) &= ~(0x3 << DMA_CCR6_PSIZE_LSB);
DMA_CCR6(dma) |= (peripheral_size << DMA_CCR6_PSIZE_LSB);
}
case 7:
if (dma == DMA1) {
DMA_CCR7(dma) &= ~(0x3 << DMA_CCR7_PSIZE_LSB);
DMA_CCR7(dma) |= (peripheral_size << DMA_CCR7_PSIZE_LSB);
}
switch (channel) {
case 1:
DMA_CCR1(dma) &= ~(0x3 << DMA_CCR1_PSIZE_LSB);
DMA_CCR1(dma) |= (peripheral_size << DMA_CCR1_PSIZE_LSB);
case 2:
DMA_CCR2(dma) &= ~(0x3 << DMA_CCR2_PSIZE_LSB);
DMA_CCR2(dma) |= (peripheral_size << DMA_CCR2_PSIZE_LSB);
case 3:
DMA_CCR3(dma) &= ~(0x3 << DMA_CCR3_PSIZE_LSB);
DMA_CCR3(dma) |= (peripheral_size << DMA_CCR3_PSIZE_LSB);
case 4:
DMA_CCR4(dma) &= ~(0x3 << DMA_CCR4_PSIZE_LSB);
DMA_CCR4(dma) |= (peripheral_size << DMA_CCR4_PSIZE_LSB);
case 5:
DMA_CCR5(dma) &= ~(0x3 << DMA_CCR5_PSIZE_LSB);
DMA_CCR5(dma) |= (peripheral_size << DMA_CCR5_PSIZE_LSB);
case 6:
if (dma == DMA1) {
DMA_CCR6(dma) &= ~(0x3 << DMA_CCR6_PSIZE_LSB);
DMA_CCR6(dma) |=
(peripheral_size << DMA_CCR6_PSIZE_LSB);
}
case 7:
if (dma == DMA1) {
DMA_CCR7(dma) &= ~(0x3 << DMA_CCR7_PSIZE_LSB);
DMA_CCR7(dma) |=
(peripheral_size << DMA_CCR7_PSIZE_LSB);
}
}
}
void dma_enable_memory_increment_mode(u32 dma, u8 channel)
{
switch (channel)
{
case 1:
DMA_CCR1(dma) |= DMA_CCR1_MINC;
case 2:
DMA_CCR2(dma) |= DMA_CCR2_MINC;
case 3:
DMA_CCR3(dma) |= DMA_CCR3_MINC;
case 4:
DMA_CCR4(dma) |= DMA_CCR4_MINC;
case 5:
DMA_CCR5(dma) |= DMA_CCR5_MINC;
case 6:
if (dma == DMA1)
DMA_CCR6(dma) |= DMA_CCR6_MINC;
case 7:
if (dma == DMA1)
DMA_CCR7(dma) |= DMA_CCR7_MINC;
switch (channel) {
case 1:
DMA_CCR1(dma) |= DMA_CCR1_MINC;
case 2:
DMA_CCR2(dma) |= DMA_CCR2_MINC;
case 3:
DMA_CCR3(dma) |= DMA_CCR3_MINC;
case 4:
DMA_CCR4(dma) |= DMA_CCR4_MINC;
case 5:
DMA_CCR5(dma) |= DMA_CCR5_MINC;
case 6:
if (dma == DMA1)
DMA_CCR6(dma) |= DMA_CCR6_MINC;
case 7:
if (dma == DMA1)
DMA_CCR7(dma) |= DMA_CCR7_MINC;
}
}
void dma_enable_peripheral_increment_mode(u32 dma, u8 channel)
{
switch (channel)
{
case 1:
DMA_CCR1(dma) |= DMA_CCR1_PINC;
case 2:
DMA_CCR2(dma) |= DMA_CCR2_PINC;
case 3:
DMA_CCR3(dma) |= DMA_CCR3_PINC;
case 4:
DMA_CCR4(dma) |= DMA_CCR4_PINC;
case 5:
DMA_CCR5(dma) |= DMA_CCR5_PINC;
case 6:
if (dma == DMA1)
DMA_CCR6(dma) |= DMA_CCR6_PINC;
case 7:
if (dma == DMA1)
DMA_CCR7(dma) |= DMA_CCR7_PINC;
switch (channel) {
case 1:
DMA_CCR1(dma) |= DMA_CCR1_PINC;
case 2:
DMA_CCR2(dma) |= DMA_CCR2_PINC;
case 3:
DMA_CCR3(dma) |= DMA_CCR3_PINC;
case 4:
DMA_CCR4(dma) |= DMA_CCR4_PINC;
case 5:
DMA_CCR5(dma) |= DMA_CCR5_PINC;
case 6:
if (dma == DMA1)
DMA_CCR6(dma) |= DMA_CCR6_PINC;
case 7:
if (dma == DMA1)
DMA_CCR7(dma) |= DMA_CCR7_PINC;
}
}
void dma_enable_circular_mode(u32 dma, u8 channel)
{
switch (channel)
{
case 1:
DMA_CCR1(dma) |= DMA_CCR1_CIRC;
DMA_CCR1(dma) &= ~DMA_CCR1_MEM2MEM;
case 2:
DMA_CCR2(dma) |= DMA_CCR2_CIRC;
DMA_CCR2(dma) &= ~DMA_CCR2_MEM2MEM;
case 3:
DMA_CCR3(dma) |= DMA_CCR3_CIRC;
DMA_CCR3(dma) &= ~DMA_CCR3_MEM2MEM;
case 4:
DMA_CCR4(dma) |= DMA_CCR4_CIRC;
DMA_CCR4(dma) &= ~DMA_CCR4_MEM2MEM;
case 5:
DMA_CCR5(dma) |= DMA_CCR5_CIRC;
DMA_CCR5(dma) &= ~DMA_CCR5_MEM2MEM;
case 6:
if (dma == DMA1) {
DMA_CCR6(dma) |= DMA_CCR6_CIRC;
DMA_CCR6(dma) &= ~DMA_CCR6_MEM2MEM;
}
case 7:
if (dma == DMA1) {
DMA_CCR7(dma) |= DMA_CCR7_CIRC;
DMA_CCR7(dma) &= ~DMA_CCR7_MEM2MEM;
}
switch (channel) {
case 1:
DMA_CCR1(dma) |= DMA_CCR1_CIRC;
DMA_CCR1(dma) &= ~DMA_CCR1_MEM2MEM;
case 2:
DMA_CCR2(dma) |= DMA_CCR2_CIRC;
DMA_CCR2(dma) &= ~DMA_CCR2_MEM2MEM;
case 3:
DMA_CCR3(dma) |= DMA_CCR3_CIRC;
DMA_CCR3(dma) &= ~DMA_CCR3_MEM2MEM;
case 4:
DMA_CCR4(dma) |= DMA_CCR4_CIRC;
DMA_CCR4(dma) &= ~DMA_CCR4_MEM2MEM;
case 5:
DMA_CCR5(dma) |= DMA_CCR5_CIRC;
DMA_CCR5(dma) &= ~DMA_CCR5_MEM2MEM;
case 6:
if (dma == DMA1) {
DMA_CCR6(dma) |= DMA_CCR6_CIRC;
DMA_CCR6(dma) &= ~DMA_CCR6_MEM2MEM;
}
case 7:
if (dma == DMA1) {
DMA_CCR7(dma) |= DMA_CCR7_CIRC;
DMA_CCR7(dma) &= ~DMA_CCR7_MEM2MEM;
}
}
}
void dma_set_read_from_peripheral(u32 dma, u8 channel)
{
switch (channel)
{
case 1:
DMA_CCR1(dma) &= ~DMA_CCR1_DIR;
case 2:
DMA_CCR2(dma) &= ~DMA_CCR2_DIR;
case 3:
DMA_CCR3(dma) &= ~DMA_CCR3_DIR;
case 4:
DMA_CCR4(dma) &= ~DMA_CCR4_DIR;
case 5:
DMA_CCR5(dma) &= ~DMA_CCR5_DIR;
case 6:
if (dma == DMA1)
DMA_CCR6(dma) &= ~DMA_CCR6_DIR;
case 7:
if (dma == DMA1)
DMA_CCR7(dma) &= ~DMA_CCR7_DIR;
switch (channel) {
case 1:
DMA_CCR1(dma) &= ~DMA_CCR1_DIR;
case 2:
DMA_CCR2(dma) &= ~DMA_CCR2_DIR;
case 3:
DMA_CCR3(dma) &= ~DMA_CCR3_DIR;
case 4:
DMA_CCR4(dma) &= ~DMA_CCR4_DIR;
case 5:
DMA_CCR5(dma) &= ~DMA_CCR5_DIR;
case 6:
if (dma == DMA1)
DMA_CCR6(dma) &= ~DMA_CCR6_DIR;
case 7:
if (dma == DMA1)
DMA_CCR7(dma) &= ~DMA_CCR7_DIR;
}
}
void dma_set_read_from_memory(u32 dma, u8 channel)
{
switch (channel)
{
case 1:
DMA_CCR1(dma) |= DMA_CCR1_DIR;
case 2:
DMA_CCR2(dma) |= DMA_CCR2_DIR;
case 3:
DMA_CCR3(dma) |= DMA_CCR3_DIR;
case 4:
DMA_CCR4(dma) |= DMA_CCR4_DIR;
case 5:
DMA_CCR5(dma) |= DMA_CCR5_DIR;
case 6:
if (dma == DMA1)
DMA_CCR6(dma) |= DMA_CCR6_DIR;
case 7:
if (dma == DMA1)
DMA_CCR7(dma) |= DMA_CCR7_DIR;
switch (channel) {
case 1:
DMA_CCR1(dma) |= DMA_CCR1_DIR;
case 2:
DMA_CCR2(dma) |= DMA_CCR2_DIR;
case 3:
DMA_CCR3(dma) |= DMA_CCR3_DIR;
case 4:
DMA_CCR4(dma) |= DMA_CCR4_DIR;
case 5:
DMA_CCR5(dma) |= DMA_CCR5_DIR;
case 6:
if (dma == DMA1)
DMA_CCR6(dma) |= DMA_CCR6_DIR;
case 7:
if (dma == DMA1)
DMA_CCR7(dma) |= DMA_CCR7_DIR;
}
}
void dma_enable_transfer_error_interrupt(u32 dma, u8 channel)
{
switch (channel)
{
case 1:
DMA_CCR1(dma) |= DMA_CCR1_TEIE;
case 2:
DMA_CCR2(dma) |= DMA_CCR2_TEIE;
case 3:
DMA_CCR3(dma) |= DMA_CCR3_TEIE;
case 4:
DMA_CCR4(dma) |= DMA_CCR4_TEIE;
case 5:
DMA_CCR5(dma) |= DMA_CCR5_TEIE;
case 6:
if (dma == DMA1)
DMA_CCR6(dma) |= DMA_CCR6_TEIE;
case 7:
if (dma == DMA1)
DMA_CCR7(dma) |= DMA_CCR7_TEIE;
switch (channel) {
case 1:
DMA_CCR1(dma) |= DMA_CCR1_TEIE;
case 2:
DMA_CCR2(dma) |= DMA_CCR2_TEIE;
case 3:
DMA_CCR3(dma) |= DMA_CCR3_TEIE;
case 4:
DMA_CCR4(dma) |= DMA_CCR4_TEIE;
case 5:
DMA_CCR5(dma) |= DMA_CCR5_TEIE;
case 6:
if (dma == DMA1)
DMA_CCR6(dma) |= DMA_CCR6_TEIE;
case 7:
if (dma == DMA1)
DMA_CCR7(dma) |= DMA_CCR7_TEIE;
}
}
void dma_disable_transfer_error_interrupt(u32 dma, u8 channel)
{
switch (channel)
{
case 1:
DMA_CCR1(dma) &= ~DMA_CCR1_TEIE;
case 2:
DMA_CCR2(dma) &= ~DMA_CCR2_TEIE;
case 3:
DMA_CCR3(dma) &= ~DMA_CCR3_TEIE;
case 4:
DMA_CCR4(dma) &= ~DMA_CCR4_TEIE;
case 5:
DMA_CCR5(dma) &= ~DMA_CCR5_TEIE;
case 6:
if (dma == DMA1)
DMA_CCR6(dma) &= ~DMA_CCR6_TEIE;
case 7:
if (dma == DMA1)
DMA_CCR7(dma) &= ~DMA_CCR7_TEIE;
switch (channel) {
case 1:
DMA_CCR1(dma) &= ~DMA_CCR1_TEIE;
case 2:
DMA_CCR2(dma) &= ~DMA_CCR2_TEIE;
case 3:
DMA_CCR3(dma) &= ~DMA_CCR3_TEIE;
case 4:
DMA_CCR4(dma) &= ~DMA_CCR4_TEIE;
case 5:
DMA_CCR5(dma) &= ~DMA_CCR5_TEIE;
case 6:
if (dma == DMA1)
DMA_CCR6(dma) &= ~DMA_CCR6_TEIE;
case 7:
if (dma == DMA1)
DMA_CCR7(dma) &= ~DMA_CCR7_TEIE;
}
}
void dma_enable_half_transfer_interrupt(u32 dma, u8 channel)
{
switch (channel)
{
case 1:
DMA_CCR1(dma) |= DMA_CCR1_HTIE;
case 2:
DMA_CCR2(dma) |= DMA_CCR2_HTIE;
case 3:
DMA_CCR3(dma) |= DMA_CCR3_HTIE;
case 4:
DMA_CCR4(dma) |= DMA_CCR4_HTIE;
case 5:
DMA_CCR5(dma) |= DMA_CCR5_HTIE;
case 6:
if (dma == DMA1)
DMA_CCR6(dma) |= DMA_CCR6_HTIE;
case 7:
if (dma == DMA1)
DMA_CCR7(dma) |= DMA_CCR7_HTIE;
switch (channel) {
case 1:
DMA_CCR1(dma) |= DMA_CCR1_HTIE;
case 2:
DMA_CCR2(dma) |= DMA_CCR2_HTIE;
case 3:
DMA_CCR3(dma) |= DMA_CCR3_HTIE;
case 4:
DMA_CCR4(dma) |= DMA_CCR4_HTIE;
case 5:
DMA_CCR5(dma) |= DMA_CCR5_HTIE;
case 6:
if (dma == DMA1)
DMA_CCR6(dma) |= DMA_CCR6_HTIE;
case 7:
if (dma == DMA1)
DMA_CCR7(dma) |= DMA_CCR7_HTIE;
}
}
void dma_disable_half_transfer_interrupt(u32 dma, u8 channel)
{
switch (channel)
{
case 1:
DMA_CCR1(dma) &= ~DMA_CCR1_HTIE;
case 2:
DMA_CCR2(dma) &= ~DMA_CCR2_HTIE;
case 3:
DMA_CCR3(dma) &= ~DMA_CCR3_HTIE;
case 4:
DMA_CCR4(dma) &= ~DMA_CCR4_HTIE;
case 5:
DMA_CCR5(dma) &= ~DMA_CCR5_HTIE;
case 6:
if (dma == DMA1)
DMA_CCR6(dma) &= ~DMA_CCR6_HTIE;
case 7:
if (dma == DMA1)
DMA_CCR7(dma) &= ~DMA_CCR7_HTIE;
switch (channel) {
case 1:
DMA_CCR1(dma) &= ~DMA_CCR1_HTIE;
case 2:
DMA_CCR2(dma) &= ~DMA_CCR2_HTIE;
case 3:
DMA_CCR3(dma) &= ~DMA_CCR3_HTIE;
case 4:
DMA_CCR4(dma) &= ~DMA_CCR4_HTIE;
case 5:
DMA_CCR5(dma) &= ~DMA_CCR5_HTIE;
case 6:
if (dma == DMA1)
DMA_CCR6(dma) &= ~DMA_CCR6_HTIE;
case 7:
if (dma == DMA1)
DMA_CCR7(dma) &= ~DMA_CCR7_HTIE;
}
}
void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel)
{
switch (channel)
{
case 1:
DMA_CCR1(dma) |= DMA_CCR1_TCIE;
case 2:
DMA_CCR2(dma) |= DMA_CCR2_TCIE;
case 3:
DMA_CCR3(dma) |= DMA_CCR3_TCIE;
case 4:
DMA_CCR4(dma) |= DMA_CCR4_TCIE;
case 5:
DMA_CCR5(dma) |= DMA_CCR5_TCIE;
case 6:
if (dma == DMA1)
DMA_CCR6(dma) |= DMA_CCR6_TCIE;
case 7:
if (dma == DMA1)
DMA_CCR7(dma) |= DMA_CCR7_TCIE;
switch (channel) {
case 1:
DMA_CCR1(dma) |= DMA_CCR1_TCIE;
case 2:
DMA_CCR2(dma) |= DMA_CCR2_TCIE;
case 3:
DMA_CCR3(dma) |= DMA_CCR3_TCIE;
case 4:
DMA_CCR4(dma) |= DMA_CCR4_TCIE;
case 5:
DMA_CCR5(dma) |= DMA_CCR5_TCIE;
case 6:
if (dma == DMA1)
DMA_CCR6(dma) |= DMA_CCR6_TCIE;
case 7:
if (dma == DMA1)
DMA_CCR7(dma) |= DMA_CCR7_TCIE;
}
}
void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel)
{
switch (channel)
{
case 1:
DMA_CCR1(dma) &= ~DMA_CCR1_TCIE;
case 2:
DMA_CCR2(dma) &= ~DMA_CCR2_TCIE;
case 3:
DMA_CCR3(dma) &= ~DMA_CCR3_TCIE;
case 4:
DMA_CCR4(dma) &= ~DMA_CCR4_TCIE;
case 5:
DMA_CCR5(dma) &= ~DMA_CCR5_TCIE;
case 6:
if (dma == DMA1)
DMA_CCR6(dma) &= ~DMA_CCR6_TCIE;
case 7:
if (dma == DMA1)
DMA_CCR7(dma) &= ~DMA_CCR7_TCIE;
switch (channel) {
case 1:
DMA_CCR1(dma) &= ~DMA_CCR1_TCIE;
case 2:
DMA_CCR2(dma) &= ~DMA_CCR2_TCIE;
case 3:
DMA_CCR3(dma) &= ~DMA_CCR3_TCIE;
case 4:
DMA_CCR4(dma) &= ~DMA_CCR4_TCIE;
case 5:
DMA_CCR5(dma) &= ~DMA_CCR5_TCIE;
case 6:
if (dma == DMA1)
DMA_CCR6(dma) &= ~DMA_CCR6_TCIE;
case 7:
if (dma == DMA1)
DMA_CCR7(dma) &= ~DMA_CCR7_TCIE;
}
}
void dma_enable_channel(u32 dma, u8 channel)
{
switch (channel)
{
case 1:
DMA_CCR1(dma) |= DMA_CCR1_EN;
case 2:
DMA_CCR2(dma) |= DMA_CCR2_EN;
case 3:
DMA_CCR3(dma) |= DMA_CCR3_EN;
case 4:
DMA_CCR4(dma) |= DMA_CCR4_EN;
case 5:
DMA_CCR5(dma) |= DMA_CCR5_EN;
case 6:
if (dma == DMA1)
DMA_CCR6(dma) |= DMA_CCR6_EN;
case 7:
if (dma == DMA1)
DMA_CCR7(dma) |= DMA_CCR7_EN;
switch (channel) {
case 1:
DMA_CCR1(dma) |= DMA_CCR1_EN;
case 2:
DMA_CCR2(dma) |= DMA_CCR2_EN;
case 3:
DMA_CCR3(dma) |= DMA_CCR3_EN;
case 4:
DMA_CCR4(dma) |= DMA_CCR4_EN;
case 5:
DMA_CCR5(dma) |= DMA_CCR5_EN;
case 6:
if (dma == DMA1)
DMA_CCR6(dma) |= DMA_CCR6_EN;
case 7:
if (dma == DMA1)
DMA_CCR7(dma) |= DMA_CCR7_EN;
}
}
void dma_disable_channel(u32 dma, u8 channel)
{
switch (channel)
{
case 1:
DMA_CCR1(dma) &= ~DMA_CCR1_EN;
case 2:
DMA_CCR2(dma) &= ~DMA_CCR2_EN;
case 3:
DMA_CCR3(dma) &= ~DMA_CCR3_EN;
case 4:
DMA_CCR4(dma) &= ~DMA_CCR4_EN;
case 5:
DMA_CCR5(dma) &= ~DMA_CCR5_EN;
case 6:
if (dma == DMA1)
DMA_CCR6(dma) &= ~DMA_CCR6_EN;
case 7:
if (dma == DMA1)
DMA_CCR7(dma) &= ~DMA_CCR7_EN;
switch (channel) {
case 1:
DMA_CCR1(dma) &= ~DMA_CCR1_EN;
case 2:
DMA_CCR2(dma) &= ~DMA_CCR2_EN;
case 3:
DMA_CCR3(dma) &= ~DMA_CCR3_EN;
case 4:
DMA_CCR4(dma) &= ~DMA_CCR4_EN;
case 5:
DMA_CCR5(dma) &= ~DMA_CCR5_EN;
case 6:
if (dma == DMA1)
DMA_CCR6(dma) &= ~DMA_CCR6_EN;
case 7:
if (dma == DMA1)
DMA_CCR7(dma) &= ~DMA_CCR7_EN;
}
}
void dma_set_peripheral_address(u32 dma, u8 channel, u32 address)
{
switch (channel)
{
case 1:
DMA_CPAR1(dma) = (u32)address;
case 2:
DMA_CPAR2(dma) = (u32)address;
case 3:
DMA_CPAR3(dma) = (u32)address;
case 4:
DMA_CPAR4(dma) = (u32)address;
case 5:
DMA_CPAR5(dma) = (u32)address;
case 6:
if (dma == DMA1)
DMA_CPAR6(dma) = (u32)address;
case 7:
if (dma == DMA1)
DMA_CPAR7(dma) = (u32)address;
switch (channel) {
case 1:
DMA_CPAR1(dma) = (u32) address;
case 2:
DMA_CPAR2(dma) = (u32) address;
case 3:
DMA_CPAR3(dma) = (u32) address;
case 4:
DMA_CPAR4(dma) = (u32) address;
case 5:
DMA_CPAR5(dma) = (u32) address;
case 6:
if (dma == DMA1)
DMA_CPAR6(dma) = (u32) address;
case 7:
if (dma == DMA1)
DMA_CPAR7(dma) = (u32) address;
}
}
void dma_set_memory_address(u32 dma, u8 channel, u32 address)
{
switch (channel)
{
case 1:
DMA_CMAR1(dma) = (u32)address;
case 2:
DMA_CMAR2(dma) = (u32)address;
case 3:
DMA_CMAR3(dma) = (u32)address;
case 4:
DMA_CMAR4(dma) = (u32)address;
case 5:
DMA_CMAR5(dma) = (u32)address;
case 6:
if (dma == DMA1)
DMA_CMAR6(dma) = (u32)address;
case 7:
if (dma == DMA1)
DMA_CMAR7(dma) = (u32)address;
switch (channel) {
case 1:
DMA_CMAR1(dma) = (u32) address;
case 2:
DMA_CMAR2(dma) = (u32) address;
case 3:
DMA_CMAR3(dma) = (u32) address;
case 4:
DMA_CMAR4(dma) = (u32) address;
case 5:
DMA_CMAR5(dma) = (u32) address;
case 6:
if (dma == DMA1)
DMA_CMAR6(dma) = (u32) address;
case 7:
if (dma == DMA1)
DMA_CMAR7(dma) = (u32) address;
}
}
void dma_set_number_of_data(u32 dma, u8 channel, u16 number)
{
switch (channel)
{
case 1:
DMA_CNDTR1(dma) = number;
case 2:
DMA_CNDTR2(dma) = number;
case 3:
DMA_CNDTR3(dma) = number;
case 4:
DMA_CNDTR4(dma) = number;
case 5:
DMA_CNDTR5(dma) = number;
case 6:
if (dma == DMA1)
DMA_CNDTR6(dma) = number;
case 7:
if (dma == DMA1)
DMA_CNDTR7(dma) = number;
switch (channel) {
case 1:
DMA_CNDTR1(dma) = number;
case 2:
DMA_CNDTR2(dma) = number;
case 3:
DMA_CNDTR3(dma) = number;
case 4:
DMA_CNDTR4(dma) = number;
case 5:
DMA_CNDTR5(dma) = number;
case 6:
if (dma == DMA1)
DMA_CNDTR6(dma) = number;
case 7:
if (dma == DMA1)
DMA_CNDTR7(dma) = number;
}
}

3
lib/stm32/f1/ethernet.c
View File

@ -38,8 +38,7 @@ void eth_smi_write(u8 phy, u8 reg, u16 data)
u16 eth_smi_read(u8 phy, u8 reg)
{
/* Set PHY and register addresses for write access. */
ETH_MACMIIAR &= ~(ETH_MACMIIAR_MR | ETH_MACMIIAR_PA |
ETH_MACMIIAR_MW);
ETH_MACMIIAR &= ~(ETH_MACMIIAR_MR | ETH_MACMIIAR_PA | ETH_MACMIIAR_MW);
ETH_MACMIIAR |= (phy << 11) | (reg << 6);
/* Begin transaction. */

8
lib/stm32/f1/exti.c
View File

@ -131,15 +131,15 @@ void exti_select_source(u32 exti, u32 gpioport)
/* Ensure that only valid EXTI lines are used. */
if (exti < EXTI4) {
AFIO_EXTICR1 &= ~(0x000F << shift);
AFIO_EXTICR1 |= (~bits << shift);
AFIO_EXTICR1 |= (~bits << shift);
} else if (exti < EXTI8) {
AFIO_EXTICR2 &= ~(0x000F << shift);
AFIO_EXTICR2 |= (~bits << shift);
AFIO_EXTICR2 |= (~bits << shift);
} else if (exti < EXTI12) {
AFIO_EXTICR3 &= ~(0x000F << shift);
AFIO_EXTICR3 |= (~bits << shift);
AFIO_EXTICR3 |= (~bits << shift);
} else if (exti < EXTI16) {
AFIO_EXTICR4 &= ~(0x000F << shift);
AFIO_EXTICR4 |= (~bits << shift);
AFIO_EXTICR4 |= (~bits << shift);
}
}

6
lib/stm32/f1/gpio.c
View File

@ -47,7 +47,7 @@ void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios)
*/
crl = GPIO_CRL(gpioport);
crh = GPIO_CRH(gpioport);
/* Iterate over all bits, use i as the bitnumber. */
for (i = 0; i < 16; i++) {
/* Only set the config if the bit is set in gpios. */
@ -61,7 +61,7 @@ void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios)
tmp32 = (i < 8) ? crl : crh;
/* Modify bits are needed. */
tmp32 &= ~(0b1111 << offset); /* Clear the bits first. */
tmp32 &= ~(0xf << offset); /* Clear the bits first. */
tmp32 |= (mode << offset) | (cnf << (offset + 2));
/* Write tmp32 into crl or crh, leave the other unchanged. */
@ -113,6 +113,6 @@ void gpio_port_config_lock(u32 gpioport, u16 gpios)
GPIO_LCKR(gpioport) = GPIO_LCKK | gpios; /* Set LCKK. */
reg32 = GPIO_LCKR(gpioport); /* Read LCKK. */
reg32 = GPIO_LCKR(gpioport); /* Read LCKK again. */
/* If (reg32 & GPIO_LCKK) is true, the lock is now active. */
}

1
lib/stm32/f1/rcc.c
View File

@ -493,6 +493,7 @@ void rcc_clock_setup_in_hse_8mhz_out_24mhz(void)
rcc_ppre1_frequency = 24000000;
rcc_ppre2_frequency = 24000000;
}
void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
{
/* Enable internal high-speed oscillator. */

8
lib/stm32/f1/rtc.c
View File

@ -167,7 +167,7 @@ void rtc_interrupt_enable(rtcflag_t flag_val)
rtc_enter_config_mode();
/* Set the correct interrupt enable. */
switch(flag_val) {
switch (flag_val) {
case RTC_SEC:
RTC_CRH |= RTC_CRH_SECIE;
break;
@ -187,7 +187,7 @@ void rtc_interrupt_disable(rtcflag_t flag_val)
rtc_enter_config_mode();
/* Disable the correct interrupt enable. */
switch(flag_val) {
switch (flag_val) {
case RTC_SEC:
RTC_CRH &= ~RTC_CRH_SECIE;
break;
@ -207,7 +207,7 @@ void rtc_clear_flag(rtcflag_t flag_val)
/* Configuration mode not needed. */
/* Clear the correct flag. */
switch(flag_val) {
switch (flag_val) {
case RTC_SEC:
RTC_CRL &= ~RTC_CRL_SECF;
break;
@ -225,7 +225,7 @@ u32 rtc_check_flag(rtcflag_t flag_val)
u32 reg32;
/* Read correct flag. */
switch(flag_val) {
switch (flag_val) {
case RTC_SEC:
reg32 = RTC_CRL & RTC_CRL_SECF;
break;

16
lib/stm32/f1/timer.c
View File

@ -125,9 +125,7 @@ void timer_set_mode(u32 timer_peripheral, u8 clock_div,
cr1 = TIM_CR1(timer_peripheral);
cr1 &= ~(TIM_CR1_CKD_CK_INT_MASK |
TIM_CR1_CMS_MASK |
TIM_CR1_DIR_DOWN);
cr1 &= ~(TIM_CR1_CKD_CK_INT_MASK | TIM_CR1_CMS_MASK | TIM_CR1_DIR_DOWN);
cr1 |= clock_div | alignment | direction;
@ -397,7 +395,8 @@ void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id,
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FORCE_LOW;
break;
case TIM_OCM_FORCE_HIGH:
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FORCE_HIGH;
TIM_CCMR1(timer_peripheral) |=
TIM_CCMR1_OC1M_FORCE_HIGH;
break;
case TIM_OCM_PWM1:
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_PWM1;
@ -428,7 +427,8 @@ void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id,
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_FORCE_LOW;
break;
case TIM_OCM_FORCE_HIGH:
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_FORCE_HIGH;
TIM_CCMR1(timer_peripheral) |=
TIM_CCMR1_OC2M_FORCE_HIGH;
break;
case TIM_OCM_PWM1:
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_PWM1;
@ -459,7 +459,8 @@ void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id,
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FORCE_LOW;
break;
case TIM_OCM_FORCE_HIGH:
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FORCE_HIGH;
TIM_CCMR2(timer_peripheral) |=
TIM_CCMR2_OC3M_FORCE_HIGH;
break;
case TIM_OCM_PWM1:
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_PWM1;
@ -490,7 +491,8 @@ void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id,
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FORCE_LOW;
break;
case TIM_OCM_FORCE_HIGH:
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FORCE_HIGH;
TIM_CCMR2(timer_peripheral) |=
TIM_CCMR2_OC4M_FORCE_HIGH;
break;
case TIM_OCM_PWM1:
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_PWM1;

6
lib/stm32/f1/vector.c
View File

@ -108,7 +108,7 @@ void WEAK otg_fs_isr(void);
__attribute__ ((section(".vectors")))
void (*const vector_table[]) (void) = {
(void*)&_stack,
(void *)&_stack,
reset_handler,
nmi_handler,
hard_fault_handler,
@ -194,7 +194,8 @@ void (*const vector_table[]) (void) = {
void reset_handler(void)
{
volatile unsigned *src, *dest;
asm("MSR msp, %0" : : "r"(&_stack));
__asm__("MSR msp, %0" : : "r"(&_stack));
for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++)
*dest = *src;
@ -293,4 +294,3 @@ void null_handler(void)
#pragma weak can2_rx1_isr = null_handler
#pragma weak can2_sce_isr = null_handler
#pragma weak otg_fs_isr = null_handler