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lib/stm32/f1: Coding-style fixes.

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This commit is contained in:
Uwe Hermann 2011-11-16 19:31:47 +01:00
parent 6e7403f769
commit 8725bc5171
10 changed files with 452 additions and 482 deletions
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39
lib/stm32/f1/adc.c
View File

@ -177,19 +177,19 @@ void adc_disable_temperature_sensor(u32 adc)
void adc_start_conversion_regular(u32 adc)
{
/* start conversion on regular channels */
/* Start conversion on regular channels. */
ADC_CR2(adc) |= ADC_CR2_SWSTART;
/* wait til the ADC starts the conversion */
/* Wait until the ADC starts the conversion. */
while (ADC_CR2(adc) & ADC_CR2_SWSTART);
}
void adc_start_conversion_injected(u32 adc)
{
/* start conversion on injected channels */
/* Start conversion on injected channels. */
ADC_CR2(adc) |= ADC_CR2_JSWSTART;
/* wait til the ADC starts the conversion */
/* Wait until the ADC starts the conversion. */
while (ADC_CR2(adc) & ADC_CR2_JSWSTART);
}
@ -285,13 +285,12 @@ void adc_set_conversion_time(u32 adc, u8 channel, u8 time)
if (channel < 10) {
reg32 = ADC_SMPR2(adc);
reg32 &= ~(0b111 << (channel * 3));
reg32 &= ~(0x7 << (channel * 3));
reg32 |= (time << (channel * 3));
ADC_SMPR2(adc) = reg32;
}
else {
} else {
reg32 = ADC_SMPR1(adc);
reg32 &= ~(0b111 << ((channel-10) * 3));
reg32 &= ~(0x7 << ((channel - 10) * 3));
reg32 |= (time << ((channel - 10) * 3));
ADC_SMPR1(adc) = reg32;
}
@ -299,17 +298,15 @@ void adc_set_conversion_time(u32 adc, u8 channel, u8 time)
void adc_set_conversion_time_on_all_channels(u32 adc, u8 time)
{
u32 reg32 = 0;
u8 i;
u32 reg32 = 0;
for (i = 0; i <= 9; i++) {
for (i = 0; i <= 9; i++)
reg32 |= (time << (i * 3));
}
ADC_SMPR2(adc) = reg32;
for (i = 10; i <= 17; i++) {
for (i = 10; i <= 17; i++)
reg32 |= (time << ((i - 10) * 3));
}
ADC_SMPR1(adc) = reg32;
}
@ -318,7 +315,7 @@ void adc_set_watchdog_high_threshold(u32 adc, u16 threshold)
u32 reg32 = 0;
reg32 = (u32)threshold;
reg32 &= ~0xfffff000; /* clear all bits above 11 */
reg32 &= ~0xfffff000; /* Clear all bits above 11. */
ADC_HTR(adc) = reg32;
}
@ -327,18 +324,16 @@ void adc_set_watchdog_low_threshold(u32 adc, u16 threshold)
u32 reg32 = 0;
reg32 = (u32)threshold;
reg32 &= ~0xfffff000; /* clear all bits above 11 */
reg32 &= ~0xfffff000; /* Clear all bits above 11. */
ADC_LTR(adc) = reg32;
}
void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[])
{
u32 reg32_1 = 0;
u32 reg32_2 = 0;
u32 reg32_3 = 0;
u32 reg32_1 = 0, reg32_2 = 0, reg32_3 = 0;
u8 i = 0;
/* maximum sequence length is 16 channels */
/* Maximum sequence length is 16 channels. */
if (length > 16)
return;
@ -362,13 +357,13 @@ void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[])
u32 reg32 = 0;
u8 i = 0;
/* maximum sequence length is 4 channels */
/* Maximum sequence length is 4 channels. */
if (length > 4)
return;
for (i = 1; i <= length; i++) {
for (i = 1; i <= length; i++)
reg32 |= (channel[i - 1] << ((i - 1) * 5));
}
reg32 |= ((length - 1) << ADC_JSQR_JL_LSB);
ADC_JSQR(adc) = reg32;

75
lib/stm32/f1/dma.c
View File

@ -21,8 +21,7 @@
void dma_enable_mem2mem_mode(u32 dma, u8 channel)
{
switch (channel)
{
switch (channel) {
case 1:
DMA_CCR1(dma) |= DMA_CCR1_MEM2MEM;
DMA_CCR1(dma) &= ~DMA_CCR1_CIRC;
@ -51,17 +50,12 @@ void dma_enable_mem2mem_mode(u32 dma, u8 channel)
}
}
void dma_set_priority(u32 dma, u8 channel, u8 prio)
{
/* parameter check */
if (prio > 3)
return;
switch (channel)
{
switch (channel) {
case 1:
DMA_CCR1(dma) &= ~(0x3 << DMA_CCR1_PL_LSB);
DMA_CCR1(dma) |= (prio << DMA_CCR1_PL_LSB);
@ -92,12 +86,10 @@ void dma_set_priority(u32 dma, u8 channel, u8 prio)
void dma_set_memory_size(u32 dma, u8 channel, u8 mem_size)
{
/* parameter check */
if (mem_size > 2)
return;
switch (channel)
{
switch (channel) {
case 1:
DMA_CCR1(dma) &= ~(0x3 << DMA_CCR1_MSIZE_LSB);
DMA_CCR1(dma) |= (mem_size << DMA_CCR1_MSIZE_LSB);
@ -126,16 +118,12 @@ void dma_set_memory_size(u32 dma, u8 channel, u8 mem_size)
}
}
void dma_set_peripheral_size(u32 dma, u8 channel, u8 peripheral_size)
{
/* parameter check */
if (peripheral_size > 2)
return;
switch (channel)
{
switch (channel) {
case 1:
DMA_CCR1(dma) &= ~(0x3 << DMA_CCR1_PSIZE_LSB);
DMA_CCR1(dma) |= (peripheral_size << DMA_CCR1_PSIZE_LSB);
@ -154,21 +142,21 @@ void dma_set_peripheral_size(u32 dma, u8 channel, u8 peripheral_size)
case 6:
if (dma == DMA1) {
DMA_CCR6(dma) &= ~(0x3 << DMA_CCR6_PSIZE_LSB);
DMA_CCR6(dma) |= (peripheral_size << DMA_CCR6_PSIZE_LSB);
DMA_CCR6(dma) |=
(peripheral_size << DMA_CCR6_PSIZE_LSB);
}
case 7:
if (dma == DMA1) {
DMA_CCR7(dma) &= ~(0x3 << DMA_CCR7_PSIZE_LSB);
DMA_CCR7(dma) |= (peripheral_size << DMA_CCR7_PSIZE_LSB);
DMA_CCR7(dma) |=
(peripheral_size << DMA_CCR7_PSIZE_LSB);
}
}
}
void dma_enable_memory_increment_mode(u32 dma, u8 channel)
{
switch (channel)
{
switch (channel) {
case 1:
DMA_CCR1(dma) |= DMA_CCR1_MINC;
case 2:
@ -190,8 +178,7 @@ void dma_enable_memory_increment_mode(u32 dma, u8 channel)
void dma_enable_peripheral_increment_mode(u32 dma, u8 channel)
{
switch (channel)
{
switch (channel) {
case 1:
DMA_CCR1(dma) |= DMA_CCR1_PINC;
case 2:
@ -213,8 +200,7 @@ void dma_enable_peripheral_increment_mode(u32 dma, u8 channel)
void dma_enable_circular_mode(u32 dma, u8 channel)
{
switch (channel)
{
switch (channel) {
case 1:
DMA_CCR1(dma) |= DMA_CCR1_CIRC;
DMA_CCR1(dma) &= ~DMA_CCR1_MEM2MEM;
@ -245,8 +231,7 @@ void dma_enable_circular_mode(u32 dma, u8 channel)
void dma_set_read_from_peripheral(u32 dma, u8 channel)
{
switch (channel)
{
switch (channel) {
case 1:
DMA_CCR1(dma) &= ~DMA_CCR1_DIR;
case 2:
@ -268,8 +253,7 @@ void dma_set_read_from_peripheral(u32 dma, u8 channel)
void dma_set_read_from_memory(u32 dma, u8 channel)
{
switch (channel)
{
switch (channel) {
case 1:
DMA_CCR1(dma) |= DMA_CCR1_DIR;
case 2:
@ -291,8 +275,7 @@ void dma_set_read_from_memory(u32 dma, u8 channel)
void dma_enable_transfer_error_interrupt(u32 dma, u8 channel)
{
switch (channel)
{
switch (channel) {
case 1:
DMA_CCR1(dma) |= DMA_CCR1_TEIE;
case 2:
@ -314,8 +297,7 @@ void dma_enable_transfer_error_interrupt(u32 dma, u8 channel)
void dma_disable_transfer_error_interrupt(u32 dma, u8 channel)
{
switch (channel)
{
switch (channel) {
case 1:
DMA_CCR1(dma) &= ~DMA_CCR1_TEIE;
case 2:
@ -337,8 +319,7 @@ void dma_disable_transfer_error_interrupt(u32 dma, u8 channel)
void dma_enable_half_transfer_interrupt(u32 dma, u8 channel)
{
switch (channel)
{
switch (channel) {
case 1:
DMA_CCR1(dma) |= DMA_CCR1_HTIE;
case 2:
@ -360,8 +341,7 @@ void dma_enable_half_transfer_interrupt(u32 dma, u8 channel)
void dma_disable_half_transfer_interrupt(u32 dma, u8 channel)
{
switch (channel)
{
switch (channel) {
case 1:
DMA_CCR1(dma) &= ~DMA_CCR1_HTIE;
case 2:
@ -383,8 +363,7 @@ void dma_disable_half_transfer_interrupt(u32 dma, u8 channel)
void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel)
{
switch (channel)
{
switch (channel) {
case 1:
DMA_CCR1(dma) |= DMA_CCR1_TCIE;
case 2:
@ -406,8 +385,7 @@ void dma_enable_transfer_complete_interrupt(u32 dma, u8 channel)
void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel)
{
switch (channel)
{
switch (channel) {
case 1:
DMA_CCR1(dma) &= ~DMA_CCR1_TCIE;
case 2:
@ -429,8 +407,7 @@ void dma_disable_transfer_complete_interrupt(u32 dma, u8 channel)
void dma_enable_channel(u32 dma, u8 channel)
{
switch (channel)
{
switch (channel) {
case 1:
DMA_CCR1(dma) |= DMA_CCR1_EN;
case 2:
@ -452,8 +429,7 @@ void dma_enable_channel(u32 dma, u8 channel)
void dma_disable_channel(u32 dma, u8 channel)
{
switch (channel)
{
switch (channel) {
case 1:
DMA_CCR1(dma) &= ~DMA_CCR1_EN;
case 2:
@ -475,8 +451,7 @@ void dma_disable_channel(u32 dma, u8 channel)
void dma_set_peripheral_address(u32 dma, u8 channel, u32 address)
{
switch (channel)
{
switch (channel) {
case 1:
DMA_CPAR1(dma) = (u32) address;
case 2:
@ -498,8 +473,7 @@ void dma_set_peripheral_address(u32 dma, u8 channel, u32 address)
void dma_set_memory_address(u32 dma, u8 channel, u32 address)
{
switch (channel)
{
switch (channel) {
case 1:
DMA_CMAR1(dma) = (u32) address;
case 2:
@ -521,8 +495,7 @@ void dma_set_memory_address(u32 dma, u8 channel, u32 address)
void dma_set_number_of_data(u32 dma, u8 channel, u16 number)
{
switch (channel)
{
switch (channel) {
case 1:
DMA_CNDTR1(dma) = number;
case 2:

3
lib/stm32/f1/ethernet.c
View File

@ -38,8 +38,7 @@ void eth_smi_write(u8 phy, u8 reg, u16 data)
u16 eth_smi_read(u8 phy, u8 reg)
{
/* Set PHY and register addresses for write access. */
ETH_MACMIIAR &= ~(ETH_MACMIIAR_MR | ETH_MACMIIAR_PA |
ETH_MACMIIAR_MW);
ETH_MACMIIAR &= ~(ETH_MACMIIAR_MR | ETH_MACMIIAR_PA | ETH_MACMIIAR_MW);
ETH_MACMIIAR |= (phy << 11) | (reg << 6);
/* Begin transaction. */

2
lib/stm32/f1/gpio.c
View File

@ -61,7 +61,7 @@ void gpio_set_mode(u32 gpioport, u8 mode, u8 cnf, u16 gpios)
tmp32 = (i < 8) ? crl : crh;
/* Modify bits are needed. */
tmp32 &= ~(0b1111 << offset); /* Clear the bits first. */
tmp32 &= ~(0xf << offset); /* Clear the bits first. */
tmp32 |= (mode << offset) | (cnf << (offset + 2));
/* Write tmp32 into crl or crh, leave the other unchanged. */

1
lib/stm32/f1/rcc.c
View File

@ -493,6 +493,7 @@ void rcc_clock_setup_in_hse_8mhz_out_24mhz(void)
rcc_ppre1_frequency = 24000000;
rcc_ppre2_frequency = 24000000;
}
void rcc_clock_setup_in_hse_8mhz_out_72mhz(void)
{
/* Enable internal high-speed oscillator. */

16
lib/stm32/f1/timer.c
View File

@ -125,9 +125,7 @@ void timer_set_mode(u32 timer_peripheral, u8 clock_div,
cr1 = TIM_CR1(timer_peripheral);
cr1 &= ~(TIM_CR1_CKD_CK_INT_MASK |
TIM_CR1_CMS_MASK |
TIM_CR1_DIR_DOWN);
cr1 &= ~(TIM_CR1_CKD_CK_INT_MASK | TIM_CR1_CMS_MASK | TIM_CR1_DIR_DOWN);
cr1 |= clock_div | alignment | direction;
@ -397,7 +395,8 @@ void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id,
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FORCE_LOW;
break;
case TIM_OCM_FORCE_HIGH:
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FORCE_HIGH;
TIM_CCMR1(timer_peripheral) |=
TIM_CCMR1_OC1M_FORCE_HIGH;
break;
case TIM_OCM_PWM1:
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_PWM1;
@ -428,7 +427,8 @@ void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id,
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_FORCE_LOW;
break;
case TIM_OCM_FORCE_HIGH:
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_FORCE_HIGH;
TIM_CCMR1(timer_peripheral) |=
TIM_CCMR1_OC2M_FORCE_HIGH;
break;
case TIM_OCM_PWM1:
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_PWM1;
@ -459,7 +459,8 @@ void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id,
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FORCE_LOW;
break;
case TIM_OCM_FORCE_HIGH:
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FORCE_HIGH;
TIM_CCMR2(timer_peripheral) |=
TIM_CCMR2_OC3M_FORCE_HIGH;
break;
case TIM_OCM_PWM1:
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_PWM1;
@ -490,7 +491,8 @@ void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id,
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FORCE_LOW;
break;
case TIM_OCM_FORCE_HIGH:
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FORCE_HIGH;
TIM_CCMR2(timer_peripheral) |=
TIM_CCMR2_OC4M_FORCE_HIGH;
break;
case TIM_OCM_PWM1:
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_PWM1;

4
lib/stm32/f1/vector.c
View File

@ -194,7 +194,8 @@ void (*const vector_table[]) (void) = {
void reset_handler(void)
{
volatile unsigned *src, *dest;
asm("MSR msp, %0" : : "r"(&_stack));
__asm__("MSR msp, %0" : : "r"(&_stack));
for (src = &_etext, dest = &_data; dest < &_edata; src++, dest++)
*dest = *src;
@ -293,4 +294,3 @@ void null_handler(void)
#pragma weak can2_rx1_isr = null_handler
#pragma weak can2_sce_isr = null_handler
#pragma weak otg_fs_isr = null_handler