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stm32g0: rcc: group rcc_registers and registers values

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Guillaume Revaillot 2019-08-28 18:04:02 +02:00 committed by Karl Palsson
parent f70f0d0b7b
commit 87dbf40cde
1 changed files with 35 additions and 27 deletions
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62
include/libopencm3/stm32/g0/rcc.h
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@ -33,8 +33,8 @@
#include <libopencm3/stm32/pwr.h>
/* --- RCC registers ------------------------------------------------------- */
/** @defgroup rcc_registers Reset and Clock Control Register
@{*/
#define RCC_CR MMIO32(RCC_BASE + 0x00)
#define RCC_ICSCR MMIO32(RCC_BASE + 0x04)
#define RCC_CFGR MMIO32(RCC_BASE + 0x08)
@ -69,11 +69,10 @@
#define RCC_CCIPR MMIO32(RCC_BASE + 0x54)
#define RCC_BDCR MMIO32(RCC_BASE + 0x5c)
#define RCC_CSR MMIO32(RCC_BASE + 0x60)
/**@}*/
/* --- RCC_CR values ------------------------------------------------------- */
/** @defgroup rcc_cr CR Clock control Register
@{*/
#define RCC_CR_PLLRDY (1 << 25)
#define RCC_CR_PLLON (1 << 24)
#define RCC_CR_CSSON (1 << 19)
@ -100,16 +99,20 @@
#define RCC_CR_HSIRDY (1 << 10)
#define RCC_CR_HSIKERON (1 << 9)
#define RCC_CR_HSION (1 << 8)
/**@}*/
/* --- RCC_ICSCR values ---------------------------------------------------- */
/** @defgroup rcc_icscr ICSCR Internal Clock Source Calibration Register
@{*/
#define RCC_ICSCR_HSITRIM_SHIFT 8
#define RCC_ICSCR_HSITRIM_MASK 0x1f
#define RCC_ICSCR_HSICAL_SHIFT 0
#define RCC_ICSCR_HSICAL_MASK 0xff
/**@}*/
/* --- RCC_CFGR values ----------------------------------------------------- */
/** @defgroup rcc_cfgr CFGR Configuration Register
@{*/
#define RCC_CFGR_MCOPRE_SHIFT 28
#define RCC_CFGR_MCOPRE_MASK 0x7
/** @defgroup rcc_cfgr_mcopre MCO Pre
@ -188,7 +191,7 @@
#define RCC_CFGR_SW_MASK 0x3
#define RCC_CFGR_SW_SHIFT 0
/** @defgroup rcc_cfgr_sws SW
/** @defgroup rcc_cfgr_sw SW
* @brief System clock switch
@sa rcc_cfgr_sw
@{*/
@ -198,9 +201,12 @@
#define RCC_CFGR_SW_LSI 0x3
#define RCC_CFGR_SW_LSE 0x4
/**@}*/
/**@}*/
/* --- RCC_PLLCFGR - PLL Configuration Register */
/** @defgroup rcc_pllcfgr PLLCFGR PLL Configuration Register
@{*/
#define RCC_PLLCFGR_PLLR_SHIFT 29
#define RCC_PLLCFGR_PLLR_MASK 0x7
/** @defgroup rcc_pllcfgr_pllr PLLR
@ -260,17 +266,19 @@
#define RCC_PLLCFGR_PLLSRC_HSI16 2
#define RCC_PLLCFGR_PLLSRC_HSE 3
/**@}*/
/**@}*/
/* --- RCC_CIER - Clock interrupt enable register */
/** @defgroup rcc_cier CIER Clock Interrupt Enable Register
@{*/
#define RCC_CIER_PLLRDYIE (1 << 5)
#define RCC_CIER_HSERDYIE (1 << 4)
#define RCC_CIER_HSIRDYIE (1 << 3)
#define RCC_CIER_LSERDYIE (1 << 1)
#define RCC_CIER_LSIRDYIE (1 << 0)
/**@}*/
/* --- RCC_CIFR - Clock interrupt flag register */
/** @defgroup rcc_cifr CIFR Clock Interrupt Flag Register
@{*/
#define RCC_CIFR_LSECSSF (1 << 9)
#define RCC_CIFR_CSSF (1 << 8)
#define RCC_CIFR_PLLRDYF (1 << 5)
@ -278,9 +286,10 @@
#define RCC_CIFR_HSIRDYF (1 << 3)
#define RCC_CIFR_LSERDYF (1 << 1)
#define RCC_CIFR_LSIRDYF (1 << 0)
/**@}*/
/* --- RCC_CICR - Clock interrupt flag register */
/** @defgroup rcc_cicr CICR Clock Interrupt Clear Register
@{*/
#define RCC_CICR_LSECSSC (1 << 9)
#define RCC_CICR_CSSC (1 << 8)
#define RCC_CICR_PLLRDYC (1 << 5)
@ -288,6 +297,7 @@
#define RCC_CICR_HSIRDYC (1 << 3)
#define RCC_CICR_LSERDYC (1 << 1)
#define RCC_CICR_LSIRDYC (1 << 0)
/**@}*/
/** @defgroup rcc_ahbrstr_rst RCC_AHBRSTR reset values
@{*/
@ -388,8 +398,6 @@
/**@}*/
/**@}*/
/* --- RCC_AHBSMENR values ------------------------------------------------- */
/** @defgroup rcc_aphbsmenr_en RCC_AHBSMENR enable in sleep/stop mode values
@{*/
#define RCC_AHBSMENR_RNGSMEN (1 << 18)
@ -400,8 +408,6 @@
#define RCC_AHBSMENR_DMASMEN (1 << 0)
/**@}*/
/* --- RCC_APBSMENR1 values ------------------------------------------------- */
/** @defgroup rcc_apbsmenr_en RCC_APBSMENR1 enable in sleep/stop mode values
@{*/
#define RCC_APBSMENR1_LPTIM1SMEN (1 << 31)
@ -427,8 +433,6 @@
#define RCC_APBSMENR1_TIM2SMEN (1 << 0)
/**@}*/
/* --- RCC_APBSMENR2 values ------------------------------------------------- */
/** @defgroup rcc_apbsmenr2_en RCC_APBSMENR2 enable in sleep/stop mode values
@{*/
#define RCC_APBSMENR2_ADCSMEN (1 << 20)
@ -443,8 +447,9 @@
#define RCC_APBSMENR2_SYSCFGSMEN (1 << 0)
/**@}*/
/* --- RCC_CCIPR - Peripherals independent clock config register ----------- */
/** @defgroup rcc_ccipr CCIPR Peripherals Independent Clock Config Register
@{*/
#define RCC_CCIPR_ADCSEL_MASK 0x3
#define RCC_CCIPR_ADCSEL_SHIFT 30
/** @defgroup rcc_ccipr_adcsel ADCSEL
@ -566,9 +571,10 @@
#define RCC_CCIPR_USART1SEL_HSI16 2
#define RCC_CCIPR_USART1SEL_LSE 3
/**@}*/
/**@}*/
/* --- RCC_BDCR - PLL Configuration Register */
/** @defgroup rcc_bdcr BDCR Backup Domain Control Register
@{*/
#define RCC_BDCR_LSCOSEL (1 << 25)
#define RCC_BDCR_LSCOEN (1 << 24)
#define RCC_BDCR_BDRST (1 << 16)
@ -597,9 +603,10 @@
#define RCC_BDCR_LSEBYP (1 << 2)
#define RCC_BDCR_LSERDY (1 << 1)
#define RCC_BDCR_LSEON (1 << 0)
/**@}*/
/* --- RCC_CSR - Control/Status register ----------------------------------- */
/** @defgroup rcc_csr CSR Control and Status Register
@{*/
#define RCC_CSR_LPWRRSTF (1 << 31)
#define RCC_CSR_WWDGRSTF (1 << 30)
#define RCC_CSR_IWDGRSTF (1 << 29)
@ -610,6 +617,7 @@
#define RCC_CSR_RMVF (1 << 23)
#define RCC_CSR_LSIRDY (1 << 1)
#define RCC_CSR_LSION (1 << 0)
/**@}*/
/* --- Variable definitions ------------------------------------------------ */