stm32: timers: fix mixup between TIMx_CCMR1 and TIMx_CCMR2 in timer_set_oc_mode()
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af3389652c
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884924d598
@ -1035,15 +1035,15 @@ void timer_set_oc_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id,
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}
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break;
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case TIM_OC3:
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TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR2_CC3S_MASK;
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TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_CC3S_OUT;
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TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_CC3S_MASK;
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TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_CC3S_OUT;
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TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3M_MASK;
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switch (oc_mode) {
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case TIM_OCM_FROZEN:
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TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FROZEN;
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break;
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case TIM_OCM_ACTIVE:
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TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_OC3M_ACTIVE;
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TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_ACTIVE;
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break;
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case TIM_OCM_INACTIVE:
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TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_INACTIVE;
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@ -1067,15 +1067,15 @@ void timer_set_oc_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id,
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}
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break;
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case TIM_OC4:
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TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR2_CC4S_MASK;
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TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_CC4S_OUT;
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TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_CC4S_MASK;
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TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_CC4S_OUT;
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TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4M_MASK;
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switch (oc_mode) {
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case TIM_OCM_FROZEN:
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TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FROZEN;
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break;
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case TIM_OCM_ACTIVE:
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TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_OC4M_ACTIVE;
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TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_ACTIVE;
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break;
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case TIM_OCM_INACTIVE:
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TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_INACTIVE;
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