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Updated lmi, nxp and stm32f4 drivers to use adiv5_target_ap().

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This commit is contained in:
Gareth McMullin 2012-06-24 14:44:02 +12:00
parent cb19164f2f
commit 8872315e82
3 changed files with 21 additions and 21 deletions
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14
src/lmi.c
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@ -102,27 +102,27 @@ int lmi_probe(struct target_s *target)
int lmi_flash_erase(struct target_s *target, uint32_t addr, int len) int lmi_flash_erase(struct target_s *target, uint32_t addr, int len)
{ {
struct target_ap_s *t = (void *)target; ADIv5_AP_t *ap = adiv5_target_ap(target);
uint32_t tmp; uint32_t tmp;
addr &= 0xFFFFFC00; addr &= 0xFFFFFC00;
len &= 0xFFFFFC00; len &= 0xFFFFFC00;
/* setup word access */ /* setup word access */
adiv5_ap_write(t->ap, 0x00, 0xA2000052); adiv5_ap_write(ap, 0x00, 0xA2000052);
/* select Flash Control */ /* select Flash Control */
adiv5_dp_low_access(t->ap->dp, 1, 0, 0x04, 0x400FD000); adiv5_dp_low_access(ap->dp, 1, 0, 0x04, 0x400FD000);
while(len) { while(len) {
/* write address to FMA */ /* write address to FMA */
adiv5_ap_write(t->ap, 0x10, addr); /* Required to switch banks */ adiv5_ap_write(ap, 0x10, addr); /* Required to switch banks */
/* set ERASE bit in FMC */ /* set ERASE bit in FMC */
adiv5_dp_low_access(t->ap->dp, 1, 0, 0x08, 0xA4420002); adiv5_dp_low_access(ap->dp, 1, 0, 0x08, 0xA4420002);
/* Read FMC to poll for ERASE bit */ /* Read FMC to poll for ERASE bit */
adiv5_dp_low_access(t->ap->dp, 1, 1, 0x08, 0); adiv5_dp_low_access(ap->dp, 1, 1, 0x08, 0);
do { do {
tmp = adiv5_dp_low_access(t->ap->dp, 1, 1, 0x08, 0); tmp = adiv5_dp_low_access(ap->dp, 1, 1, 0x08, 0);
} while (tmp & 2); } while (tmp & 2);
len -= 0x400; len -= 0x400;

3
src/nxp_tgt.c
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@ -70,11 +70,10 @@ static const char lpc11xx_xml_memory_map[] = "<?xml version=\"1.0\"?>"
int int
lpc11xx_probe(struct target_s *target) lpc11xx_probe(struct target_s *target)
{ {
struct target_ap_s *t = (void *)target;
uint32_t idcode; uint32_t idcode;
/* read the device ID register */ /* read the device ID register */
idcode = adiv5_ap_mem_read(t->ap, 0x400483F4); idcode = adiv5_ap_mem_read(adiv5_target_ap(target), 0x400483F4);
switch (idcode) { switch (idcode) {

23
src/stm32f4.c
View File

@ -91,6 +91,8 @@ static const char stm32f4_xml_memory_map[] = "<?xml version=\"1.0\"?>"
#define SR_ERROR_MASK 0xF2 #define SR_ERROR_MASK 0xF2
#define SR_EOP 0x01 #define SR_EOP 0x01
#define DBGMCU_IDCODE 0xE0042000
/* This routine is uses word access. Only usable on target voltage >2.7V */ /* This routine is uses word access. Only usable on target voltage >2.7V */
uint16_t stm32f4_flash_write_stub[] = { uint16_t stm32f4_flash_write_stub[] = {
// _start: // _start:
@ -133,10 +135,9 @@ uint16_t stm32f4_flash_write_stub[] = {
int stm32f4_probe(struct target_s *target) int stm32f4_probe(struct target_s *target)
{ {
struct target_ap_s *t = (void *)target;
uint32_t idcode; uint32_t idcode;
idcode = adiv5_ap_mem_read(t->ap, 0xE0042000); idcode = adiv5_ap_mem_read(adiv5_target_ap(target), DBGMCU_IDCODE);
switch(idcode & 0xFFF) { switch(idcode & 0xFFF) {
case 0x411: /* Documented to be 0x413! This is what I read... */ case 0x411: /* Documented to be 0x413! This is what I read... */
case 0x413: case 0x413:
@ -152,7 +153,7 @@ int stm32f4_probe(struct target_s *target)
static int stm32f4_flash_erase(struct target_s *target, uint32_t addr, int len) static int stm32f4_flash_erase(struct target_s *target, uint32_t addr, int len)
{ {
struct target_ap_s *t = (void *)target; ADIv5_AP_t *ap = adiv5_target_ap(target);
uint16_t sr; uint16_t sr;
uint32_t cr; uint32_t cr;
uint32_t pagesize; uint32_t pagesize;
@ -160,8 +161,8 @@ static int stm32f4_flash_erase(struct target_s *target, uint32_t addr, int len)
addr &= 0x07FFC000; addr &= 0x07FFC000;
/* Enable FPEC controller access */ /* Enable FPEC controller access */
adiv5_ap_mem_write(t->ap, FLASH_KEYR, KEY1); adiv5_ap_mem_write(ap, FLASH_KEYR, KEY1);
adiv5_ap_mem_write(t->ap, FLASH_KEYR, KEY2); adiv5_ap_mem_write(ap, FLASH_KEYR, KEY2);
while(len) { while(len) {
if (addr < 0x10000) { /* Sector 0..3 */ if (addr < 0x10000) { /* Sector 0..3 */
cr = (addr >> 11); cr = (addr >> 11);
@ -177,12 +178,12 @@ static int stm32f4_flash_erase(struct target_s *target, uint32_t addr, int len)
} }
cr |= FLASH_CR_EOPIE | FLASH_CR_ERRIE | FLASH_CR_SER; cr |= FLASH_CR_EOPIE | FLASH_CR_ERRIE | FLASH_CR_SER;
/* Flash page erase instruction */ /* Flash page erase instruction */
adiv5_ap_mem_write(t->ap, FLASH_CR, cr); adiv5_ap_mem_write(ap, FLASH_CR, cr);
/* write address to FMA */ /* write address to FMA */
adiv5_ap_mem_write(t->ap, FLASH_CR, cr | FLASH_CR_STRT); adiv5_ap_mem_write(ap, FLASH_CR, cr | FLASH_CR_STRT);
/* Read FLASH_SR to poll for BSY bit */ /* Read FLASH_SR to poll for BSY bit */
while(adiv5_ap_mem_read(t->ap, FLASH_SR) & FLASH_SR_BSY) while(adiv5_ap_mem_read(ap, FLASH_SR) & FLASH_SR_BSY)
if(target_check_error(target)) if(target_check_error(target))
return -1; return -1;
@ -191,7 +192,7 @@ static int stm32f4_flash_erase(struct target_s *target, uint32_t addr, int len)
} }
/* Check for error */ /* Check for error */
sr = adiv5_ap_mem_read(t->ap, FLASH_SR); sr = adiv5_ap_mem_read(ap, FLASH_SR);
if(sr & SR_ERROR_MASK) if(sr & SR_ERROR_MASK)
return -1; return -1;
@ -201,7 +202,7 @@ static int stm32f4_flash_erase(struct target_s *target, uint32_t addr, int len)
static int stm32f4_flash_write(struct target_s *target, uint32_t dest, static int stm32f4_flash_write(struct target_s *target, uint32_t dest,
const uint8_t *src, int len) const uint8_t *src, int len)
{ {
struct target_ap_s *t = (void *)target; ADIv5_AP_t *ap = adiv5_target_ap(target);
uint32_t offset = dest % 4; uint32_t offset = dest % 4;
uint32_t words = (offset + len + 3) / 4; uint32_t words = (offset + len + 3) / 4;
uint32_t data[2 + words]; uint32_t data[2 + words];
@ -226,7 +227,7 @@ static int stm32f4_flash_write(struct target_s *target, uint32_t dest,
while(!target_halt_wait(target)); while(!target_halt_wait(target));
/* Check for error */ /* Check for error */
sr = adiv5_ap_mem_read(t->ap, FLASH_SR); sr = adiv5_ap_mem_read(ap, FLASH_SR);
if(sr & SR_ERROR_MASK) if(sr & SR_ERROR_MASK)
return -1; return -1;