From 8a1cfa8cebfb6e7de3e50fee47d8e5be948670cc Mon Sep 17 00:00:00 2001 From: Guillaume Revaillot Date: Wed, 28 Aug 2019 18:04:02 +0200 Subject: [PATCH] stm32g0: use proper register for gpio peripheral clock sleep enable. Reviewed-by: Karl Palsson --- include/libopencm3/stm32/g0/rcc.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/include/libopencm3/stm32/g0/rcc.h b/include/libopencm3/stm32/g0/rcc.h index bf6ec4d1..dd989cef 100644 --- a/include/libopencm3/stm32/g0/rcc.h +++ b/include/libopencm3/stm32/g0/rcc.h @@ -678,12 +678,12 @@ enum rcc_periph_clken { RCC_TIM1 = _REG_BIT(RCC_APBENR2_OFFSET, 11), RCC_SYSCFG = _REG_BIT(RCC_APBENR2_OFFSET, 0), - SCC_GPIOF = _REG_BIT(RCC_IOPENR_OFFSET, 5), - SCC_GPIOE = _REG_BIT(RCC_IOPENR_OFFSET, 4), - SCC_GPIOD = _REG_BIT(RCC_IOPENR_OFFSET, 3), - SCC_GPIOC = _REG_BIT(RCC_IOPENR_OFFSET, 2), - SCC_GPIOB = _REG_BIT(RCC_IOPENR_OFFSET, 1), - SCC_GPIOA = _REG_BIT(RCC_IOPENR_OFFSET, 0), + SCC_GPIOF = _REG_BIT(RCC_IOPSMENR_OFFSET, 5), + SCC_GPIOE = _REG_BIT(RCC_IOPSMENR_OFFSET, 4), + SCC_GPIOD = _REG_BIT(RCC_IOPSMENR_OFFSET, 3), + SCC_GPIOC = _REG_BIT(RCC_IOPSMENR_OFFSET, 2), + SCC_GPIOB = _REG_BIT(RCC_IOPSMENR_OFFSET, 1), + SCC_GPIOA = _REG_BIT(RCC_IOPSMENR_OFFSET, 0), SCC_RNG = _REG_BIT(RCC_AHBSMENR_OFFSET, 18), SCC_AES = _REG_BIT(RCC_AHBSMENR_OFFSET, 16),