diff --git a/include/libopencm3/lpc43xx/creg.h b/include/libopencm3/lpc43xx/creg.h
index 63871808..dafc8824 100644
--- a/include/libopencm3/lpc43xx/creg.h
+++ b/include/libopencm3/lpc43xx/creg.h
@@ -29,48 +29,48 @@
  * Chip configuration register 32 kHz oscillator output and BOD control
  * register
  */
-#define CREG0                           MMIO32(CREG_BASE + 0x004)
+#define CREG_CREG0                      MMIO32(CREG_BASE + 0x004)
 
 /* ARM Cortex-M4 memory mapping */
-#define M4MEMMAP                        MMIO32(CREG_BASE + 0x100)
+#define CREG_M4MEMMAP                   MMIO32(CREG_BASE + 0x100)
 
 /* Chip configuration register 1 */
-#define CREG1                           MMIO32(CREG_BASE + 0x108)
+#define CREG_CREG1                      MMIO32(CREG_BASE + 0x108)
 
 /* Chip configuration register 2 */
-#define CREG2                           MMIO32(CREG_BASE + 0x10C)
+#define CREG_CREG2                      MMIO32(CREG_BASE + 0x10C)
 
 /* Chip configuration register 3 */
-#define CREG3                           MMIO32(CREG_BASE + 0x110)
+#define CREG_CREG3                      MMIO32(CREG_BASE + 0x110)
 
 /* Chip configuration register 4 */
-#define CREG4                           MMIO32(CREG_BASE + 0x114)
+#define CREG_CREG4                      MMIO32(CREG_BASE + 0x114)
 
 /* Chip configuration register 5 */
-#define CREG5                           MMIO32(CREG_BASE + 0x118)
+#define CREG_CREG5                      MMIO32(CREG_BASE + 0x118)
 
 /* DMA muxing control */
-#define DMAMUX                          MMIO32(CREG_BASE + 0x11C)
+#define CREG_DMAMUX                     MMIO32(CREG_BASE + 0x11C)
 
 /* ETB RAM configuration */
-#define ETBCFG                          MMIO32(CREG_BASE + 0x128)
+#define CREG_ETBCFG                     MMIO32(CREG_BASE + 0x128)
 
 /*
  * Chip configuration register 6. Controls multiple functions: Ethernet
  * interface, SCT output, I2S0/1 inputs, EMC clock.
  */
-#define CREG6                           MMIO32(CREG_BASE + 0x12C)
+#define CREG_CREG6                      MMIO32(CREG_BASE + 0x12C)
 
 /* Cortex-M4 TXEV event clear */
-#define M4TXEVENT                       MMIO32(CREG_BASE + 0x130)
+#define CREG_M4TXEVENT                  MMIO32(CREG_BASE + 0x130)
 
 /* Part ID */
-#define CHIPID                          MMIO32(CREG_BASE + 0x200)
+#define CREG_CHIPID                     MMIO32(CREG_BASE + 0x200)
 
 /* Cortex-M0 TXEV event clear */
-#define M0TXEVENT                       MMIO32(CREG_BASE + 0x400)
+#define CREG_M0TXEVENT                  MMIO32(CREG_BASE + 0x400)
 
 /* ARM Cortex-M0 memory mapping */
-#define M0APPMEMMAP                     MMIO32(CREG_BASE + 0x404)
+#define CREG_M0APPMEMMAP                MMIO32(CREG_BASE + 0x404)
 
 #endif