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Mention reserved memory map areas in code comments.

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This commit is contained in:
Uwe Hermann 2010-01-15 01:41:09 +01:00
parent d7d851e579
commit 8d196a2a1f
1 changed files with 11 additions and 0 deletions
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11
include/libopenstm32/memorymap.h
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@ -35,11 +35,14 @@
#define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00) #define TIM5_BASE (PERIPH_BASE_APB1 + 0x0c00)
#define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) #define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000)
#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) #define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400)
/* PERIPH_BASE_APB1 + 0x1800 (0x4000 1800 - 0x4000 27FF): Reserved */
#define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) #define RTC_BASE (PERIPH_BASE_APB1 + 0x2800)
#define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) #define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00)
#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000) #define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
#define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800) #define SPI2_I2S_BASE (PERIPH_BASE_APB1 + 0x3800)
#define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00) #define SPI3_I2S_BASE (PERIPH_BASE_APB1 + 0x3c00)
/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400) #define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
#define USART3_BASE (PERIPH_BASE_APB1 + 0x4800) #define USART3_BASE (PERIPH_BASE_APB1 + 0x4800)
#define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00) #define UART4_BASE (PERIPH_BASE_APB1 + 0x4c00)
@ -50,9 +53,11 @@
#define USB_CAN_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000) #define USB_CAN_SRAM_BASE (PERIPH_BASE_APB1 + 0x6000)
#define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400) #define BX_CAN1_BASE (PERIPH_BASE_APB1 + 0x6400)
#define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800) #define BX_CAN2_BASE (PERIPH_BASE_APB1 + 0x6800)
/* PERIPH_BASE_APB1 + 0x6800 (0x4000 6800 - 0x4000 6BFF): Reserved? Typo? */
#define BACKUP_REGS_BASE (PERIPH_BASE_APB1 + 0x6c00) #define BACKUP_REGS_BASE (PERIPH_BASE_APB1 + 0x6c00)
#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000) #define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400) #define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
/* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 FFFF): Reserved */
/* APB2 */ /* APB2 */
#define AFIO_BASE (PERIPH_BASE_APB2 + 0x0000) #define AFIO_BASE (PERIPH_BASE_APB2 + 0x0000)
@ -71,15 +76,21 @@
#define TIM8_BASE (PERIPH_BASE_APB2 + 0x3400) #define TIM8_BASE (PERIPH_BASE_APB2 + 0x3400)
#define USART1_BASE (PERIPH_BASE_APB2 + 0x3800) #define USART1_BASE (PERIPH_BASE_APB2 + 0x3800)
#define ADC3_BASE (PERIPH_BASE_APB2 + 0x3c00) #define ADC3_BASE (PERIPH_BASE_APB2 + 0x3c00)
/* PERIPH_BASE_APB2 + 0x4000 (0x4001 4000 - 0x4001 7FFF): Reserved */
/* AHB */ /* AHB */
#define SDIO_BASE (PERIPH_BASE_AHB + 0x00000) #define SDIO_BASE (PERIPH_BASE_AHB + 0x00000)
/* PERIPH_BASE_AHB + 0x0400 (0x4001 8400 - 0x4001 7FFF): Reserved */
#define DMA1_BASE (PERIPH_BASE_AHB + 0x08000) #define DMA1_BASE (PERIPH_BASE_AHB + 0x08000)
#define DMA2_BASE (PERIPH_BASE_AHB + 0x08400) #define DMA2_BASE (PERIPH_BASE_AHB + 0x08400)
/* PERIPH_BASE_AHB + 0x8800 (0x4002 0800 - 0x4002 0FFF): Reserved */
#define RCC_BASE (PERIPH_BASE_AHB + 0x09000) #define RCC_BASE (PERIPH_BASE_AHB + 0x09000)
/* PERIPH_BASE_AHB + 0x9400 (0x4002 1400 - 0x4002 1FFF): Reserved */
#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x0a000) #define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x0a000)
#define CRC_BASE (PERIPH_BASE_AHB + 0x0b000) #define CRC_BASE (PERIPH_BASE_AHB + 0x0b000)
/* PERIPH_BASE_AHB + 0xb400 (0x4002 3400 - 0x4002 7FFF): Reserved */
#define ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000) #define ETHERNET_BASE (PERIPH_BASE_AHB + 0x10000)
/* PERIPH_BASE_AHB + 0x18000 (0x4003 0000 - 0x4FFF FFFF): Reserved */
#define USB_OTG_FS_BASE (PERIPH_BASE_AHB + 0x10000000) #define USB_OTG_FS_BASE (PERIPH_BASE_AHB + 0x10000000)
#endif #endif