From 8d5ad52e0f7ff72532805ec1883e2bc01482cd16 Mon Sep 17 00:00:00 2001 From: Frantisek Burian Date: Thu, 6 Feb 2014 11:23:01 +0100 Subject: [PATCH] Fix the stm32f0 evident bugs --- include/libopencm3/stm32/f0/rcc.h | 51 +++++++++++++++++++++++++++++-- lib/stm32/f0/rcc.c | 4 +-- 2 files changed, 51 insertions(+), 4 deletions(-) diff --git a/include/libopencm3/stm32/f0/rcc.h b/include/libopencm3/stm32/f0/rcc.h index 24fc2c06..2bbd040f 100644 --- a/include/libopencm3/stm32/f0/rcc.h +++ b/include/libopencm3/stm32/f0/rcc.h @@ -61,7 +61,7 @@ Control #define RCC_AHBRSTR MMIO32(RCC_BASE + 0x28) #define RCC_CFGR2 MMIO32(RCC_BASE + 0x2c) #define RCC_CFGR3 MMIO32(RCC_BASE + 0x30) -#define RCC_CR2 MMIO32(RCC_BASE + 0x32) +#define RCC_CR2 MMIO32(RCC_BASE + 0x34) /*****************************************************************************/ /* Register values */ @@ -128,8 +128,10 @@ Control #define RCC_CFGR_PLLXTPRE (1<<17) #define RCC_CFGR_PLLSRC (1<<16) +#define RCC_CFGR_PLLSRC0 (1<<15) #define RCC_CFGR_ADCPRE (1<<14) + #define RCC_CFGR_PPRE_SHIFT 8 #define RCC_CFGR_PPRE (7 << RCC_CFGR_PPRE_SHIFT) #define RCC_CFGR_PPRE_NODIV (0 << RCC_CFGR_PPRE_SHIFT) @@ -155,22 +157,26 @@ Control #define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) #define RCC_CFGR_SWS_HSE (1 << RCC_CFGR_SWS_SHIFT) #define RCC_CFGR_SWS_PLL (2 << RCC_CFGR_SWS_SHIFT) +#define RCC_CFGR_SWS_HSI48 (3 << RCC_CFGR_SWS_SHIFT) #define RCC_CFGR_SW_SHIFT 0 #define RCC_CFGR_SW (3 << RCC_CFGR_SW_SHIFT) #define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) #define RCC_CFGR_SW_HSE (1 << RCC_CFGR_SW_SHIFT) #define RCC_CFGR_SW_PLL (2 << RCC_CFGR_SW_SHIFT) +#define RCC_CFGR_SW_HSI48 (3 << RCC_CFGR_SW_SHIFT) /* --- RCC_CIR values ------------------------------------------------------ */ #define RCC_CIR_CSSC (1 << 23) +#define RCC_CIR_HSI48RDYC (1 << 22) #define RCC_CIR_HSI14RDYC (1 << 21) #define RCC_CIR_PLLRDYC (1 << 20) #define RCC_CIR_HSERDYC (1 << 19) #define RCC_CIR_HSIRDYC (1 << 18) #define RCC_CIR_LSERDYC (1 << 17) #define RCC_CIR_LSIRDYC (1 << 16) +#define RCC_CIR_HSI48RDYIE (1 << 14) #define RCC_CIR_HSI14RDYIE (1 << 13) #define RCC_CIR_PLLRDYIE (1 << 12) #define RCC_CIR_HSERDYIE (1 << 11) @@ -178,6 +184,7 @@ Control #define RCC_CIR_LSERDYIE (1 << 9) #define RCC_CIR_LSIRDYIE (1 << 8) #define RCC_CIR_CSSF (1 << 7) +#define RCC_CIR_HSI48RDYF (1 << 6) #define RCC_CIR_HSI14RDYF (1 << 5) #define RCC_CIR_PLLRDYF (1 << 4) #define RCC_CIR_HSERDYF (1 << 3) @@ -202,12 +209,18 @@ Control #define RCC_APB1RSTR_CECRST (1 << 30) #define RCC_APB1RSTR_DACRST (1 << 29) #define RCC_APB1RSTR_PWRRST (1 << 28) +#define RCC_APB1RSTR_CRSRST (1 << 27) +#define RCC_APB1RSTR_CANRST (1 << 25) +#define RCC_APB1RSTR_USBRST (1 << 23) #define RCC_APB1RSTR_I2C2RST (1 << 22) #define RCC_APB1RSTR_I2C1RST (1 << 21) +#define RCC_APB1RSTR_USART4RST (1 << 19) +#define RCC_APB1RSTR_USART3RST (1 << 18) #define RCC_APB1RSTR_USART2RST (1 << 17) #define RCC_APB1RSTR_SPI2RST (1 << 14) #define RCC_APB1RSTR_WWDGRST (1 << 11) #define RCC_APB1RSTR_TIM14RST (1 << 8) +#define RCC_APB1RSTR_TIM7RST (1 << 5) #define RCC_APB1RSTR_TIM6RST (1 << 4) #define RCC_APB1RSTR_TIM3RST (1 << 1) #define RCC_APB1RSTR_TIM2RST (1 << 0) @@ -216,6 +229,7 @@ Control #define RCC_AHBENR_TSCEN (1 << 24) #define RCC_AHBENR_GPIOFEN (1 << 22) +#define RCC_AHBENR_GPIOEEN (1 << 21) #define RCC_AHBENR_GPIODEN (1 << 20) #define RCC_AHBENR_GPIOCEN (1 << 19) #define RCC_AHBENR_GPIOBEN (1 << 18) @@ -242,12 +256,18 @@ Control #define RCC_APB1ENR_CECEN (1 << 30) #define RCC_APB1ENR_DACEN (1 << 29) #define RCC_APB1ENR_PWREN (1 << 28) +#define RCC_APB1ENR_CRSEN (1 << 27) +#define RCC_APB1ENR_CANEN (1 << 25) +#define RCC_APB1ENR_USBEN (1 << 23) #define RCC_APB1ENR_I2C2EN (1 << 22) #define RCC_APB1ENR_I2C1EN (1 << 21) +#define RCC_APB1ENR_USART4EN (1 << 19) +#define RCC_APB1ENR_USART3EN (1 << 18) #define RCC_APB1ENR_USART2EN (1 << 17) #define RCC_APB1ENR_SPI2EN (1 << 14) #define RCC_APB1ENR_WWDGEN (1 << 11) #define RCC_APB1ENR_TIM14EN (1 << 8) +#define RCC_APB1ENR_TIM7EN (1 << 5) #define RCC_APB1ENR_TIM6EN (1 << 4) #define RCC_APB1ENR_TIM3EN (1 << 1) #define RCC_APB1ENR_TIM2EN (1 << 0) @@ -290,6 +310,7 @@ Control #define RCC_AHBRSTR_TSCRST (1 << 24) #define RCC_AHBRSTR_IOPFRST (1 << 22) +#define RCC_AHBRSTR_IOPERST (1 << 21) #define RCC_AHBRSTR_IOPDRST (1 << 20) #define RCC_AHBRSTR_IOPCRST (1 << 19) #define RCC_AHBRSTR_IOPBRST (1 << 18) @@ -318,9 +339,17 @@ Control /* --- RCC_CFGR3 values ---------------------------------------------------- */ +#define RCC_CFGR3_USART2SW_SHIFT 16 +#define RCC_CFGR3_USART2SW (3 << RCC_CFGR3_USART2SW_SHIFT) +#define RCC_CFGR3_USART2SW_PCLK (0 << RCC_CFGR3_USART2SW_SHIFT) +#define RCC_CFGR3_USART2SW_SYSCLK (1 << RCC_CFGR3_USART2SW_SHIFT) +#define RCC_CFGR3_USART2SW_LSE (2 << RCC_CFGR3_USART2SW_SHIFT) +#define RCC_CFGR3_USART2SW_HSI (3 << RCC_CFGR3_USART2SW_SHIFT) + #define RCC_CFGR3_ADCSW (1 << 8) #define RCC_CFGR3_CECSW (1 << 6) #define RCC_CFGR3_I2C1SW (1 << 4) + #define RCC_CFGR3_USART1SW_SHIFT 0 #define RCC_CFGR3_USART1SW (3 << RCC_CFGR3_USART1SW_SHIFT) #define RCC_CFGR3_USART1SW_PCLK (0 << RCC_CFGR3_USART1SW_SHIFT) @@ -330,6 +359,10 @@ Control /* --- RCC_CFGR3 values ---------------------------------------------------- */ +#define RCC_CR2_HSI48CAL_SHIFT 24 +#define RCC_CR2_HSI48CAL (0xFF << RCC_CR2_HSI48CAL_SHIFT) +#define RCC_CR2_HSI48RDY (1 << 17) +#define RCC_CR2_HSI48ON (1 << 16) #define RCC_CR2_HSI14CAL_SHIFT 8 #define RCC_CR2_HSI14CAL (0xFF << RCC_CR2_HSI14CAL_SHIFT) #define RCC_CR2_HSI14TRIM_SHIFT 3 @@ -347,7 +380,7 @@ extern uint32_t rcc_core_frequency; extern uint32_t rcc_ppre_frequency; enum rcc_osc { - HSI14, HSI, HSE, PLL, LSI, LSE + HSI14, HSI, HSE, PLL, LSI, LSE, HSI48 }; #define _REG_BIT(base, bit) (((base) << 5) + (bit)) @@ -362,6 +395,7 @@ enum rcc_periph_clken { RCC_GPIOB = _REG_BIT(0x14, 18), RCC_GPIOC = _REG_BIT(0x14, 19), RCC_GPIOD = _REG_BIT(0x14, 20), + RCC_GPIOE = _REG_BIT(0x14, 21), RCC_GPIOF = _REG_BIT(0x14, 22), RCC_TSC = _REG_BIT(0x14, 24), @@ -380,12 +414,18 @@ enum rcc_periph_clken { RCC_TIM2 = _REG_BIT(0x1C, 0), RCC_TIM3 = _REG_BIT(0x1C, 1), RCC_TIM6 = _REG_BIT(0x1C, 4), + RCC_TIM7 = _REG_BIT(0x1C, 5), RCC_TIM14 = _REG_BIT(0x1C, 8), RCC_WWDG = _REG_BIT(0x1C, 11), RCC_SPI2 = _REG_BIT(0x1C, 14), RCC_USART2 = _REG_BIT(0x1C, 17), + RCC_USART3 = _REG_BIT(0x1C, 18), + RCC_USART4 = _REG_BIT(0x1C, 19), RCC_I2C1 = _REG_BIT(0x1C, 21), RCC_I2C2 = _REG_BIT(0x1C, 22), + RCC_USB = _REG_BIT(0x1C, 23), + RCC_CAN = _REG_BIT(0x1C, 25), + RCC_CRS = _REG_BIT(0x1C, 27), RCC_PWR = _REG_BIT(0x1C, 28), RCC_DAC = _REG_BIT(0x1C, 29), RCC_CEC = _REG_BIT(0x1C, 30), @@ -410,12 +450,18 @@ enum rcc_periph_rst { RST_TIM2 = _REG_BIT(0x10, 0), RST_TIM3 = _REG_BIT(0x10, 1), RST_TIM6 = _REG_BIT(0x10, 4), + RST_TIM7 = _REG_BIT(0x10, 5), RST_TIM14 = _REG_BIT(0x10, 8), RST_WWDG = _REG_BIT(0x10, 11), RST_SPI2 = _REG_BIT(0x10, 14), RST_USART2 = _REG_BIT(0x10, 17), + RST_USART3 = _REG_BIT(0x10, 18), + RST_USART4 = _REG_BIT(0x10, 19), RST_I2C1 = _REG_BIT(0x10, 21), RST_I2C2 = _REG_BIT(0x10, 22), + RST_USB = _REG_BIT(0x10, 23), + RST_CAN = _REG_BIT(0x10, 25), + RST_CRS = _REG_BIT(0x10, 27), RST_PWR = _REG_BIT(0x10, 28), RST_DAC = _REG_BIT(0x10, 29), RST_CEC = _REG_BIT(0x10, 30), @@ -428,6 +474,7 @@ enum rcc_periph_rst { RST_GPIOB = _REG_BIT(0x28, 18), RST_GPIOC = _REG_BIT(0x28, 19), RST_GPIOD = _REG_BIT(0x28, 20), + RST_GPIOE = _REG_BIT(0x28, 21), RST_GPIOF = _REG_BIT(0x28, 22), RST_TSC = _REG_BIT(0x28, 24), }; diff --git a/lib/stm32/f0/rcc.c b/lib/stm32/f0/rcc.c index e5a9a200..93c5982a 100644 --- a/lib/stm32/f0/rcc.c +++ b/lib/stm32/f0/rcc.c @@ -572,8 +572,8 @@ void rcc_clock_setup_in_hsi_out_40mhz(void) rcc_wait_for_osc_ready(PLL); rcc_set_sysclk_source(PLL); - rcc_ppre_frequency = 32000000; - rcc_core_frequency = 32000000; + rcc_ppre_frequency = 40000000; + rcc_core_frequency = 40000000; } void rcc_clock_setup_in_hsi_out_48mhz(void)