From 8feb711ca0975808b8604903e44eefe48926ca46 Mon Sep 17 00:00:00 2001 From: Karl Palsson Date: Sat, 24 Feb 2018 13:42:20 +0000 Subject: [PATCH] stm32l0:rcc: add rcc_set_pll_source() as per L1 reported by: kaeipnos in https://github.com/libopencm3/libopencm3/pull/609 --- include/libopencm3/stm32/l0/rcc.h | 1 + lib/stm32/l0/rcc.c | 13 +++++++++++++ 2 files changed, 14 insertions(+) diff --git a/include/libopencm3/stm32/l0/rcc.h b/include/libopencm3/stm32/l0/rcc.h index 6fb3e3d7..ace255b1 100644 --- a/include/libopencm3/stm32/l0/rcc.h +++ b/include/libopencm3/stm32/l0/rcc.h @@ -687,6 +687,7 @@ void rcc_set_hsi48_source_pll(void); void rcc_set_sysclk_source(enum rcc_osc osc); void rcc_set_pll_multiplier(uint32_t factor); void rcc_set_pll_divider(uint32_t factor); +void rcc_set_pll_source(uint32_t pllsrc); void rcc_set_ppre2(uint32_t ppre2); void rcc_set_ppre1(uint32_t ppre1); void rcc_set_hpre(uint32_t hpre); diff --git a/lib/stm32/l0/rcc.c b/lib/stm32/l0/rcc.c index d851c39a..a6e398e2 100644 --- a/lib/stm32/l0/rcc.c +++ b/lib/stm32/l0/rcc.c @@ -336,6 +336,19 @@ void rcc_set_pll_divider(uint32_t factor) RCC_CFGR = reg | (factor << RCC_CFGR_PLLDIV_SHIFT); } +/** + * Set the pll source. + * @param pllsrc RCC_CFGR_PLLSRC_HSI16_CLK or RCC_CFGR_PLLSRC_HSE_CLK + */ +void rcc_set_pll_source(uint32_t pllsrc) +{ + uint32_t reg32; + + reg32 = RCC_CFGR; + reg32 &= ~(RCC_CFGR_PLLSRC_HSE_CLK << 16); + RCC_CFGR = (reg32 | (pllsrc<<16)); +} + /*---------------------------------------------------------------------------*/ /** @brief RCC Set the APB1 Prescale Factor. *