From 9ac5adfcef94f04f3c1ddedcaf3b3d5b2c0338c4 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sat, 7 Nov 2020 15:44:16 +0100 Subject: [PATCH] adiv5: Additional decoding. --- src/target/adiv5.c | 5 +++++ src/target/cortexm.c | 3 +++ 2 files changed, 8 insertions(+) diff --git a/src/target/adiv5.c b/src/target/adiv5.c index 80cf7daf..9f7a7ccc 100644 --- a/src/target/adiv5.c +++ b/src/target/adiv5.c @@ -608,6 +608,8 @@ ADIv5_AP_t *adiv5_new_ap(ADIv5_DP_t *dp, uint8_t apsel) uint32_t cfg = adiv5_ap_read(ap, ADIV5_AP_CFG); DEBUG_INFO("AP %3d: IDR=%08"PRIx32" CFG=%08"PRIx32" BASE=%08" PRIx32 " CSW=%08"PRIx32"\n", apsel, ap->idr, cfg, ap->base, ap->csw); + DEBUG_INFO("AP#0 IDR = 0x%08" PRIx32 " (AHB-AP var%x rev%x)\n", + ap->idr, (ap->idr >> 4) & 0xf, ap->idr >> 28); #endif adiv5_ap_ref(ap); return ap; @@ -615,6 +617,9 @@ ADIv5_AP_t *adiv5_new_ap(ADIv5_DP_t *dp, uint8_t apsel) void adiv5_dp_init(ADIv5_DP_t *dp) { + DEBUG_INFO("DPIDR 0x%08" PRIx32 " (v%d %srev%d)\n", dp->idcode, + (dp->idcode >> 12) & 0xf, + (dp->idcode & 0x10000) ? "MINDP " : "", dp->idcode >> 28); volatile uint32_t ctrlstat = 0; #if PC_HOSTED == 1 platform_adiv5_dp_defaults(dp); diff --git a/src/target/cortexm.c b/src/target/cortexm.c index 452fe2d2..99252761 100644 --- a/src/target/cortexm.c +++ b/src/target/cortexm.c @@ -329,6 +329,9 @@ bool cortexm_probe(ADIv5_AP_t *ap) default: DEBUG_WARN("Unexpected CortexM CPUID partno %04x\n", cpuid_partno); } + DEBUG_INFO("CPUID 0x%08" PRIx32 " (%s var %x rev %x)\n", t->cpuid, + t->core, (t->cpuid & CPUID_REVISION_MASK) >> 20, + t->cpuid & CPUID_PATCH_MASK); t->attach = cortexm_attach; t->detach = cortexm_detach;