diff --git a/examples/stm32/l1/stm32l-discovery/miniblink/miniblink.c b/examples/stm32/l1/stm32l-discovery/miniblink/miniblink.c index a9d7c3dc..fbace3c1 100644 --- a/examples/stm32/l1/stm32l-discovery/miniblink/miniblink.c +++ b/examples/stm32/l1/stm32l-discovery/miniblink/miniblink.c @@ -29,7 +29,7 @@ void gpio_setup(void) { /* Enable GPIOB clock. */ /* Manually: */ - RCC_AHBENR |= RCC_AHBENR_IOPBEN; + RCC_AHBENR |= RCC_AHBENR_GPIOBEN; /* Using API functions: */ //rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_IOPBEN); @@ -63,7 +63,7 @@ int main(void) // __asm__("nop"); /* Using API function gpio_toggle(): */ - gpio_toggle(PORT_LED, PORT_LED); /* LED on/off */ + gpio_toggle(PORT_LED, PIN_LED); /* LED on/off */ for (i = 0; i < 1000000; i++) /* Wait a bit. */ __asm__("nop"); } diff --git a/include/libopencm3/stm32/l1/rcc.h b/include/libopencm3/stm32/l1/rcc.h index ebcca86d..07d36926 100644 --- a/include/libopencm3/stm32/l1/rcc.h +++ b/include/libopencm3/stm32/l1/rcc.h @@ -219,27 +219,19 @@ LGPL License Terms @ref lgpl_license /* --- RCC_APB1RSTR values ------------------------------------------------- */ -TODO : up to here - +#define RCC_APB1RSTR_COMPRST (1 << 31) #define RCC_APB1RSTR_DACRST (1 << 29) #define RCC_APB1RSTR_PWRRST (1 << 28) -#define RCC_APB1RSTR_BKPRST (1 << 27) -#define RCC_APB1RSTR_CAN2RST (1 << 26) /* (**) */ -#define RCC_APB1RSTR_CAN1RST (1 << 25) /* (**) */ -#define RCC_APB1RSTR_CANRST (1 << 25) /* (XX) Alias for CAN1RST */ -#define RCC_APB1RSTR_USBRST (1 << 23) /* (XX) */ +#define RCC_APB1RSTR_USBRST (1 << 23) #define RCC_APB1RSTR_I2C2RST (1 << 22) #define RCC_APB1RSTR_I2C1RST (1 << 21) -#define RCC_APB1RSTR_UART5RST (1 << 20) -#define RCC_APB1RSTR_UART4RST (1 << 19) #define RCC_APB1RSTR_USART3RST (1 << 18) #define RCC_APB1RSTR_USART2RST (1 << 17) -#define RCC_APB1RSTR_SPI3RST (1 << 15) #define RCC_APB1RSTR_SPI2RST (1 << 14) #define RCC_APB1RSTR_WWDGRST (1 << 11) +#define RCC_APB1RSTR_LCDRST (1 << 9) #define RCC_APB1RSTR_TIM7RST (1 << 5) #define RCC_APB1RSTR_TIM6RST (1 << 4) -#define RCC_APB1RSTR_TIM5RST (1 << 3) #define RCC_APB1RSTR_TIM4RST (1 << 2) #define RCC_APB1RSTR_TIM3RST (1 << 1) #define RCC_APB1RSTR_TIM2RST (1 << 0) @@ -250,17 +242,15 @@ TODO : up to here @ingroup STM32L1xx_rcc_defines @{*/ -#define RCC_AHBENR_ETHMACENRX (1 << 16) -#define RCC_AHBENR_ETHMACENTX (1 << 15) -#define RCC_AHBENR_ETHMACEN (1 << 14) -#define RCC_AHBENR_OTGFSEN (1 << 12) -#define RCC_AHBENR_SDIOEN (1 << 10) -#define RCC_AHBENR_FSMCEN (1 << 8) -#define RCC_AHBENR_CRCEN (1 << 6) -#define RCC_AHBENR_FLITFEN (1 << 4) -#define RCC_AHBENR_SRAMEN (1 << 2) -#define RCC_AHBENR_DMA2EN (1 << 1) -#define RCC_AHBENR_DMA1EN (1 << 0) +#define RCC_AHBENR_DMA1EN (1 << 24) +#define RCC_AHBENR_FLITFEN (1 << 15) +#define RCC_AHBENR_CRCEN (1 << 12) +#define RCC_AHBENR_GPIOHEN (1 << 5) +#define RCC_AHBENR_GPIOEEN (1 << 4) +#define RCC_AHBENR_GPIODEN (1 << 3) +#define RCC_AHBENR_GPIOCEN (1 << 2) +#define RCC_AHBENR_GPIOBEN (1 << 1) +#define RCC_AHBENR_GPIOAEN (1 << 0) /*@}*/ /* --- RCC_APB2ENR values -------------------------------------------------- */ @@ -269,21 +259,13 @@ TODO : up to here @ingroup STM32L1xx_rcc_defines @{*/ -#define RCC_APB2ENR_ADC3EN (1 << 15) /* (XX) */ #define RCC_APB2ENR_USART1EN (1 << 14) -#define RCC_APB2ENR_TIM8EN (1 << 13) /* (XX) */ #define RCC_APB2ENR_SPI1EN (1 << 12) -#define RCC_APB2ENR_TIM1EN (1 << 11) -#define RCC_APB2ENR_ADC2EN (1 << 10) #define RCC_APB2ENR_ADC1EN (1 << 9) -#define RCC_APB2ENR_IOPGEN (1 << 8) /* (XX) */ -#define RCC_APB2ENR_IOPFEN (1 << 7) /* (XX) */ -#define RCC_APB2ENR_IOPEEN (1 << 6) -#define RCC_APB2ENR_IOPDEN (1 << 5) -#define RCC_APB2ENR_IOPCEN (1 << 4) -#define RCC_APB2ENR_IOPBEN (1 << 3) -#define RCC_APB2ENR_IOPAEN (1 << 2) -#define RCC_APB2ENR_AFIOEN (1 << 0) +#define RCC_APB2ENR_TIM11EN (1 << 4) +#define RCC_APB2ENR_TIM10EN (1 << 3) +#define RCC_APB2ENR_TIM9EN (1 << 2) +#define RCC_APB2ENR_SYSCFGEN (1 << 0) /*@}*/ /* --- RCC_APB1ENR values -------------------------------------------------- */ @@ -292,38 +274,61 @@ TODO : up to here @ingroup STM32L1xx_rcc_defines @{*/ +#define RCC_APB1ENR_COMPEN (1 << 31) #define RCC_APB1ENR_DACEN (1 << 29) #define RCC_APB1ENR_PWREN (1 << 28) -#define RCC_APB1ENR_BKPEN (1 << 27) -#define RCC_APB1ENR_CAN2EN (1 << 26) /* (**) */ -#define RCC_APB1ENR_CAN1EN (1 << 25) /* (**) */ -#define RCC_APB1ENR_CANEN (1 << 25) /* (XX) Alias for CAN1EN */ -#define RCC_APB1ENR_USBEN (1 << 23) /* (XX) */ +#define RCC_APB1ENR_USBEN (1 << 23) #define RCC_APB1ENR_I2C2EN (1 << 22) #define RCC_APB1ENR_I2C1EN (1 << 21) -#define RCC_APB1ENR_UART5EN (1 << 20) -#define RCC_APB1ENR_UART4EN (1 << 19) #define RCC_APB1ENR_USART3EN (1 << 18) #define RCC_APB1ENR_USART2EN (1 << 17) -#define RCC_APB1ENR_SPI3EN (1 << 15) #define RCC_APB1ENR_SPI2EN (1 << 14) #define RCC_APB1ENR_WWDGEN (1 << 11) +#define RCC_APB1ENR_LCDEN (1 << 9) #define RCC_APB1ENR_TIM7EN (1 << 5) #define RCC_APB1ENR_TIM6EN (1 << 4) -#define RCC_APB1ENR_TIM5EN (1 << 3) #define RCC_APB1ENR_TIM4EN (1 << 2) #define RCC_APB1ENR_TIM3EN (1 << 1) #define RCC_APB1ENR_TIM2EN (1 << 0) /*@}*/ -/* --- RCC_BDCR values ----------------------------------------------------- */ +/* --- RCC_AHBLPENR -------------------------------------------------------- */ +#define RCC_AHBLPENR_DMA1LPEN (1 << 24) +#define RCC_AHBLPENR_SRAMLPEN (1 << 16) +#define RCC_AHBLPENR_FLITFLPEN (1 << 15) +#define RCC_AHBLPENR_CRCLPEN (1 << 12) +#define RCC_AHBLPENR_GPIOHLPEN (1 << 5) +#define RCC_AHBLPENR_GPIOELPEN (1 << 4) +#define RCC_AHBLPENR_GPIODLPEN (1 << 3) +#define RCC_AHBLPENR_GPIOCLPEN (1 << 2) +#define RCC_AHBLPENR_GPIOBLPEN (1 << 1) +#define RCC_AHBLPENR_GPIOALPEN (1 << 0) + +#define RCC_APB2LPENR_USART1LPEN (1 << 14) +#define RCC_APB2LPENR_SPI1LPEN (1 << 12) +#define RCC_APB2LPENR_ADC1LPEN (1 << 9) +#define RCC_APB2LPENR_TIM11LPEN (1 << 4) +#define RCC_APB2LPENR_TIM10LPEN (1 << 3) +#define RCC_APB2LPENR_TIM9LPEN (1 << 2) +#define RCC_APB2LPENR_SYSCFGLPEN (1 << 0) + +#define RCC_APB1LPENR_COMPLPEN (1 << 31) +#define RCC_APB1LPENR_DACLPEN (1 << 29) +#define RCC_APB1LPENR_PWRLPEN (1 << 28) +#define RCC_APB1LPENR_USBLPEN (1 << 23) +#define RCC_APB1LPENR_I2C2LPEN (1 << 22) +#define RCC_APB1LPENR_I2C1LPEN (1 << 21) +#define RCC_APB1LPENR_USART3LPEN (1 << 18) +#define RCC_APB1LPENR_USART2LPEN (1 << 17) +#define RCC_APB1LPENR_SPI2LPEN (1 << 14) +#define RCC_APB1LPENR_WWDGLPEN (1 << 11) +#define RCC_APB1LPENR_LCDLPEN (1 << 9) +#define RCC_APB1LPENR_TIM7LPEN (1 << 5) +#define RCC_APB1LPENR_TIM6LPEN (1 << 4) +#define RCC_APB1LPENR_TIM4LPEN (1 << 2) +#define RCC_APB1LPENR_TIM3LPEN (1 << 1) +#define RCC_APB1LPENR_TIM2LPEN (1 << 0) -#define RCC_BDCR_BDRST (1 << 16) -#define RCC_BDCR_RTCEN (1 << 15) -/* RCC_BDCR[9:8]: RTCSEL */ -#define RCC_BDCR_LSEBYP (1 << 2) -#define RCC_BDCR_LSERDY (1 << 1) -#define RCC_BDCR_LSEON (1 << 0) /* --- RCC_CSR values ------------------------------------------------------ */ @@ -333,72 +338,17 @@ TODO : up to here #define RCC_CSR_SFTRSTF (1 << 28) #define RCC_CSR_PORRSTF (1 << 27) #define RCC_CSR_PINRSTF (1 << 26) +#define RCC_CSR_OBLRSTF (1 << 25) #define RCC_CSR_RMVF (1 << 24) +#define RCC_CSR_RTCRST (1 << 23) +#define RCC_CSR_RTCEN (1 << 22) +/* RTCSEL[1:0] */ +#define RCC_CSR_LSEBYP (1 << 10) +#define RCC_CSR_LSERDY (1 << 9) +#define RCC_CSR_LSEON (1 << 8) #define RCC_CSR_LSIRDY (1 << 1) #define RCC_CSR_LSION (1 << 0) -/* --- RCC_AHBRSTR values -------------------------------------------------- */ - -#define RCC_AHBRSTR_ETHMACRST (1 << 14) -#define RCC_AHBRSTR_OTGFSRST (1 << 12) - -/* --- RCC_CFGR2 values ---------------------------------------------------- */ - -/* I2S3SRC: I2S3 clock source */ -#define RCC_CFGR2_I2S3SRC_SYSCLK 0x0 -#define RCC_CFGR2_I2S3SRC_PLL3_VCO_CLK 0x1 - -/* I2S2SRC: I2S2 clock source */ -#define RCC_CFGR2_I2S2SRC_SYSCLK 0x0 -#define RCC_CFGR2_I2S2SRC_PLL3_VCO_CLK 0x1 - -/* PREDIV1SRC: PREDIV1 entry clock source */ -#define RCC_CFGR2_PREDIV1SRC_HSE_CLK 0x0 -#define RCC_CFGR2_PREDIV1SRC_PLL2_CLK 0x1 - -#define RCC_CFGR2_PLL2MUL (1 << 0) -#define RCC_CFGR2_PREDIV2 (1 << 0) -#define RCC_CFGR2_PREDIV1 (1 << 0) - -/* PLL3MUL: PLL3 multiplication factor */ -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL8 0x6 -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL9 0x7 -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL10 0x8 -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL11 0x9 -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL12 0xa -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL13 0xb -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL14 0xc -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL16 0xe -#define RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL20 0xf - -/* PLL2MUL: PLL2 multiplication factor */ -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8 0x6 -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL9 0x7 -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL10 0x8 -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL11 0x9 -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL12 0xa -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL13 0xb -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL14 0xc -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16 0xe -#define RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20 0xf - -/* PREDIV2: PREDIV2 division factor */ -#define RCC_CFGR2_PREDIV2_NODIV 0x0 -#define RCC_CFGR2_PREDIV2_DIV2 0x1 -#define RCC_CFGR2_PREDIV2_DIV3 0x2 -#define RCC_CFGR2_PREDIV2_DIV4 0x3 -#define RCC_CFGR2_PREDIV2_DIV5 0x4 -#define RCC_CFGR2_PREDIV2_DIV6 0x5 -#define RCC_CFGR2_PREDIV2_DIV7 0x6 -#define RCC_CFGR2_PREDIV2_DIV8 0x7 -#define RCC_CFGR2_PREDIV2_DIV9 0x8 -#define RCC_CFGR2_PREDIV2_DIV10 0x9 -#define RCC_CFGR2_PREDIV2_DIV11 0xa -#define RCC_CFGR2_PREDIV2_DIV12 0xb -#define RCC_CFGR2_PREDIV2_DIV13 0xc -#define RCC_CFGR2_PREDIV2_DIV14 0xd -#define RCC_CFGR2_PREDIV2_DIV15 0xe -#define RCC_CFGR2_PREDIV2_DIV16 0xf /* --- Variable definitions ------------------------------------------------ */ extern u32 rcc_ppre1_frequency; @@ -407,9 +357,10 @@ extern u32 rcc_ppre2_frequency; /* --- Function prototypes ------------------------------------------------- */ typedef enum { - PLL, HSE, HSI, LSE, LSI + PLL, HSE, HSI, MSI, LSE, LSI } osc_t; +#if FINISHED == 0 void rcc_osc_ready_int_clear(osc_t osc); void rcc_osc_ready_int_enable(osc_t osc); void rcc_osc_ready_int_disable(osc_t osc); @@ -449,5 +400,6 @@ void rcc_clock_setup_in_hse_8mhz_out_72mhz(void); void rcc_clock_setup_in_hse_12mhz_out_72mhz(void); void rcc_clock_setup_in_hse_16mhz_out_72mhz(void); void rcc_backupdomain_reset(void); +#endif #endif