From 9b642dea2a15977e211c1a47ab1325cbcfd26522 Mon Sep 17 00:00:00 2001 From: Eric Kerman Date: Wed, 18 Nov 2015 23:51:50 +0100 Subject: [PATCH] stm32l0: Add timer support Signed-off-by: Karl Palsson --- include/libopencm3/stm32/l0/memorymap.h | 2 ++ include/libopencm3/stm32/l0/rcc.h | 12 ++++++++++++ lib/stm32/l0/Makefile | 1 + 3 files changed, 15 insertions(+) diff --git a/include/libopencm3/stm32/l0/memorymap.h b/include/libopencm3/stm32/l0/memorymap.h index ebefc7b8..d1466b7d 100644 --- a/include/libopencm3/stm32/l0/memorymap.h +++ b/include/libopencm3/stm32/l0/memorymap.h @@ -34,7 +34,9 @@ /* APB1 */ #define TIM2_BASE (PERIPH_BASE_APB1 + 0x0000) +#define TIM3_BASE (PERIPH_BASE_APB1 + 0x0400) #define TIM6_BASE (PERIPH_BASE_APB1 + 0x1000) +#define TIM7_BASE (PERIPH_BASE_APB1 + 0x1400) #define LCD_BASE (PERIPH_BASE_APB1 + 0x2400) #define RTC_BASE (PERIPH_BASE_APB1 + 0x2800) #define WWDG_BASE (PERIPH_BASE_APB1 + 0x2c00) diff --git a/include/libopencm3/stm32/l0/rcc.h b/include/libopencm3/stm32/l0/rcc.h index 46ad2caf..c6bbefce 100644 --- a/include/libopencm3/stm32/l0/rcc.h +++ b/include/libopencm3/stm32/l0/rcc.h @@ -291,7 +291,9 @@ #define RCC_APB1RSTR_SPI2RST (1 << 14) #define RCC_APB1RSTR_WWDGRST (1 << 11) #define RCC_APB1RSTR_LCDRST (1 << 9) +#define RCC_APB1RSTR_TIM7RST (1 << 5) #define RCC_APB1RSTR_TIM6RST (1 << 4) +#define RCC_APB1RSTR_TIM3RST (1 << 1) #define RCC_APB1RSTR_TIM2RST (1 << 0) /* --- RCC_IOPENR - GPIO clock enable register */ @@ -350,7 +352,9 @@ #define RCC_APB1ENR_SPI2EN (1 << 14) #define RCC_APB1ENR_WWDGEN (1 << 11) #define RCC_APB1ENR_LCDEN (1 << 9) +#define RCC_APB1ENR_TIM7EN (1 << 5) #define RCC_APB1ENR_TIM6EN (1 << 4) +#define RCC_APB1ENR_TIM3EN (1 << 1) #define RCC_APB1ENR_TIM2EN (1 << 0) /*@}*/ @@ -396,7 +400,9 @@ #define RCC_APB1SMENR_SPI2SMEN (1 << 14) #define RCC_APB1SMENR_WWDGSMEN (1 << 11) #define RCC_APB1SMENR_LCDSMEN (1 << 9) +#define RCC_APB1SMENR_TIM7SMEN (1 << 5) #define RCC_APB1SMENR_TIM6SMEN (1 << 4) +#define RCC_APB1SMENR_TIM3SMEN (1 << 1) #define RCC_APB1SMENR_TIM2SMEN (1 << 0) /* --- RCC_CCIPR - Clock config register */ @@ -512,7 +518,9 @@ enum rcc_periph_clken { /* APB1 peripherals */ RCC_TIM2 = _REG_BIT(0x38, 0), + RCC_TIM3 = _REG_BIT(0x38, 1), RCC_TIM6 = _REG_BIT(0x38, 4), + RCC_TIM7 = _REG_BIT(0x38, 5), RCC_LCD = _REG_BIT(0x38, 9), RCC_WWDG = _REG_BIT(0x38, 11), RCC_SPI2 = _REG_BIT(0x38, 14), @@ -553,7 +561,9 @@ enum rcc_periph_clken { /* APB1 peripherals in sleep mode */ SCC_TIM2 = _REG_BIT(0x48, 0), + SCC_TIM3 = _REG_BIT(0x48, 1), SCC_TIM6 = _REG_BIT(0x48, 4), + SCC_TIM7 = _REG_BIT(0x48, 5), SCC_LCD = _REG_BIT(0x48, 9), SCC_WWDG = _REG_BIT(0x48, 11), SCC_SPI2 = _REG_BIT(0x48, 14), @@ -595,7 +605,9 @@ enum rcc_periph_rst { /* APB1 peripherals*/ RST_TIM2 = _REG_BIT(0x28, 0), + RST_TIM3 = _REG_BIT(0x28, 1), RST_TIM6 = _REG_BIT(0x28, 4), + RST_TIM7 = _REG_BIT(0x28, 5), RST_LCD = _REG_BIT(0x28, 9), RST_WWDG = _REG_BIT(0x28, 11), RST_SPI2 = _REG_BIT(0x28, 14), diff --git a/lib/stm32/l0/Makefile b/lib/stm32/l0/Makefile index 6cf194e3..97a274dc 100644 --- a/lib/stm32/l0/Makefile +++ b/lib/stm32/l0/Makefile @@ -37,6 +37,7 @@ ARFLAGS = rcs OBJS = gpio.o rcc.o desig.o OBJS += pwr_common_all.o pwr_common_l01.o +OBJS += timer_common_all.o OBJS += gpio_common_all.o gpio_common_f0234.o rcc_common_all.o OBJS += adc_common_v2.o