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stm32f4: add GPIOJ & GPIOK

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They are available on STM32F429 and STM32F439.
This commit is contained in:
Nicolas Schodet 2015-10-27 14:42:58 +01:00
parent fd100ea6c2
commit 9b8d44e8a3
4 changed files with 41 additions and 1 deletions
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22
include/libopencm3/stm32/common/gpio_common_f24.h
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@ -48,6 +48,8 @@ specific memorymap.h header before including this header file.*/
#define GPIOG GPIO_PORT_G_BASE #define GPIOG GPIO_PORT_G_BASE
#define GPIOH GPIO_PORT_H_BASE #define GPIOH GPIO_PORT_H_BASE
#define GPIOI GPIO_PORT_I_BASE #define GPIOI GPIO_PORT_I_BASE
#define GPIOJ GPIO_PORT_J_BASE
#define GPIOK GPIO_PORT_K_BASE
/**@}*/ /**@}*/
/* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------- */ /* --- GPIO registers for STM32F2, STM32F3 and STM32F4 --------------------- */
@ -56,51 +58,71 @@ specific memorymap.h header before including this header file.*/
#define GPIOG_MODER GPIO_MODER(GPIOG) #define GPIOG_MODER GPIO_MODER(GPIOG)
#define GPIOH_MODER GPIO_MODER(GPIOH) #define GPIOH_MODER GPIO_MODER(GPIOH)
#define GPIOI_MODER GPIO_MODER(GPIOI) #define GPIOI_MODER GPIO_MODER(GPIOI)
#define GPIOJ_MODER GPIO_MODER(GPIOJ)
#define GPIOK_MODER GPIO_MODER(GPIOK)
/* Port output type register (GPIOx_OTYPER) */ /* Port output type register (GPIOx_OTYPER) */
#define GPIOG_OTYPER GPIO_OTYPER(GPIOG) #define GPIOG_OTYPER GPIO_OTYPER(GPIOG)
#define GPIOH_OTYPER GPIO_OTYPER(GPIOH) #define GPIOH_OTYPER GPIO_OTYPER(GPIOH)
#define GPIOI_OTYPER GPIO_OTYPER(GPIOI) #define GPIOI_OTYPER GPIO_OTYPER(GPIOI)
#define GPIOJ_OTYPER GPIO_OTYPER(GPIOJ)
#define GPIOK_OTYPER GPIO_OTYPER(GPIOK)
/* Port output speed register (GPIOx_OSPEEDR) */ /* Port output speed register (GPIOx_OSPEEDR) */
#define GPIOG_OSPEEDR GPIO_OSPEEDR(GPIOG) #define GPIOG_OSPEEDR GPIO_OSPEEDR(GPIOG)
#define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH) #define GPIOH_OSPEEDR GPIO_OSPEEDR(GPIOH)
#define GPIOI_OSPEEDR GPIO_OSPEEDR(GPIOI) #define GPIOI_OSPEEDR GPIO_OSPEEDR(GPIOI)
#define GPIOJ_OSPEEDR GPIO_OSPEEDR(GPIOJ)
#define GPIOK_OSPEEDR GPIO_OSPEEDR(GPIOK)
/* Port pull-up/pull-down register (GPIOx_PUPDR) */ /* Port pull-up/pull-down register (GPIOx_PUPDR) */
#define GPIOG_PUPDR GPIO_PUPDR(GPIOG) #define GPIOG_PUPDR GPIO_PUPDR(GPIOG)
#define GPIOH_PUPDR GPIO_PUPDR(GPIOH) #define GPIOH_PUPDR GPIO_PUPDR(GPIOH)
#define GPIOI_PUPDR GPIO_PUPDR(GPIOI) #define GPIOI_PUPDR GPIO_PUPDR(GPIOI)
#define GPIOJ_PUPDR GPIO_PUPDR(GPIOJ)
#define GPIOK_PUPDR GPIO_PUPDR(GPIOK)
/* Port input data register (GPIOx_IDR) */ /* Port input data register (GPIOx_IDR) */
#define GPIOG_IDR GPIO_IDR(GPIOG) #define GPIOG_IDR GPIO_IDR(GPIOG)
#define GPIOH_IDR GPIO_IDR(GPIOH) #define GPIOH_IDR GPIO_IDR(GPIOH)
#define GPIOI_IDR GPIO_IDR(GPIOI) #define GPIOI_IDR GPIO_IDR(GPIOI)
#define GPIOJ_IDR GPIO_IDR(GPIOJ)
#define GPIOK_IDR GPIO_IDR(GPIOK)
/* Port output data register (GPIOx_ODR) */ /* Port output data register (GPIOx_ODR) */
#define GPIOG_ODR GPIO_ODR(GPIOG) #define GPIOG_ODR GPIO_ODR(GPIOG)
#define GPIOH_ODR GPIO_ODR(GPIOH) #define GPIOH_ODR GPIO_ODR(GPIOH)
#define GPIOI_ODR GPIO_ODR(GPIOI) #define GPIOI_ODR GPIO_ODR(GPIOI)
#define GPIOJ_ODR GPIO_ODR(GPIOJ)
#define GPIOK_ODR GPIO_ODR(GPIOK)
/* Port bit set/reset register (GPIOx_BSRR) */ /* Port bit set/reset register (GPIOx_BSRR) */
#define GPIOG_BSRR GPIO_BSRR(GPIOG) #define GPIOG_BSRR GPIO_BSRR(GPIOG)
#define GPIOH_BSRR GPIO_BSRR(GPIOH) #define GPIOH_BSRR GPIO_BSRR(GPIOH)
#define GPIOI_BSRR GPIO_BSRR(GPIOI) #define GPIOI_BSRR GPIO_BSRR(GPIOI)
#define GPIOJ_BSRR GPIO_BSRR(GPIOJ)
#define GPIOK_BSRR GPIO_BSRR(GPIOK)
/* Port configuration lock register (GPIOx_LCKR) */ /* Port configuration lock register (GPIOx_LCKR) */
#define GPIOG_LCKR GPIO_LCKR(GPIOG) #define GPIOG_LCKR GPIO_LCKR(GPIOG)
#define GPIOH_LCKR GPIO_LCKR(GPIOH) #define GPIOH_LCKR GPIO_LCKR(GPIOH)
#define GPIOI_LCKR GPIO_LCKR(GPIOI) #define GPIOI_LCKR GPIO_LCKR(GPIOI)
#define GPIOJ_LCKR GPIO_LCKR(GPIOJ)
#define GPIOK_LCKR GPIO_LCKR(GPIOK)
/* Alternate function low register (GPIOx_AFRL) */ /* Alternate function low register (GPIOx_AFRL) */
#define GPIOG_AFRL GPIO_AFRL(GPIOG) #define GPIOG_AFRL GPIO_AFRL(GPIOG)
#define GPIOH_AFRL GPIO_AFRL(GPIOH) #define GPIOH_AFRL GPIO_AFRL(GPIOH)
#define GPIOI_AFRL GPIO_AFRL(GPIOI) #define GPIOI_AFRL GPIO_AFRL(GPIOI)
#define GPIOJ_AFRL GPIO_AFRL(GPIOJ)
#define GPIOK_AFRL GPIO_AFRL(GPIOK)
/* Alternate function high register (GPIOx_AFRH) */ /* Alternate function high register (GPIOx_AFRH) */
#define GPIOG_AFRH GPIO_AFRH(GPIOG) #define GPIOG_AFRH GPIO_AFRH(GPIOG)
#define GPIOH_AFRH GPIO_AFRH(GPIOH) #define GPIOH_AFRH GPIO_AFRH(GPIOH)
#define GPIOI_AFRH GPIO_AFRH(GPIOI) #define GPIOI_AFRH GPIO_AFRH(GPIOI)
#define GPIOJ_AFRH GPIO_AFRH(GPIOJ)
#define GPIOK_AFRH GPIO_AFRH(GPIOK)
/**@}*/ /**@}*/
#endif #endif

4
include/libopencm3/stm32/f4/memorymap.h
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@ -108,7 +108,9 @@
#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB1 + 0x1800) #define GPIO_PORT_G_BASE (PERIPH_BASE_AHB1 + 0x1800)
#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB1 + 0x1C00) #define GPIO_PORT_H_BASE (PERIPH_BASE_AHB1 + 0x1C00)
#define GPIO_PORT_I_BASE (PERIPH_BASE_AHB1 + 0x2000) #define GPIO_PORT_I_BASE (PERIPH_BASE_AHB1 + 0x2000)
/* PERIPH_BASE_AHB1 + 0x2400 (0x4002 2400 - 0x4002 2FFF): Reserved */ #define GPIO_PORT_J_BASE (PERIPH_BASE_AHB1 + 0x2400)
#define GPIO_PORT_K_BASE (PERIPH_BASE_AHB1 + 0x2800)
/* PERIPH_BASE_AHB1 + 0x2C00 (0x4002 2C00 - 0x4002 2FFF): Reserved */
#define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000) #define CRC_BASE (PERIPH_BASE_AHB1 + 0x3000)
/* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 37FF): Reserved */ /* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 37FF): Reserved */
#define RCC_BASE (PERIPH_BASE_AHB1 + 0x3800) #define RCC_BASE (PERIPH_BASE_AHB1 + 0x3800)

6
include/libopencm3/stm32/f4/rcc.h
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@ -590,6 +590,8 @@ enum rcc_periph_clken {
RCC_GPIOG = _REG_BIT(0x30, 6), RCC_GPIOG = _REG_BIT(0x30, 6),
RCC_GPIOH = _REG_BIT(0x30, 7), RCC_GPIOH = _REG_BIT(0x30, 7),
RCC_GPIOI = _REG_BIT(0x30, 8), RCC_GPIOI = _REG_BIT(0x30, 8),
RCC_GPIOJ = _REG_BIT(0x30, 9),
RCC_GPIOK = _REG_BIT(0x30, 10),
RCC_CRC = _REG_BIT(0x30, 12), RCC_CRC = _REG_BIT(0x30, 12),
RCC_BKPSRAM = _REG_BIT(0x30, 18), RCC_BKPSRAM = _REG_BIT(0x30, 18),
RCC_CCMDATARAM = _REG_BIT(0x30, 20), RCC_CCMDATARAM = _REG_BIT(0x30, 20),
@ -673,6 +675,8 @@ enum rcc_periph_clken {
SCC_GPIOG = _REG_BIT(0x50, 6), SCC_GPIOG = _REG_BIT(0x50, 6),
SCC_GPIOH = _REG_BIT(0x50, 7), SCC_GPIOH = _REG_BIT(0x50, 7),
SCC_GPIOI = _REG_BIT(0x50, 8), SCC_GPIOI = _REG_BIT(0x50, 8),
SCC_GPIOJ = _REG_BIT(0x50, 9),
SCC_GPIOK = _REG_BIT(0x50, 10),
SCC_CRC = _REG_BIT(0x50, 12), SCC_CRC = _REG_BIT(0x50, 12),
SCC_FLTIF = _REG_BIT(0x50, 15), SCC_FLTIF = _REG_BIT(0x50, 15),
SCC_SRAM1 = _REG_BIT(0x50, 16), SCC_SRAM1 = _REG_BIT(0x50, 16),
@ -755,6 +759,8 @@ enum rcc_periph_rst {
RST_GPIOG = _REG_BIT(0x10, 6), RST_GPIOG = _REG_BIT(0x10, 6),
RST_GPIOH = _REG_BIT(0x10, 7), RST_GPIOH = _REG_BIT(0x10, 7),
RST_GPIOI = _REG_BIT(0x10, 8), RST_GPIOI = _REG_BIT(0x10, 8),
RST_GPIOJ = _REG_BIT(0x10, 9),
RST_GPIOK = _REG_BIT(0x10, 10),
RST_CRC = _REG_BIT(0x10, 12), RST_CRC = _REG_BIT(0x10, 12),
RST_DMA1 = _REG_BIT(0x10, 21), RST_DMA1 = _REG_BIT(0x10, 21),
RST_DMA2 = _REG_BIT(0x10, 22), RST_DMA2 = _REG_BIT(0x10, 22),

10
lib/stm32/common/exti_common_all.c
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@ -135,6 +135,16 @@ void exti_select_source(uint32_t exti, uint32_t gpioport)
case GPIOI: case GPIOI:
bits = 8; bits = 8;
break; break;
#endif
#if defined(GPIOJ) && defined(GPIO_PORT_J_BASE)
case GPIOJ:
bits = 9;
break;
#endif
#if defined(GPIOK) && defined(GPIO_PORT_K_BASE)
case GPIOK:
bits = 10;
break;
#endif #endif
} }