diff --git a/lib/stm32/nvic.c b/lib/cm3/nvic.c
similarity index 85%
rename from lib/stm32/nvic.c
rename to lib/cm3/nvic.c
index 84fa6749..db187b36 100644
--- a/lib/stm32/nvic.c
+++ b/lib/cm3/nvic.c
@@ -1,31 +1,9 @@
-/** @defgroup STM32F_nvic_file NVIC
-
-@ingroup STM32F_files
-
-@brief libopencm3 STM32F Nested Vectored Interrupt Controller
-
-@version 1.0.0
-
-@author @htmlonly © @endhtmlonly 2010 Thomas Otto
-@author @htmlonly © @endhtmlonly 2012 Fergus Noble
-
-@date 18 August 2012
-
-The STM32F series provides up to 68 maskable user interrupts for the STM32F10x
-series, and 87 for the STM32F2xx and STM32F4xx series.
-
-The NVIC registers are defined by the ARM standards but the STM32F series have some
-additional limitations
-@see Cortex-M3 Devices Generic User Guide
-@see STM32F10xxx Cortex-M3 programming manual
-
-LGPL License Terms @ref lgpl_license
-*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2010 Thomas Otto
* Copyright (C) 2012 Fergus Noble
+ * Copyright (C) 2012 Benjamin Vernoux
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
@@ -40,10 +18,32 @@ LGPL License Terms @ref lgpl_license
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see .
*/
+/** @defgroup CM3_nvic_file NVIC
+@ingroup CM3_files
+
+@brief libopencm3 Cortex Nested Vectored Interrupt Controller
+
+@version 1.0.0
+
+@author @htmlonly © @endhtmlonly 2010 Thomas Otto
+@author @htmlonly © @endhtmlonly 2012 Fergus Noble
+
+@date 18 August 2012
+
+Cortex processors provide 14 cortex-defined interrupts (NMI, usage faults,
+systicks etc.) and varying numbers of implementation defined interrupts
+(typically peripherial interrupts and DMA).
+
+@see Cortex-M3 Devices Generic User Guide
+@see STM32F10xxx Cortex-M3 programming manual
+
+LGPL License Terms @ref lgpl_license
+*/
/**@{*/
-#include
+#include
+#include
/*-----------------------------------------------------------------------------*/
/** @brief NVIC Enable Interrupt
@@ -153,7 +153,18 @@ Control Register (SCB_AIRCR), as done in @ref scb_set_priority_grouping.
void nvic_set_priority(u8 irqn, u8 priority)
{
- NVIC_IPR(irqn) = priority;
+ /* code from lpc43xx/nvic.c -- this is quite a hack and alludes to the
+ * negative interrupt numbers assigned to the system interrupts. better
+ * handling would mean signed integers. */
+ if(irqn>=NVIC_IRQ_COUNT)
+ {
+ /* Cortex-M system interrupts */
+ SCS_SHPR( (irqn&0xF)-4 ) = priority;
+ }else
+ {
+ /* Device specific interrupts */
+ NVIC_IPR(irqn) = priority;
+ }
}
/*-----------------------------------------------------------------------------*/
@@ -171,4 +182,3 @@ void nvic_generate_software_interrupt(u16 irqn)
NVIC_STIR |= irqn;
}
/**@}*/
-
diff --git a/lib/lpc43xx/nvic.c b/lib/lpc43xx/nvic.c
deleted file mode 100644
index 47933127..00000000
--- a/lib/lpc43xx/nvic.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * This file is part of the libopencm3 project.
- *
- * Copyright (C) 2010 Thomas Otto
- * Copyright (C) 2012 Fergus Noble
- * Copyright (C) 2012 Benjamin Vernoux
- *
- * This library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU Lesser General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public License
- * along with this library. If not, see .
- */
-#include
-#include
-
-void nvic_enable_irq(u8 irqn)
-{
- NVIC_ISER(irqn / 32) = (1 << (irqn % 32));
-}
-
-void nvic_disable_irq(u8 irqn)
-{
- NVIC_ICER(irqn / 32) = (1 << (irqn % 32));
-}
-
-u8 nvic_get_pending_irq(u8 irqn)
-{
- return NVIC_ISPR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
-}
-
-void nvic_set_pending_irq(u8 irqn)
-{
- NVIC_ISPR(irqn / 32) = (1 << (irqn % 32));
-}
-
-void nvic_clear_pending_irq(u8 irqn)
-{
- NVIC_ICPR(irqn / 32) = (1 << (irqn % 32));
-}
-
-u8 nvic_get_active_irq(u8 irqn)
-{
- return NVIC_IABR(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
-}
-
-u8 nvic_get_irq_enabled(u8 irqn)
-{
- return NVIC_ISER(irqn / 32) & (1 << (irqn % 32)) ? 1 : 0;
-}
-
-void nvic_set_priority(u8 irqn, u8 priority)
-{
- if(irqn>NVIC_M4_QEI_IRQ)
- {
- /* Cortex-M system interrupts */
- SCS_SHPR( (irqn&0xF)-4 ) = priority;
- }else
- {
- /* Device specific interrupts */
- NVIC_IPR(irqn) = priority;
- }
-}
-
-void nvic_generate_software_interrupt(u8 irqn)
-{
- if (irqn <= 239)
- NVIC_STIR |= irqn;
-}