cortex: FAULTMASK does not exist on armv6m.

This commit is contained in:
Guillaume Revaillot 2019-10-16 16:48:09 +02:00 committed by Karl Palsson
parent db6237cd1e
commit 9d15ac7ae7

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@ -91,6 +91,7 @@ static inline bool cm_is_masked_interrupts(void)
return result; return result;
} }
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief Cortex M Check if Fault interrupt is masked /** @brief Cortex M Check if Fault interrupt is masked
* *
@ -105,6 +106,7 @@ static inline bool cm_is_masked_faults(void)
__asm__ volatile ("MRS %0, FAULTMASK" : "=r" (result)); __asm__ volatile ("MRS %0, FAULTMASK" : "=r" (result));
return result; return result;
} }
#endif
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief Cortex M Mask interrupts /** @brief Cortex M Mask interrupts
@ -126,6 +128,7 @@ static inline uint32_t cm_mask_interrupts(uint32_t mask)
return old; return old;
} }
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/** @brief Cortex M Mask HardFault interrupt /** @brief Cortex M Mask HardFault interrupt
* *
@ -145,6 +148,7 @@ static inline uint32_t cm_mask_faults(uint32_t mask)
__asm__ __volatile__ ("MSR FAULTMASK, %0" : : "r" (mask)); __asm__ __volatile__ ("MSR FAULTMASK, %0" : : "r" (mask));
return old; return old;
} }
#endif
/**@}*/ /**@}*/