From 9d2e074b3d634dfe103dd50c8624c089a2a4da88 Mon Sep 17 00:00:00 2001 From: Thomas Otto Date: Sun, 28 Mar 2010 15:19:32 +0200 Subject: [PATCH] Cosmetic fixes. --- include/libopenstm32/dma.h | 1 + include/libopenstm32/nvic.h | 1 + include/libopenstm32/scb.h | 15 +++++++++++++++ lib/adc.c | 18 +++++++++--------- lib/nvic.c | 14 +++++++------- 5 files changed, 33 insertions(+), 16 deletions(-) diff --git a/include/libopenstm32/dma.h b/include/libopenstm32/dma.h index b1eb0521..389019f7 100644 --- a/include/libopenstm32/dma.h +++ b/include/libopenstm32/dma.h @@ -688,6 +688,7 @@ /* MA[31:0]: Memory address */ /* --- Generic values ------------------------------------------------------ */ + #define DMA_CHANNEL1 1 #define DMA_CHANNEL2 2 #define DMA_CHANNEL3 3 diff --git a/include/libopenstm32/nvic.h b/include/libopenstm32/nvic.h index 03ac38f0..bb2c35d8 100644 --- a/include/libopenstm32/nvic.h +++ b/include/libopenstm32/nvic.h @@ -64,6 +64,7 @@ /* --- IRQ channel numbers-------------------------------------------------- */ + /* Cortex M3 System Interrupts */ #define NVIC_NMI_IRQ -14 #define NVIC_HARD_FAULT_IRQ -13 diff --git a/include/libopenstm32/scb.h b/include/libopenstm32/scb.h index b0a3677e..17d892f5 100644 --- a/include/libopenstm32/scb.h +++ b/include/libopenstm32/scb.h @@ -75,6 +75,7 @@ /* --- SCB values ---------------------------------------------------------- */ /* --- SCB_CPUID values ---------------------------------------------------- */ + /* Implementer[31:24]: Implementer code */ #define SCP_CPUID_IMPLEMENTER_LSB 24 /* Variant[23:20]: Variant number */ @@ -87,6 +88,7 @@ #define SCP_CPUID_REVISION_LSB 0 /* --- SCB_ICSR values ----------------------------------------------------- */ + /* NMIPENDSET: NMI set-pending bit */ #define SCB_ICSR_NMIPENDSET (1 << 31) /* Bits [30:29]: reserved - must be kept cleared */ @@ -111,11 +113,13 @@ #define SCB_ICSR_VECTACTIVE_LSB 0 /* --- SCB_VTOR values ----------------------------------------------------- */ + /* Bits [31:30]: reserved - must be kept cleared */ /* TBLOFF[29:9]: Vector table base offset field */ #define SCB_VTOR_TBLOFF_LSB 9 /* inconsistent datasheet - LSB could be 11 */ /* --- SCB_AIRCR values ---------------------------------------------------- */ + /* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */ #define SCB_AIRCR_VECTKEYSTAT_LSB 16 /* ENDIANESS Data endianness bit */ @@ -137,6 +141,7 @@ #define SCB_AIRCR_VECTRESET (1 << 0) /* --- SCB_SCR values ------------------------------------------------------ */ + /* Bits [31:5]: reserved - must be kept cleared */ /* SEVEONPEND Send Event on Pending bit */ #define SCB_SCR_SEVEONPEND (1 << 4) @@ -148,6 +153,7 @@ /* Bit 0: reserved - must be kept cleared */ /* --- SCB_CCR values ------------------------------------------------------ */ + /* Bits [31:10]: reserved - must be kept cleared */ /* STKALIGN */ #define SCB_CCR_STKALIGN (1 << 9) @@ -165,6 +171,7 @@ #define SCB_CCR_NONBASETHRDENA (1 << 0) /* --- SCB_SHPR1 values ---------------------------------------------------- */ + /* Bits [31:24]: reserved - must be kept cleared */ /* PRI_6[23:16]: Priority of system handler 6, usage fault */ #define SCB_SHPR1_PRI_6_LSB 16 @@ -174,11 +181,13 @@ #define SCB_SHPR1_PRI_4_LSB 0 /* --- SCB_SHPR2 values ---------------------------------------------------- */ + /* PRI_11[31:24]: Priority of system handler 11, SVCall */ #define SCB_SHPR2_PRI_11_LSB 24 /* Bits [23:0]: reserved - must be kept cleared */ /* --- SCB_SHPR3 values ---------------------------------------------------- */ + /* PRI_15[31:24]: Priority of system handler 15, SysTick exception */ #define SCB_SHPR3_PRI_15_LSB 24 /* PRI_14[23:16]: Priority of system handler 14, PendSV */ @@ -186,6 +195,7 @@ /* Bits [15:0]: reserved - must be kept cleared */ /* --- SCB_SHCSR values ---------------------------------------------------- */ + /* Bits [31:19]: reserved - must be kept cleared */ /* USGFAULTENA: Usage fault enable */ #define SCB_SHCSR_USGFAULTENA (1 << 18) @@ -220,6 +230,7 @@ #define SCB_SHCSR_MEMFAULTACT (1 << 0) /* --- SCB_CFSR values ----------------------------------------------------- */ + /* Bits [31:26]: reserved - must be kept cleared */ /* DIVBYZERO: Divide by zero usage fault */ #define SCB_CFSR_DIVBYZERO (1 << 25) @@ -261,6 +272,7 @@ #define SCB_CFSR_IACCVIOL (1 << 0) /* --- SCB_HFSR values ----------------------------------------------------- */ + /* DEBUG_VT: reserved for debug use */ #define SCB_HFSR_DEBUG_VT (1 << 31) /* FORCED: Forced hard fault */ @@ -271,12 +283,15 @@ /* Bit 0: reserved - must be kept cleared */ /* --- SCB_MMFAR values ---------------------------------------------------- */ + /* MMFAR [31:0]: Memory management fault address */ /* --- SCB_BFAR values ----------------------------------------------------- */ + /* BFAR [31:0]: Bus fault address */ /* --- SCB functions ------------------------------------------------------- */ + /* TODO: */ #endif diff --git a/lib/adc.c b/lib/adc.c index 8723996c..d2623d84 100644 --- a/lib/adc.c +++ b/lib/adc.c @@ -286,13 +286,13 @@ void adc_set_conversion_time(u32 adc, u8 channel, u8 time) if (channel < 10) { reg32 = ADC_SMPR2(adc); reg32 &= ~(0b111 << (channel * 3)); - reg32 |= (time << (channel *3)); + reg32 |= (time << (channel * 3)); ADC_SMPR2(adc) = reg32; } else { reg32 = ADC_SMPR1(adc); - reg32 &= ~(0b111 << ((channel-10) *3)); - reg32 |= (time << ((channel-10) *3)); + reg32 &= ~(0b111 << ((channel-10) * 3)); + reg32 |= (time << ((channel-10) * 3)); ADC_SMPR1(adc) = reg32; } } @@ -302,12 +302,12 @@ void adc_set_conversion_time_on_all_channels(u32 adc, u8 time) u32 reg32 = 0; u8 i; - for (i=0; i<=9; i++) { + for (i = 0; i <= 9; i++) { reg32 |= (time << (i * 3)); } ADC_SMPR2(adc) = reg32; - for (i=10; i<=17; i++) { + for (i = 10; i <= 17; i++) { reg32 |= (time << ((i-10) * 3)); } ADC_SMPR1(adc) = reg32; @@ -343,11 +343,11 @@ void adc_set_regular_sequence(u32 adc, u8 length, u8 channel[]) return; for (i=1; i<=length; i++) { - if (i<=6) + if (i <= 6) reg32_3 |= (channel[i-1] << ((i-1) * 5)); - if ((i>6) & (i<=12)) + if ((i > 6) & (i <= 12)) reg32_2 |= (channel[i-6-1] << ((i-6-1) * 5)); - if ((i>12) & (i<=16)) + if ((i > 12) & (i <= 16)) reg32_1 |= (channel[i-12-1] << ((i-12-1) * 5)); } reg32_1 |= ((length -1) << ADC_SQR1_L_LSB); @@ -366,7 +366,7 @@ void adc_set_injected_sequence(u32 adc, u8 length, u8 channel[]) if (length > 4) return; - for (i=1; i<=length; i++) { + for (i = 1; i <= length; i++) { reg32 |= (channel[i-1] << ((i-1) * 5)); } reg32 |= ((length-1) << ADC_JSQR_JL_LSB); diff --git a/lib/nvic.c b/lib/nvic.c index 0c568b08..4dffe45c 100644 --- a/lib/nvic.c +++ b/lib/nvic.c @@ -25,7 +25,7 @@ void nvic_enable_irq(u8 irqn) NVIC_ISER(0) |= (1 << irqn); if ((irqn >= 32) & (irqn < 64)) NVIC_ISER(1) |= (1 << (irqn - 32)); - if ((irqn >=64) & (irqn < 68)) + if ((irqn >= 64) & (irqn < 68)) NVIC_ISER(2) |= (1 << (irqn - 64)); } @@ -35,7 +35,7 @@ void nvic_disable_irq(u8 irqn) NVIC_ICER(0) |= (1 << irqn); if ((irqn >= 32) & (irqn < 64)) NVIC_ICER(1) |= (1 << (irqn - 32)); - if ((irqn >=64) & (irqn < 68)) + if ((irqn >= 64) & (irqn < 68)) NVIC_ICER(2) |= (1 << (irqn - 64)); } @@ -45,7 +45,7 @@ u8 nvic_get_pending_irq(u8 irqn) return (NVIC_ISPR(0) & (1 << irqn)); if ((irqn >= 32) & (irqn < 64)) return (NVIC_ISPR(1) & (1 << (irqn - 32))); - if ((irqn >=64) & (irqn < 68)) + if ((irqn >= 64) & (irqn < 68)) return (NVIC_ISPR(2) & (1 << (irqn - 64))); return 0; } @@ -56,7 +56,7 @@ void nvic_set_pending_irq(u8 irqn) NVIC_ISPR(0) |= (1 << irqn); if ((irqn >= 32) & (irqn < 64)) NVIC_ISPR(1) |= (1 << (irqn - 32)); - if ((irqn >=64) & (irqn < 68)) + if ((irqn >= 64) & (irqn < 68)) NVIC_ISPR(2) |= (1 << (irqn - 64)); } @@ -66,7 +66,7 @@ void nvic_clear_pending_irq(u8 irqn) NVIC_ICPR(0) |= (1 << irqn); if ((irqn >= 32) & (irqn < 64)) NVIC_ICPR(1) |= (1 << (irqn - 32)); - if ((irqn >=64) & (irqn < 68)) + if ((irqn >= 64) & (irqn < 68)) NVIC_ICPR(2) |= (1 << (irqn - 64)); } @@ -76,7 +76,7 @@ u8 nvic_get_active_irq(u8 irqn) return (NVIC_IABR(0) & (1 << irqn)); if ((irqn >= 32) & (irqn < 64)) return (NVIC_IABR(1) & (1 << (irqn - 32))); - if ((irqn >=64) & (irqn < 68)) + if ((irqn >= 64) & (irqn < 68)) return (NVIC_IABR(2) & (1 << (irqn - 64))); return 0; } @@ -87,7 +87,7 @@ u8 nvic_get_irq_enabled(u8 irqn) return (NVIC_ISER(0) & (1 << irqn)); if ((irqn >= 32) & (irqn < 64)) return (NVIC_ISER(1) & (1 << (irqn - 32))); - if ((irqn >=64) & (irqn < 68)) + if ((irqn >= 64) & (irqn < 68)) return (NVIC_ISER(2) & (1 << (irqn - 64))); return 0; }