diff --git a/include/libopenstm32/rcc.h b/include/libopenstm32/rcc.h
index 7ba41086..0c544c63 100644
--- a/include/libopenstm32/rcc.h
+++ b/include/libopenstm32/rcc.h
@@ -378,5 +378,9 @@ void rcc_osc_bypass_enable(osc_t osc);
 void rcc_osc_bypass_disable(osc_t osc);
 void rcc_enable_peripheral_clock(volatile u32 *reg, u32 peripheral_en);
 void rcc_disable_peripheral_clock(volatile u32 *reg, u32 peripheral_en);
+void rcc_set_sysclk_source(u32 clk);
+void rcc_set_pll_multiplication_factor(u32 mul);
+void rcc_set_pll_source(u32 pllsrc);
+void rcc_set_pllxtpre(u32 pllxtpre);
 
 #endif
diff --git a/lib/rcc.c b/lib/rcc.c
index 30ad8026..390c795b 100644
--- a/lib/rcc.c
+++ b/lib/rcc.c
@@ -234,3 +234,38 @@ void rcc_disable_peripheral_clock(volatile u32 *reg, u32 peripheral_en)
 	*reg &= ~peripheral_en;
 }
 
+void rcc_set_sysclk_source(u32 clk)
+{
+	u32 reg32;
+
+	reg32 = RCC_CFGR;
+	reg32 &= ~((1 << 1) | (1 << 0));
+	RCC_CFGR = (reg32 | clk);
+}
+
+void rcc_set_pll_multiplication_factor(u32 mul)
+{
+	u32 reg32;
+
+	reg32 = RCC_CFGR;
+	reg32 &= ~((1 << 21) | (1 << 20) | (1 << 19) | (1 << 18));
+	RCC_CFGR = (reg32 | (mul << 18));
+}
+
+void rcc_set_pll_source(u32 pllsrc)
+{
+	u32 reg32;
+
+	reg32 = RCC_CFGR;
+	reg32 &= ~(1 << 16);
+	RCC_CFGR = (reg32 | (pllsrc << 16));
+}
+
+void rcc_set_pllxtpre(u32 pllxtpre)
+{
+	u32 reg32;
+
+	reg32 = RCC_CFGR;
+	reg32 &= ~(1 << 17);
+	RCC_CFGR = (reg32 | (pllxtpre << 17));
+}